Isolated Bipolar Bidirectional Three-Port Converter with Voltage Self-Balancing Capability for Bipolar DC Microgrids

Abstract

Bipolar DC microgrids gain significant attention for their flexible structure, high power supply reliability, and strong compatibility with distributed power sources. However, inter-pole voltage imbalance undermines system operational stability. An isolated bipolar bidirectional three-port converter with voltage self-balancing capability is proposed in this paper, which can serve as the interface between the energy storage system and bipolar bus while achieving automatic voltage balance between poles. Unlike traditional bidirectional grid-connected voltage balancers (VBs), the proposed converter requires no additional voltage monitoring or complex control systems. The operating modes, soft-switching boundary conditions, and inter-pole voltage self-balancing mechanism are elaborated. A 1 kW experimental prototype has been built to validate the theoretical analysis of the proposed converter.

1. Introduction

Bipolar DC microgrid has become a research hotspot because its bus architecture is convenient for distributed energy, energy storage devices, and DC load access, and has the technical advantages of flexible voltage level, low transmission loss, and high power quality [1,2]. Stable bus voltage and balanced inter-pole voltage are key guarantees for the stable and reliable operation of bipolar DC microgrids [3,4,5]. During islanded operation, the bus voltage stability is maintained by the converter connected to the energy storage system, while the inter-pole voltage balance relies on a dedicated voltage balancer [6,7,8,9]. The topologies of common voltage balancers can be divided into non-isolated and isolated types. The derivation of non-isolated VBs is mostly based on basic bidirectional topologies [10,11,12,13] and three-level topologies [14,15,16,17], while typical isolated VBs are mainly realized through dual-active-bridge (DAB) topologies [18,19,20,21,22,23,24]. In the research of isolated VB topologies, a VB topology based on three-level DAB converter is proposed in [19,20], which achieves output voltage balancing by controlling the charging/discharging processes of voltage divider capacitors through modulation of switching sequences in the three-level DAB converter. Another isolated VB topology is proposed in [20,21,22,23], which connects two triple-active-bridge (TAB) series at the output side. This converter employs two independent control variables to regulate the bipolar output power, thereby achieving output voltage balancing. However, the inter-pole voltage balancing in the aforementioned topologies relies on complex voltage monitoring and feedback control, which inherently suffer from slow dynamic response and complex control circuit. To address this problem, a series of voltage self-balancing topologies are proposed in [24,25,26], which clamps the inter-pole voltage to the same value through indirect parallel connection of capacitors, but it only supports unidirectional energy flow. A series of topologies that support bidirectional energy flow and have the ability of inter-pole voltage self-balancing are proposed in [27,28]. These topologies are derived from the DAB converter, thus retaining its bidirectional energy flow characteristic. Meanwhile, they utilize the volt-second balance principle of the balancing inductor to achieve automatic balancing of the output voltage.

An isolated bipolar bidirectional three-port converter based on integrated balancing inductor is proposed in this paper. The presented converter not only interfaces energy storage systems with bipolar DC buses but also achieves automatic inter-pole voltage balancing. Furthermore, the multi-port power supply structure significantly enhances system reliability while enabling flexible power flow control and bidirectional energy transfer. The operating modes of the converter are elaborated in detail, and the quantitative model for soft-switching conditions is established. Finally, the theoretical analysis is verified by a 1 kW experimental prototype.

2. Working Principle

The proposed topology is shown in Figure 1. Port 1, Port 2, and Port 3 of the full bridge are connected by a three-winding high-frequency transformer with a turns ratio of n₁:n₂:n₃. The leakage inductors of the transformer are L_pk’, L_sk’, and L_tk’ respectively. Port 1 and Port 2 are connected to the energy storage batteries V_ESS1 and V_ESS2 respectively, and Port 3 is connected to the bipolar buses. The upper and lower switches within the same bridge arm of each port operate in complementary conduction, while the diagonal switches within the bridge arm conduct simultaneously. φ₁₂, φ₁₃, and φ₂₃ represent the phase shift angles between Port 1 and Port 2, Port 1 and Port 3, and Port 2 and Port 3, respectively. Among them, φ₂₃ = φ₁₃−φ₁₂. The magnitude and direction of power transfer can be controlled by adjusting the phase shift angle, enabling energy transmission from the leading-phase port to the lagging-phase port.

To facilitate the analysis of power flow, the equivalent circuit model of the converter after “Y–∆” transformation is shown in Figure 2. v₁’, v₂’, and v₃’ are the input voltages before the reduction, respectively; v₁, v₂, and v₃ are the input voltages after the reduction, respectively; L_pk, L_sk, and L_tk are the equivalent values of the inductors after the reduction, respectively; L₁₂, L₁₃, and L₂₃ are the equivalent values of the inductors after the “Y–∆” transformation, respectively; and i_L12, i_L13, and i_L23 are the corresponding inductor current values. To simplify the analysis, the following assumptions are made: (1) All switches and diodes are ideal devices, and the parallel diodes and capacitors of switches are their body diodes and junction capacitors. (2) The resonant frequencies of the parasitic capacitors and the leakage inductors are far less than the switching frequency of the converter.

Taking the dual-input single-output mode (the energy storage batteries V_ESS1 and V_ESS2 supply power to the bipolar bus) as an example, the isolated three-port converter has 18 operating modes within one switching period. The key waveforms within one switching period are shown in Figure 3, and the specific modal analysis is as follows:

Mode 1 (t₀–t₁): The switches P₁ and P₄ are turned off simultaneously. The leakage inductor current i_Lpk charges the parasitic capacitors C₁₁ and C₁₄ and discharges the parasitic capacitors C₁₂ and C₁₃. At this time, the switches S₁ and S₄ in Port 2 are turned on, and the leakage inductor current i_Lsk gradually rises. The body diodes D₃₁ and D₃₄ in Port 3 are turned on.

Mode 2 (t₁–t₂): The parasitic capacitors C₁₁ and C₁₄ are charged to V_ESS1, and the parasitic capacitors C₁₂ and C₁₃ are discharged to zero. The body diodes D₁₂ and D₁₃ of the switches P₂ and P₃ are turned on for freewheeling, and the leakage inductor current i_Lpk starts to decrease. When the drive signals of the switches P₂ and P₃ arrive, since the leakage inductor current i_Lpk is positive, it still freewheels through the body diodes D₁₂ and D₁₃. At this time, there is a power backflow phenomenon at Port 1. The operating characteristics of the other two ports remain unchanged.

Mode 3 (t₂–t₃): When the leakage inductor current i_Lpk drops to zero, the drive signals of the switches P₂ and P₃ are still at a high level, and natural commutation occurs. Due to the clamping effect of the body diodes D₁₂ and D₁₃, the switches P₂ and P₃ are turned on with zero voltage switching (ZVS). The leakage inductor current i_Lpk continues to decrease; the operating characteristics of the other two ports remain unchanged.

Mode 4 (t₃–t₄): The switches S₁ and S₄ are turned off simultaneously. The leakage inductor current i_Lsk charges the parasitic capacitors C₂₁ and C₂₄ and discharges the parasitic capacitors C₁₂ and C₁₃. At this time, the switches P₂ and P₃ in Port 1 are turned on, the leakage inductor current i_Lpk continues to decrease, and the body diodes D₃₁ and D₃₄ in Port 3 are turned on.

Mode 5 (t₄–t₅): The parasitic capacitors C₂₁ and C₂₄ are charged to V_ESS2, and the parasitic capacitors C₂₂ and C₂₃ are discharged to zero. The body diodes D₂₂ and D₂₃ of the switches S₂ and S₃ are turned on for freewheeling, and the leakage inductor current i_Lsk starts to decrease. When the drive signals of the switches S₂ and S₃ arrive, since the leakage inductor current i_Lsk is positive, it still freewheels through the body diodes D₂₂ and D₂₃. At this time, Port 2 absorbs power, and the operating characteristics of the other two ports remain unchanged.

Mode 6 (t₅–t₆): At this time, the leakage inductor current i_Ltk drops to zero, and the current starts to flow in the reverse direction. The drive signals of the switches T₁ and T₄ in Port 3 are at a high level, and natural commutation occurs. Due to the clamping effect of the body diodes D₃₁ and D₃₄, the switches T₁ and T₄ are turned on with ZVS. The leakage inductor current i_Lsk continues to decrease, but it is still positive, so it still freewheels through the body diodes D₂₂ and D₂₃. Port 3 supplies power, whereas Port 2 remains in power absorbing state.

Mode 7 (t₆–t₇): The switches T₁ and T₄ are turned off simultaneously. The leakage inductor current i_Ltk charges the parasitic capacitors C₃₁ and C₃₄ and discharges the parasitic capacitors C₃₂ and C₃₃ at the same time. The operating characteristics of the other two ports remain unchanged.

Mode 8 (t₇–t₈): The parasitic capacitors C₃₁ and C₃₄ are charged to (V_p + V_n), and the parasitic capacitors C₃₂ and C₃₃ are discharged to zero. The body diodes D₃₂ and D₃₄ of the switches T₂ and T₃ are turned on for freewheeling. The operating characteristics of the other two ports remain unchanged.

Mode 9 (t₈–t₉): At this time, the leakage inductor current i_Lsk drops to zero, and the current starts to flow in the reverse direction. The drive signals of the switches S₂ and S₃ in Port 2 are at a high level, and natural commutation occurs. Due to the clamping effect of the body diodes D₂₂ and D₂₃, the switches S₂ and S₃ are turned on with ZVS, and Port 2 supplies power.

Starting from t₉, the converter starts working for another half period. Its operating mode is symmetrical to the above half period, and further elaboration on it is not necessary.

3. Performance Characteristics

3.1. Analysis of Transmitted Power

Based on the equivalent circuit shown in Figure 2 and combined with the modal analysis, the magnitudes of the powers P₁₃, P₁₂, and P₂₃ transmitted on the equivalent inductors L₁₃, L₁₂, and L₂₃ can be calculated, as shown in Equation (1); and the actual transmitted powers P₁₃, P₁₂, and P₂₃ of each port can be obtained by superposition based on the KCL circuit theorem. The flow direction and magnitude of the port power can be controlled by adjusting the phase shift angles φ₁₂ and φ₂₃, as shown in Figure 4a,b.

$$\left\{\begin{array}{l}{P}_{12}={\displaystyle \frac{1}{2\pi }}{\displaystyle {\int }_0^{2\pi }{i}_{{\mathrm{L}}_{12}}(\theta )}(v_1-v_2)d\theta ={\displaystyle \frac{V_1{V}_2}{\pi w{L}_{12}}}{\phi }_{12}(\pi -{\phi }_{12})\\ P_{13}={\displaystyle \frac{1}{2\pi }}{\displaystyle {\int }_0^{2\pi }{i}_{{\mathrm{L}}_{13}}(\theta )}(v_1-v_3)d\theta ={\displaystyle \frac{V_1{V}_3}{\pi w{L}_{13}}}{\phi }_{13}(\pi -{\phi }_{13})\\ P_{23}={\displaystyle \frac{1}{2\pi }}{\displaystyle {\int }_0^{2\pi }{i}_{{\mathrm{L}}_{23}}(\theta )}(v_2-v_3)d\theta ={\displaystyle \frac{V_2{V}_3}{\pi w{L}_{23}}}{\phi }_{23}(\pi -{\phi }_{23})\\ P_1=P_{12}+P_{13},P_2=-P_{12}+P_{23},P_3=P_{13}+P_{23}\end{array}\right.$$

(1)

When Port 3 is connected to a load simulating the operation of bipolar bus, the forward power transfer relationship can be expressed by Equation (2). The output voltage exhibits symmetrical characteristics with respect to the phase shift angles φ₁₂ and φ₂₃, as shown in Figure 4c. The existence of power backflow leads to additional losses with increasing phase shift angle; thus, the phase shift angle is generally constrained to the range of [0, π/2].

$$V_{C_{\mathrm{p}}}=V_{C_{\mathrm{n}}}={\displaystyle \frac{R_{\mathrm{p}}{R}_{\mathrm{n}}[\frac{2{\phi }_{13}(\pi -{\phi }_{13})}{2{\pi }^2{f}_{\mathrm{s}}{L}_{13}}{V}_{C_1}+\frac{2{\phi }_{23}(\pi -{\phi }_{23})}{2{\pi }^2{f}_{\mathrm{s}}{L}_{23}}{V}_{C_2}]}{R_{\mathrm{p}}+R_{\mathrm{n}}}}$$

(2)

In Equation (2), V_Cp, V_Cn, V_C1, and V_C2 represent the voltages of capacitors C_p, C_n, C₁, and C₂ respectively; R_p and R_n represent the equivalent loads of the bipolar bus; and f_s represents the switching frequency.

Similarly, the reverse power transmission relationship can be expressed as Equation (3):

$$\left\{\begin{array}{l}{V}_{C_1}={\displaystyle \frac{b{R}_{\mathrm{b}1}+a\cdot c{R}_{\mathrm{b}1}{R}_{\mathrm{b}2}}{1+a^2{R}_{\mathrm{b}1}{R}_{\mathrm{b}2}}}(V_{C_{\mathrm{p}}}+V_{C_{\mathrm{n}}})\\ V_{C_2}={\displaystyle \frac{c{R}_{\mathrm{b}2}-a\cdot b{R}_{\mathrm{b}1}{R}_{\mathrm{b}2}}{1+a^2{R}_{\mathrm{b}1}{R}_{\mathrm{b}2}}}(V_{C_{\mathrm{p}}}+V_{C_{\mathrm{n}}})\\ a={\displaystyle \frac{\left|{\phi }_{12}\right|(\pi -\left|{\phi }_{12}\right|)}{2{\pi }^2{f}_{\mathrm{s}}{L}_{12}}},b={\displaystyle \frac{\left|{\phi }_{13}\right|(\pi -\left|{\phi }_{13}\right|)}{2{\pi }^2{f}_{\mathrm{s}}{L}_{13}}}c={\displaystyle \frac{\left|{\phi }_{23}\right|(\pi -\left|{\phi }_{23}\right|)}{2{\pi }^2{f}_{\mathrm{s}}{L}_{23}}}\end{array}\right.$$

(3)

In Equation (3), R_b1 and R_b represent the equivalent internal resistances of the batteries V_ESS1 and V_ESS2, respectively.

3.2. Analysis of Voltage and Current Stress

According to the working principle of the converter, the voltage stress of the switches in each full-bridge port is the corresponding port voltage, as shown in Equation (4).

$$\left\{\begin{array}{l}{V}_{{\mathrm{P}}_1}~V_{{\mathrm{P}}_4}==V_{{\mathrm{ESS}}_1}\\ V_{{\mathrm{S}}_1}~V_{{\mathrm{S}}_4}=V_{{\mathrm{ESS}}_2}\\ V_{{\mathrm{T}}_1}~V_{{\mathrm{T}}_4}=V_{\mathrm{p}}+V_{\mathrm{n}}\end{array}\right.$$

(4)

In Equation (4), V_P1~V_P4, V_S1~V_S4, V_T1~V_T4 are the port voltages of the switches, respectively; V_p is the voltage between the P-Z pole; and V_n is the voltage between the Z-N pole.

The current stress of the switches in each full-bridge port is the leakage inductor current of the corresponding port before turn-off. According to the power transmission relationship of the converter and the KCL principle, let w = 2πf_s. The leakage inductor current of each port can be calculated, and the current stress of the switches are shown in Equation (5).

$$\left\{\begin{array}{l}{i}_{{\mathrm{P}}_1}~i_{{\mathrm{P}}_4}={\displaystyle \frac{{\phi }_{13}(\pi -{\phi }_{13})}{w{L}_{13}}}(V_{\mathrm{p}}+V_{\mathrm{n}})+{\displaystyle \frac{{\phi }_{12}(\pi -{\phi }_{12})}{w{L}_{12}}}{V}_{{\mathrm{ESS}}_2}\\ i_{{\mathrm{S}}_1}~i_{{\mathrm{S}}_4}={\displaystyle \frac{{\phi }_{23}(\pi -{\phi }_{23})}{w{L}_{23}}}(V_{\mathrm{p}}+V_{\mathrm{n}})-{\displaystyle \frac{{\phi }_{12}(\pi -{\phi }_{12})}{w{L}_{12}}}{V}_{{\mathrm{ESS}}_1}\\ i_{{\mathrm{T}}_1}~i_{{\mathrm{T}}_4}={\displaystyle \frac{{\phi }_{23}(\pi -{\phi }_{23})}{w{L}_{23}}}{V}_{{\mathrm{ESS}}_2}+{\displaystyle \frac{{\phi }_{13}(\pi -{\phi }_{13})}{w{L}_{13}}}{V}_{{\mathrm{ESS}}_1}\end{array}\right.$$

(5)

3.3. Analysis of the Voltage Self-Balancing Mechanism

3.3.1. The Principle of the Inter-Pole Voltage Self-Balancing

When the switch T₄ is turned on, the balancing inductor L is connected in parallel with the capacitor C_n through the switch T₄, and the voltage on the balancing inductor L is V_L = −V_n, as shown in Figure 5a. When the switch T₃ is turned on, the balancing inductor L is connected in parallel with the capacitor C_p through the switch T₃, and the voltage on the balancing inductor L is V_L = V_p, as shown in Figure 5b. The switches T₃ and T₄ on the same bridge arm operate complementarily, both conducting for half of the switching period (that is, T₊ =T₋ = T_s/2, where T₊ and T₋ are the conduction times of the positive and negative half-periods, respectively, and T_s is the switching period), as shown in Figure 5c. According to the inductor volt-second balance principle, the voltages of the bipolar output ports are clamped to the same level, thereby achieving automatic voltage balancing between the poles.

3.3.2. Balancing Inductor Design

Due to the existence of the balancing inductor, the power of the bipolar bus can be redistributed. Under unbalanced load conditions, the average current of the balancing inductor is not zero, and its relationship with the unbalanced power is shown in Equation (6). Let ΔP = P_n − P_p, where P_p and P_n are the load powers of the positive and negative poles, respectively:

$$i_{\mathrm{L}}=i_{\mathrm{n}}-i_{\mathrm{p}}={\displaystyle \frac{P_{\mathrm{n}}}{V_{\mathrm{n}}}}-{\displaystyle \frac{P_{\mathrm{p}}}{V_{\mathrm{p}}}}={\displaystyle \frac{2\mathrm{\Delta }P}{V_{\mathrm{dc}}}}$$

(6)

In Equation (6), i_L is the average current flowing through the balancing inductor. i_n and i_p are the load currents of the positive and negative poles, respectively.

Within one switching period, the current ripple of the balancing inductor L is shown in Equation (7):

$$\mathrm{\Delta }{i}_L={\displaystyle \frac{1}{2}}\cdot {\displaystyle \frac{V_{\mathrm{dc}}}{2L}}\cdot {\displaystyle \frac{T_{\mathrm{s}}}{2}}$$

(7)

From Equations (6) and (7), the constraint condition of the inductor can be derived as shown in Equation (8):

$$L\ge {\displaystyle \frac{V_{\mathrm{dc}}^2{T}_{\mathrm{s}}}{16\xi \mathrm{\Delta }P}}$$

(8)

Among them, $\xi$ is the current ripple coefficient, and the common value is 5%; ∆P represents the processed unbalanced power, calculated based on the worst-case scenario (i.e., one pole at full-load while the other pole at no-load).

3.3.3. Analysis of the Voltage Self-Balancing Ability of the Proposed Converter

To characterize the regulation characteristics of the proposed converter under bipolar bus unbalance conditions, the following model is established:

P, N, and Z represent the three buses of the bipolar DC microgrid, and r_p, r_z, and r_n are the equivalent line impedances, as shown in Figure 6. Assume that the output voltage amplitudes of the converter at this time are v_p and v_n. The currents flowing through the bipolar buses are i_p, i_z, and i_n. The voltage amplitudes between the bipolar buses are v_lp and v_ln. There is an unbalanced voltage between the poles, and the voltage difference is ∆V. The power that can be processed by the converter is P. The self-balancing power is defined as the magnitude of power balanced by the converter under the inter-pole unbalanced voltage. To simplify the analysis process, the parasitic parameters of the converter devices are ignored.

To simplify the analysis, the equivalent line impedance is assumed to be equal to r_p = r_n = r_z = r. According to the KVL principle, the relationship between the output voltage of the converter and the bipolar buses voltage with respect to the line impedance is shown in Equation (9):

$$\left\{\begin{array}{l}{v}_{\mathrm{p}}=v_{\mathrm{lp}}+i_{\mathrm{p}}r+(i_{\mathrm{p}}-i_{\mathrm{n}})r\\ v_{\mathrm{n}}=v_{\ln }+i_{\mathrm{n}}r-(i_{\mathrm{p}}-i_{\mathrm{n}})r\end{array}\right.$$

(9)

The power equation of the proposed converter is shown in Equation (10), where D₁₃ = j₁₃/p and D₂₃ = j ₂₃/p:

$$P={\displaystyle \frac{D_{13}(1-D_{13})V_{\mathrm{ESS}1}}{2f_{\mathrm{s}}{L}_{13}}}(v_{\mathrm{p}}+v_{\mathrm{n}})+{\displaystyle \frac{D_{23}(1-D_{23})V_{\mathrm{ESS}2}}{2f_{\mathrm{s}}{L}_{23}}}(v_{\mathrm{p}}+v_{\mathrm{n}})$$

(10)

Due to the volt-second balance of the inductor, the output voltages of the converter can be maintained as v_p = v_n. From Equations (9) and (10), the current magnitude relationship of different connection points can be obtained as shown in Equation (11).

$$\left\{\begin{array}{l}{i}_{\mathrm{p}}={\displaystyle \frac{1}{2r}}[{\displaystyle \frac{P}{\alpha }}-(v_{\mathrm{lp}}+v_{\ln })-{\displaystyle \frac{v_{\mathrm{lp}}-v_{\ln }}{3}}]={\displaystyle \frac{1}{2r}}({\displaystyle \frac{P}{\alpha }}-v_{\mathrm{dc}}-{\displaystyle \frac{\mathrm{\Delta }v}{3}})\\ i_{\mathrm{n}}={\displaystyle \frac{1}{2r}}[{\displaystyle \frac{P}{\alpha }}-(v_{\mathrm{lp}}+v_{\ln })+{\displaystyle \frac{v_{\mathrm{lp}}-v_{\ln }}{3}}]={\displaystyle \frac{1}{2r}}({\displaystyle \frac{P}{\alpha }}-v_{\mathrm{dc}}+{\displaystyle \frac{\mathrm{\Delta }v}{3}})\\ \alpha ={\displaystyle \frac{D_{13}(1-D_{13})}{2f_{\mathrm{s}}{L}_{13}}}{V}_{\mathrm{ESS}1}+{\displaystyle \frac{D_{23}(1-D_{23})}{2f_{\mathrm{s}}{L}_{23}}}{V}_{\mathrm{ESS}2}\\ v_{\mathrm{dc}}=v_{\mathrm{lp}}+v_{\ln },\mathrm{\Delta }v=v_{\mathrm{lp}}-v_{\ln }\end{array}\right.$$

(11)

Therefore, when there is a deviation in the buses, the unbalanced power processed by the converter is calculated as shown in Equation (12), which describes the relationship between the balanced power and the external environment (the voltage difference between the poles and the line impedance) and the internal environment (converter real-time processing power).

$$\begin{array}{c}\mathrm{\Delta }P=v_{\mathrm{p}}{i}_{\mathrm{p}}-v_{\mathrm{n}}{i}_{\mathrm{n}}=v_{\mathrm{lp}}{i}_{\mathrm{p}}-v_{\ln }{i}_{\mathrm{n}}+2r(i_{\mathrm{p}}+i_{\mathrm{n}})(i_{\mathrm{p}}-i_{\mathrm{n}})\\ =-{\displaystyle \frac{\mathrm{\Delta }v}{6r}}\cdot {\displaystyle \frac{P}{\frac{D_{13}(1-D_{13})}{2f_{\mathrm{s}}{L}_{13}}{V}_{\mathrm{ESS}1}+\frac{D_{23}(1-D_{23})}{2f_{\mathrm{s}}{L}_{23}}{V}_{\mathrm{ESS}2}}}\end{array}$$

(12)

The comparison of simulation and theoretical calculation results of the converter under different unbalanced voltages is shown in Figure 7. It can be seen from the figure that the error between the theory and the simulation is small, which verifies the correctness of Equation (12). The main reason for the error is the influence of the capacitor and inductor ripple of the converter.

However, when the unbalanced power to be processed exceeds the rated power range of the converter, there will be a deviation between v_p and v_n. The main reason is that the conduction state of the switching periods changes during the dead time, resulting in inconsistent durations of the positive and negative periods of the balancing inductor voltage. The additional unbalanced power will be regulated by the balancing inductor, flowing from the bus with higher voltage to the bus with lower voltage. As shown in Figure 8, the voltage of the N-pole is higher than that of the P-pole. When the switch T₄ is turned off, the current of the balancing inductor will continue to flow through the body diode of the switch T₂, and the duration of the positive half-period of the balancing inductor voltage will be 2T_d longer than that of the negative half-period. According to the volt-second balance principle of the inductor, the following Equation (13) can be obtained:

$$\left\{\begin{array}{l}{T}_{+}{v}_{\mathrm{p}}-T_{-}{v}_{\mathrm{n}}=0\\ T_{+}={\displaystyle \frac{T_{\mathrm{s}}}{2}}+T_{\mathrm{d}},T_{-}={\displaystyle \frac{T_{\mathrm{s}}}{2}}-T_{\mathrm{d}}\\ v_{\mathrm{p}}+v_{\mathrm{n}}=v_{\mathrm{dc}}\end{array}\right.$$

(13)

Therefore, the expression of the unbalanced voltage can be obtained as shown in Equation (14):

$$\mathrm{\Delta }v={\displaystyle \frac{2T_{\mathrm{d}}}{T_{\mathrm{s}}}}{v}_{\mathrm{dc}}$$

(14)

4. Analysis of Soft Switch Implementation Range

The condition for the switch to achieve ZVS is that the inductor stored energy is sufficient to discharge the energy stored in the junction capacitor before the switch is turned on. Due to the symmetry of the port currents, when switches P₁ and P₄ at Port 1 achieve ZVS, switches P₂ and P₃ can also achieve ZVS, and this principle also applies to Ports 2 and 3.

The Y-type circuit after Thevenin equivalent simplification is shown in Figure 9. Take the switches X₂ and X₃ turned off and switches X₁ and X₄ turned on as an example: at this stage, i_Leq < 0. According to the KCL principle of the circuit node, Equation (15) can be obtained.

$$\left\{\begin{array}{l}{i}_{\mathrm{x}}=C_{\mathrm{ds}}{\displaystyle \frac{d{v}_{{\mathrm{C}}_{\mathrm{X}1}}}{dt}}+C_{\mathrm{ds}}{\displaystyle \frac{d{v}_{{\mathrm{C}}_{\mathrm{X}3}}}{dt}}\\ i_{{\mathrm{L}}_{\mathrm{eq}}}=C_{\mathrm{ds}}{\displaystyle \frac{d{v}_{{\mathrm{C}}_{\mathrm{X}1}}}{dt}}-C_{\mathrm{ds}}{\displaystyle \frac{d{v}_{{\mathrm{C}}_{\mathrm{X}2}}}{dt}}\end{array}\right.$$

(15)

For simplified analysis, it is uniformly assumed that the parasitic capacitor value of the drain source of the switch is C_ds. v_CX1, v_CX2, v_CX3 are the voltages of the capacitors C_X1, C_X2, C_X3. From the perspective of energy, the energy difference ∆E between the input side and the output side is shown in Equation (16). This part of the energy difference is provided by the energy E_Leq stored in the inductor.

$$\left\{\begin{array}{l}\mathrm{\Delta }E={\displaystyle {\int }_0^{t_{\mathrm{d}}}(V_{\mathrm{x}}{i}_{\mathrm{x}}-V_{\mathrm{eq}}{i}_{L_{\mathrm{eq}}})dt=2C_{\mathrm{ds}}{V}_{\mathrm{eq}}{V}_{\mathrm{x}}}\\ E_{{\mathrm{L}}_{\mathrm{eq}}}={\displaystyle \frac{1}{2}}{L}_{\mathrm{eq}}{i}_{{\mathrm{L}}_{\mathrm{eq}}}^2(t_{\mathrm{d}})-{\displaystyle \frac{1}{2}}{L}_{\mathrm{eq}}{i}_{{\mathrm{L}}_{\mathrm{eq}}}^2(0)\end{array}\right.$$

(16)

When ∆E < 0, the energy stored in the inductor decreases. Taking i_Leq(t_d) = 0 as the limit, t_d is the end time of the dead time. While maintaining directional requirements, the inductor current magnitude is also constrained by the condition E_Leq > ∆E, as specified in Equation (17):

$$i_{{\mathrm{L}}_{\mathrm{eq}}}\le -\sqrt{{\displaystyle \frac{-4C_{\mathrm{ds}}{V}_{\mathrm{eq}}{V}_{\mathrm{x}}}{L_{\mathrm{eq}}}}}$$

(17)

When ∆E > 0, the energy stored in the inductor increases, and only the requirement of current directionality needs to be met, that is, i_Leq < 0. Let L₁₂ = L₁₃ = L₂₃ = L_k, V_ESS2/V_ESS1 = M₁₂, V_dc/V_ESS1 = M₁₃. According to the conservation of node current, the current flowing through the switches at each port when the switch is turned on can be obtained as shown in Equation (18). According to the analysis of Figure 10, due to the power coupling of the converter, when the other port is heavily loaded or in the case of ∆E < 0, the range for realizing soft switching will be reduced. When the turns ratio of the transformer is close to 1, there will be a wider range for realizing soft switching.

$$\left\{\begin{array}{c}{i}_{{\mathrm{L}}_{\mathrm{pk}}}(0)={\displaystyle \frac{-2M_{12}{\phi }_{12}-2M_{13}{\phi }_{13}+\pi (-2+M_{12}+M_{13})}{2w{L}_{\mathrm{k}}}}<0\\ i_{{\mathrm{L}}_{\mathrm{sk}}}({\phi }_{12})={\displaystyle \frac{(-2+2M_{13}){\phi }_{12}-2M_{13}{\phi }_{13}+\pi (1-2M_{12}+M_{13})}{2w{L}_{\mathrm{k}}}}<0\\ i_{{\mathrm{L}}_{\mathrm{tk}}}({\phi }_{13})={\displaystyle \frac{2M_{12}{\phi }_{12}-(2+2M_{12}){\phi }_{13}+\pi (1+M_{12}-2M_{13})}{2w{L}_{\mathrm{k}}}}<0\end{array}\right.$$

(18)

5. Simulation and Experimental Verification

To verify the voltage self-balancing ability of the proposed converter in the microgrid, a 400 V DC voltage source is connected to both ends of the positive and negative buses to simulate the rectification from the high-voltage grid into the DC bus. A load with R_P = 50 Ω and R_N = 200 Ω is used to simulate the unbalanced loads at the two poles of the bipolar DC bus. The simulation model of the proposed converter has a rate power of 1 kW and an output voltage of ±200 V.

The simulation results are shown in Figure 11. It can be seen from the simulation results that before 0.05 s, when the proposed converter is not put into operation, the unbalance of the load causes the bipolar bus voltages to operate asymmetrically at 80 V and 320 V. At 0.05 s, the proposed converter is put into operation. After a short oscillation of 0.03 s, the bipolar bus voltages are 199.3 V and 200.7 V, respectively, achieving a voltage balance rate of 0.35% and basically achieving inter-pole voltage balance. These results demonstrate that the proposed converter has the voltage self-balancing capability. When the inter-pole voltage of the bipolar DC microgrid is unbalanced, it can preferentially provide more energy to the bus with lower voltage, effectively reducing the voltage asymmetry.

To validate the correctness of the above theoretical analysis, an experimental prototype with a rated output power of 1 kW is constructed. The experimental prototype is shown in Figure 12, and the detailed parameters are listed in

Table 1. Experimental prototype parameters.

Parameters	Model and Value
Input voltage VESS1, VESS2/V	48 V,48 V
Output voltage Vo/V	400 V (±200 V)
Output power P/kW	1 kW
Switching frequency fs/kHz	100 kHz
Inductor Lpk, Lsk, Ltk, L/µH	1.678 µH, 1.678 µH, 1.2 µH, 470 µH
Capacitance C1, C2, Cp, Cn/µF	20 µF, 20 µF, 100 µF, 100 µF
Power switch of port 1 S1~S4	IPP200N25N3
Power switch of port 2 P1~P4	IPP200N25N3
Power switch of port 3 T1~T4	STW88N65M5

.

The proposed topology operates at a switching frequency of 100 kHz, with an ADC sampling frequency of 857 kHz. The dead time was set to 1 μs. The controller used was an STM32F103ZET6 microcontroller running at a system frequency of 72 MHz. For the operational state where two input power sources simultaneously supply a bipolar load, the control system designed in this paper is illustrated in Figure 13. The overall control strategy is as follows: Port 1 and Port 2 are connected to batteries, whose voltages can be considered constant. The input power of Port 2 is controlled by controlling its input current, while Port 3 is connected to a load emulating a DC microgrid, whose voltage requires control. The control system does not directly adjust the power of the battery at Port 1. Under the single-phase-shift modulation strategy adopted in this work, the input/output power at Port 1 naturally equals the power difference between Port 2 and Port 3. By leveraging the principle of power conservation, the battery automatically charges or discharges to compensate for the imbalance between the power generated by the battery at Port 2 and the power demand at the DC microgrid port. Thus, while the control system explicitly regulates the power at Ports 2 and 3, the power at Port 1 is indirectly and automatically controlled.

The experimental waveforms are presented in Figure 14. The voltage waveforms of each transformer winding are depicted in Figure 14a, where V_PT, V_ST, and V_TT represent the port voltages of the transformer’s primary, secondary, and tertiary sides, respectively. Considering the losses, the phase shift ratio is set to 0.38 to achieve the required voltage. The current waveforms of each transformer winding are shown in Figure 14b. The average value of the leakage inductor current over one period is zero, indicating no DC bias. Figure 15a–c illustrates the realization of soft switching for the switches in the three full-bridge structures, respectively. The waveforms indicate that all switches achieve ZVS, thereby effectively reducing switching losses. Figure 16a,b are the input and output voltage and current waveforms under the balanced condition (R_P = 80 Ω, R_N = 80 Ω).

The effectiveness of voltage self-balancing is typically evaluated using the inter-pole voltage unbalance factor (VUF%) [26], which is defined as follows:

$$VUF\%=\left|{\displaystyle \frac{V_{\mathrm{p}}-V_{\mathrm{n}}}{V_{\mathrm{p}}+V_{\mathrm{n}}}}\right|\times 100\%$$

(19)

Under the experimental conditions of this study, Figure 17a,b presents the output voltage and current waveforms under unbalanced power conditions of 200 W (R_P = 100 Ω, R_N = 66.7 Ω) and 500 W (R_P = 160 Ω, R_N = 53.3 Ω), respectively. The measured inter-pole voltage deviations were 0.48 V and 1.459 V, corresponding to VUF% values of 0.12% and 0.36%, respectively, demonstrating the effectiveness of the voltage self-balancing capability of the proposed converter.

Figure 18a,b shows the voltage and current waveforms when the positive load R_P steps up from 80 Ω to 200 Ω and steps down from 200 Ω to 80 Ω, respectively. As observed, when R_P steps up from 80 Ω to 200 Ω, the output current i_P decreases from 2.5 A to 1 A, and the positive and negative output voltages stabilize at 200 V after a 20 ms transient with an overshoot of only 5 V. When R_P steps down from 200 Ω to 80 Ω, the output current i_P increases from 1 A to 2.5 A, and the output voltages also return to 200 V within 20 ms with the same 5 V overshoot. Similarly, Figure 18c,d presents the voltage and current waveforms during step changes in the negative load R_N between 80 Ω and 200 Ω, which exhibit behavior consistent with that of R_P. These results validate the stability of the closed-loop control system, demonstrating excellent disturbance rejection and fast dynamic response.

Figure 19 illustrates the efficiency of the experimental prototype. It is observed that as the output power gradually increases, the converter’s efficiency exhibits a trend of first increasing and then decreasing. The prototype achieves a peak efficiency of approximately 94.3% at an output power of 500 W, and the efficiency at the rated power of 1 kW is 92.7%. Figure 20 shows the thermal imaging of the prototype under the rated power of 1 kW. It can be seen from the figure that the switches have a lower temperature due to the realization of soft switching, and the highest temperature appears in the auxiliary inductor connected in series with the transformer, which is 54.9 °C. Figure 21 is the theoretical loss distribution of the proposed converter under the rated power condition. The losses are mainly switching losses, inductor losses, and transformer losses, accounting for about 94.12% of the total losses, while the losses of capacitors, drivers, and others are small, only accounting for 5.88%.

6. Performance Comparison and Analysis

Table 2. Performance comparison between the proposed converter and other converters.

Converter	The Number of Devices					Self-Balancing Capability	Electrical Isolation	Number of Ports (Input + Output)
	Switch	Diode	Transformer	Inductor	Capacitor
Reference [10]	4	0	0	3	4	No	Non-isolation	1 + 2
Reference [17]	6	0	0	3	4	Yes	Non-isolation	2 + 2
Reference [23]	12	0	1	2	3	No	Isolation	1 + 2
Reference [27]	8	0	1	2	3	Yes	Isolation	1 + 2
The proposed converter	12	0	1	1	4	Yes	Isolation	2 + 2

presents a comparison between the proposed converter and existing common bidirectional grid-energy storage voltage balancers. The approach of combinatorial transformation based on the basic topology is proposed in [10,17]. This solution can achieve voltage self-balancing but fails to provide electrical isolation, resulting in relatively low safety. The method of connecting two ports of a TAB in series to achieve bipolar output is proposed in [23], but its voltage balancing relies on a complex control system. The approach of introducing a balancing inductor based on DAB to achieve voltage self-balancing is proposed in [27]. However, compared with this, the proposed topology features more flexible power flow. Furthermore, the proposed converter does not require detection results of voltage unbalance and can automatically redistribute and process the inter-pole unbalanced power. Meanwhile, it has the advantages of flexible power regulation and high-power supply reliability.

7. Conclusions

This paper proposes an isolated bipolar bidirectional multi-port converter with inherent inter-pole voltage self-balancing capability. The power flow can be flexibly controlled through phase shift control while autonomously maintaining voltage balance between the poles. The results demonstrate that the proposed converter offers the following advantages:

(1)

The proposed converter features inherent self-balancing output voltage characteristics. Under unbalanced load conditions, it can autonomously redistribute power between the poles to maintain balanced output voltages, without relying on complex voltage sampling and control systems to sustain symmetric operation of the bipolar output.

(2)

The proposed converter supports multi-port input and bidirectional energy exchange. Phase shift control enables flexible power flow regulation and precise management of energy distribution among multiple input ports. Additionally, the high-frequency transformer provides electrical isolation, making the converter well-suited for high-power applications with enhanced operational safety and reliability.

(3)

The proposed converter achieves Zero Voltage Switching (ZVS) for its power switches, significantly reducing switching losses. This capability enhances overall efficiency and extends the operational lifespan of the components, thereby ensuring highly efficient performance even under high-frequency switching conditions.