Redundancy-Interpolated Three-Segment DAC with On-Chip Digital Calibration for Improved Static Linearity

Abstract

This paper presents a three-segment interpolating Digital-to-Analog Converter (DAC) that employs a redundancy-based interpolation scheme and digital calibration to enhance linearity. The proposed architecture consists of a Most Significant Bit (MSB) resistor string DAC, an Intermediate Significant Bit (ISB) resistor string DAC, and a Least Significant Bit (LSB) interpolating differential buffer. The MSB segment uses a split-unit resistor structure ($r_A,r_B$) to improve post-calibration differential nonlinearity (DNL) by minimizing voltage step errors. A fully digital calibration algorithm is implemented to compensate for process variations, component mismatches, and finite switch resistance, ensuring a highly linear DAC output. The proposed 16-bit DAC is implemented in a 180 nm CMOS process and is segmented into a 5-bit MSB stage, a 5-bit ISB stage, and a 6-bit LSB stage. The structure achieves post-calibration integral nonlinearity (INL) and differential nonlinearity (DNL) values of less than ±1 LSB. Simulation results validate the proposed design, demonstrating enhanced linearity and reduced area overhead compared with conventional segmented architectures.

1. Introduction

With the advent of the Internet of Things (IoT), the semiconductor industry has witnessed an unprecedented demand for low-power, small-area, and high-functioning integrated circuits [1,2]. This trend has been historically propelled by the relentless pace of Moore’s Law, which has enabled the exponential scaling of digital logic, leading to more powerful processors, larger memories, and more complex digital systems on a single chip [3]. This miniaturization has been a key enabler of the proliferation of smart devices, from wearable health monitors and remote environmental sensors to complex industrial automation systems [4,5]. These applications universally demand long battery life and compact form factors, placing stringent constraints on the power consumption and physical footprint of their electronic components [6].

While digital circuits have thrived under Moore’s Law, the same cannot be said for their analog counterparts. Analog and mixed-signal circuits, which form the critical interface between the digital processing core and the physical world, face a scaling crisis. As transistor dimensions shrink into deep sub-micron regimes, analog performance metrics often degrade. Lower supply voltages reduce the available signal headroom and dynamic range, while the decreased intrinsic gain of short-channel transistors makes designing high-performance amplifiers more difficult. Furthermore, the inherent variability and mismatch of components increase at smaller scales. This dichotomy presents a formidable challenge for designers of Systems on a Chip (SoCs), where the performance of the entire system is often bottlenecked by its analog front-end [7,8]. Among the most critical of these analog blocks is the Digital-to-Analog Converter (DAC), which is fundamental for applications requiring signal synthesis, actuation, or control.

Among the available DAC architectures, the resistor string DAC, often referred to as the R-string or string DAC, remains a popular choice, particularly for applications where low power consumption and inherent monotonicity are crucial [9]. The architecture’s elegance lies in its simplicity: a series of identical resistors form a voltage divider, and a set of switches select a specific tap point to generate the desired analog output voltage. Because selecting a physically higher tap on the string can only ever produce a higher or equal voltage, the architecture is inherently monotonic by design [9,10]. This property is highly desirable since it guarantees that the output will consistently increase or remain constant for increasing digital input codes, preventing the large-scale errors associated with non-monotonic behavior [10].

The principal drawback of the non-segmented string DAC is its prohibitive area cost at higher resolutions [10,11]. A standard n-bit implementation requires an array of $2^n$ unit resistors and $2^n$ switches, together with an n-to-$2^n$ thermometer decoder. As the resolution n increases, this exponential growth in component count leads to an impractically large silicon footprint [12]. To circumvent this scaling issue, designers almost universally employ segmentation. In a segmented design [12,13], the DAC is partitioned into two or more sub-DACs. In a typical two-stage arrangement, an $n_1$-bit coarse DAC selects a voltage range and an $n_2$-bit fine DAC interpolates within that range. This approach reduces the component count to approximately $2^{n_1}+2^{n_2}$, making high-resolution designs practical [11,14]. The concept can be extended to a three-segment architecture comprising Most Significant Bit (MSB), Intermediate Significant Bit (ISB), and Least Significant Bit (LSB) stages.

Although segmentation removes the raw area problem [15,16,17], it introduces new challenges that compromise the very benefits for which the string DAC is valued. The clean monotonicity of the original design is lost, and the converter’s linearity becomes highly susceptible to two dominant error mechanisms [16,18]: inter-stage loading and component mismatch. Inter-stage loading occurs when the fine-DAC stage draws current from the coarse stage, altering the voltage at the selected tap and introducing a systematic nonlinearity [15]. Moreover, the transitions between segments, for example, the MSB-to-ISB boundary, become critical points where resistor mismatches can cause large linearity errors [19]. A conventional mitigation strategy is to insert power-hungry buffer amplifiers between the stages [18,19]. These buffers provide impedance isolation but at the cost of increased power, design complexity, and silicon area. This counteracts the motivations for choosing the string DAC in the first place.

The static performance of a string DAC is governed by the matching accuracy of its unit resistors, which directly determines its differential and integral nonlinearities [16,20]. DNL quantifies the deviation in step size between adjacent digital codes from the ideal 1 LSB, whereas INL measures the maximum deviation in the entire transfer curve from a fitline [10]. Process-induced mismatch produces both DNL and INL errors [16,17,21,22]. These variations can be systematic, such as wafer-level gradients, or random, such as microscopic fluctuations in resistor width and thickness [16]. Systematic errors can often be alleviated with careful layout, for example, common-centroid placement [23], yet random mismatch remains a fundamental physical limitation whose standard deviation is inversely proportional to the square root of the component area.

Failure to meet the matching requirement leads to discontinuities in the DAC transfer curve [14]. Not all discontinuities are equally harmful: negative DNL steps can often be tolerated or calibrated, whereas positive DNL steps are far more pernicious [24]. A large positive jump creates a missing code, a range of output values the DAC can never produce, representing a permanent loss of information that is effectively uncalibrated [17]. This insight motivates redundancy-based or sub-radix design, which shifts the goal from perfect analog matching to permitting digitally correctable imperfections [25].

The sub-radix approach intentionally sets major-bit step sizes slightly below the ideal, so the effective radix is less than 2. This produces small, predictable negative DNL errors, ensuring that there are no positive jumps and therefore no missing codes. Redundancy sharply reduces the chance of large, uncalibrated errors from random mismatch. As a result, resistor-matching constraints can be relaxed, smaller components can be used, and the overall area shrinks. Accuracy is then recovered in the digital domain: an all-digital calibration stage maps the nonlinear but monotonic DAC output to a fully linear transfer curve. A small lookup table or digital state machine stores this mapping, and modern SoCs have sufficient logic and memory to implement it without difficulty.

This paper presents a novel 16-bit, three-segment interpolating DAC that fully capitalizes on this redundancy-based calibration strategy to achieve high linearity and area efficiency. The architecture, implemented in a 180 nm CMOS process, is segmented into a 5-bit MSB stage, a 5-bit ISB stage, and a 6-bit LSB stage. The key innovations of this work are as follows:

• MSB Stage: The MSB segment introduces a split-unit resistor structure ($r_A,r_B$). This technique enhances the DAC’s sub-radix property to reduce post-calibration differential nonlinearity (DNL).
• ISB Stage: The ISB employs redundancy-based interpolation, achieved by adding an extra resistor to the string, which reduces voltage step errors and improves static linearity. The extra resistor directly counteracts the inter-stage loading effect. This loading effect is a source of nonlinearity, occurring when the ISB string draws current from the Most Significant Bit (MSB) stage and alters its tap voltages. By incorporating this extra resistor, we increase the total number of unit resistors ($D_I$) in the ISB string, which in turn raises its equivalent total resistance ($E_M$). This increased resistance effectively compensates for the loading, a critical factor in achieving the precise sub-radix behavior required for calibration.
• LSB Interpolating Buffer: The LSB segment departs from the traditional design by replacing the resistor ladder with a custom-designed differential interpolating buffer. This buffer is built with a two-stage folded cascode amplifier and a Class AB output stage and interpolates between ISB outputs to eliminate the need for a fine resistor string DAC.
• Integrated Buffer Functionality: This integrated LSB interpolator serves a dual purpose: it performs high-resolution voltage interpolation while simultaneously acting as the load driving output buffer. This approach eliminates the need for a separate area-intensive buffer, reduces static loading on the ISB string, and lowers overall power consumption.

A fully digital calibration algorithm compensates for process variations, mismatches, and finite switch resistance to ensure a highly linear DAC output. Simulation results validate the proposed architecture, demonstrating that both post-calibration integral nonlinearity (INL) and differential nonlinearity (DNL) are less than $\pm 1$ LSB.

2. Proposed DAC Architectures

2.1. Existing Design

The utilization of multi-stage string DACs devoid of buffer amplifiers is a known technique for creating area- and power-efficient converters [26]. In this general approach, the first-string DAC processes the Most Significant Bits (MSBs) to generate a pair of voltages that serve as the high and low references for the subsequent stage. This interpolation scheme continues through the stages; however, the absence of a buffer means that the individual-string DACs exhibit a loading effect on each other, which can degrade the overall linearity of the converter. A notable architecture that builds on this principle consists of three stages: an $n_M$-bit MSB, an $n_I$-bit ISB, and an $n_L$-bit LSB resistor string ladder [25]. This design comprises $D_M=2^{n_M}+1$, $D_I=2^{n_I}$, and $D_L=2^{n_L}-1$ unit resistors, respectively. The key feature of this architecture is the introduction of negative jumps in the DAC’s transfer curve, which creates a sub-radix characteristic in the output. This inherent redundancy facilitates digital calibration, allowing for the correction of nonlinearities even when resistor matching is limited. This enables a significant area reduction compared with conventional $2^n$ resistor implementation, by segmenting the DAC without resorting to buffer amplifiers.

Despite these advancements, critical limitations remain. A buffer is still required to drive any external load, which is a crucial function for a DAC. Furthermore, in designs with a higher number of LSBs, a conventional LSB resistor DAC interpolation stage requires a larger area. This increased footprint leads to higher static loading on the ISB string DAC, resulting in greater static power consumption. In the next sub-section, we present our architecture, which overcomes these challenges and enhances the performance of multi-stage string DACs.

2.2. Review of Proposed DAC Structure 1

The proposed architecture consists of three stages, an $n_M$-bit MSB, an $n_I$-bit ISB resistor string ladder, and an $n_L$-bit LSB differential pair interpolator, forming an n-bit resolution DAC. The digital input codes, $S_w^M\in [0,2^{n_M}-1]$, $S_w^I\in [0,2^{n_I}-1]$, and $S_w^L\in [0,2^{n_L}-1]$, are used to control switches in the MSB ladder, ISB ladder, and the LSB differential interpolator, respectively. A specific decoding scheme, similar to that presented in [25], is employed. Lower-order bits are handled by the ISB resistor ladder and the LSB differential interpolator. Under ideal conditions, without resistor mismatch or switch non-idealities, the combination of the ISB and LSB stages has been shown to yield a linear ($n_I+n_L$)-bit output by providing $D_I+1$ unique node voltages from the ISB string. The respective stages are discussed below.

2.2.1. MSB String DAC

An $n_M$-bit MSB subword of the digital input word is decoded to close two unique switches along the resistive string. A switch at node $S_w^M$ connects to the first conductor to produce a voltage $V_1^I$, and a second switch at node $S_w^M+2$ connects to a second conductor to produce a voltage $V_2^I$. The pair of voltages ($V_1^I,V_2^I$) serves as the high and low references for the subsequent ISB stage. The resistor string and the corresponding set of switches constitute the MSB string DAC, and the voltage pair is a coarse analog representation of the MSB subword. This coarse analog representation is intentionally non-monotonic. A key feature of this MSB switching method is the creation of negative jumps in the full DAC transfer curve, giving the converter a sub-radix characteristic. The result is a transfer function composed of $2^{n_M}$ straight-line segments separated by these negative jumps, which occur whenever $S_w^M$ changes. A total of $2^{n_M}+1$ resistors are used in the MSB resistive string DAC if the MSB subword has $n_M$ bits. The schematic of the proposed MSB string DAC in context is presented in Figure 1 for an implementation where $n_M=3$ bits.

2.2.2. ISB String DAC

The proposed architecture also includes an Intermediate Significant Bit (ISB) string DAC. This stage performs an intermediate interpolation between the two reference voltages, $V_1^I$ and $V_2^I$, provided by the MSB stage. This interpolation occurs in response to the $n_I$-bit ISB subword. The schematic of the proposed ISB string DAC in context is presented in Figure 1 for an implementation where $n_I=3$ bits.

2.2.3. LSB Segment

The concept of an LSB differential pair interpolator was initially introduced in [13]. However, that work did not extend the idea to an interpolator that functions as a load-driving buffer. In our design, we implement a two-stage folded cascode amplifier with a Class AB biasing stage that serves as an interpolator and buffer for DAC output. The proposed architecture includes an $n_L$-bit LSB segment which produces a fine interpolation between the reference voltages $V_1^L$ and $V_2^L$ provided by the ISB stage, wherein the interpolation occurs in response to an $n_L$-bit LSB subword. The LSB segment is a two-stage cascode amplifier with a Class AB output stage, in which accuracy is assured by the precise summing of differential currents. This is accomplished by one of the amplifier’s PMOS input pairs being implemented as a binary-weighted transistor structure. The gates of the transistors within this structure are selectively connected to either $V_1^L$ or $V_2^L$ by switches, respectively, in response to the decoding of the $n_L$-bit LSB subword. For an $n_L$-bit LSB subword, the decoder is arranged so that each increment in the value of the subword switches the gate connection of a corresponding portion of the binary-weighted transistor structure, altering the effective transconductance of the differential pair. The output of the differential input pair drives the folded cascode stage, which provides high gain. The output of this first stage is then connected to a second stage, which includes the Class AB output buffer. The gate biases for the Class AB stage are provided by a Monticelli biasing circuit, which ensures stable rail-to-rail output performance. The amplifier’s input pair, implemented as a binary-weighted transistor structure, generates a differential signal current. This current is then processed by the folded cascode stage, and subsequently buffered by the Class AB stage to produce the final output voltage. This integrated design serves the dual purpose of being both an interpolator and the final output buffer. This integrated architecture eliminates the need for a separate buffer, reduces static loading on the ISB string, provides the necessary input common-mode range, and ensures rail-to-rail output performance to meet load requirements. The power consumption of the operational amplifier is 630 µW. Figure 2 provides a detailed circuit diagram of the proposed LSB interpolator for an implementation where $n_L=2$ bits.

Figure 3 shows the schematic of the proposed DAC design with an LSB differential pair interpolator connected in a unity feedback configuration.

The decoding scheme for the proposed DAC structure 1 is summarized in

Table 1. Summary of decoding scheme employed in proposed DAC structure 1.

Voltage (V)	Node Number	Segmented DACs
$V_2^I$	$S_w^M+2$	MSB
$V_1^I$	$S_w^M$	MSB
$V_2^L$	$S_w^I+1$	ISB
$V_1^L$	$S_w^I$	ISB
$V_{\mathrm{out}}$	$S_w^I$ is even: $S_w^L$	LSB
	$S_w^I$ is odd: $2^{n_L}-1-S_w^L$	LSB

.

Under the assumption that the resistors and switches are ideal, the expressions for $V_1^I$ and $V_2^I$ are given below:

$$V_1^I={\displaystyle \frac{S_w^M}{D_M-2+E_M}}\times V_{\mathrm{REF}}$$

(1)

$$V_2^I={\displaystyle \frac{S_w^M+E_M}{D_M-2+E_M}}\times V_{\mathrm{REF}}$$

(2)

where

$$E_M={\displaystyle \frac{\left(2\right)D_I}{2+D_I}}$$

(3)

The ISB segment interpolates between the two voltages, $V_1^I$ and $V_2^I$, provided by the MSB segment. Following this, the LSB segment performs a final interpolation between the two voltages, $V_1^L$ and $V_2^L$, generated by the ISB. The expressions for $V_1^L$ and $V_2^L$ are shown below:

$$V_1^L={\displaystyle \frac{S_w^I}{D_I}}(V_2^I-V_1^I)+V_1^I$$

(4)

$$V_2^L={\displaystyle \frac{S_w^I+1}{D_I}}(V_2^I-V_1^I)+V_1^I$$

(5)

From the LSB interpolator, the DAC’s output is given below:

$$V_{\mathrm{out}}={\displaystyle \frac{S_w^L}{2^{n_L}}}(V_2^L-V_1^L)+V_1^L$$

(6)

By substituting all the necessary parameters, we end up with the expression for $V_{\mathrm{out}}$ given below:

$$V_{\mathrm{out}}={\displaystyle \frac{S_w^M·2^{n_L}·D_I+(S_w^L+2^{n_L}·S_w^I)E_M}{2^{n_L}·D_I(D_M-2+E_M)}}\times V_{\mathrm{REF}}$$

(7)

Suppose that the target resolution post-calibration is $n_{DAC}$; then the expected step size is $V_{LSB}^D={\displaystyle \frac{V_{\mathrm{REF}}}{2^{n_{DAC}}}}$, and to attain good post-calibration linearity, $n_{DAC}<n$, where $n=n_M+n_I+n_L$. Consequently, for any change of 1 in the DAC code, $S_w$, while the MSB code remains fixed, the change in output normalized to LSB is given below:

$${\displaystyle \frac{\Delta V_{\mathrm{out}}}{V_{LSB}^D}}={\displaystyle \frac{E_M\left(2^{n_{DAC}}\right)}{2^{n_L}·D_I(D_M-2+E_M)}}$$

(8)

This equation captures the desired sub-radix and redundancy properties in the proposed architecture.

2.3. Improved Redundancy-Interpolated Three-Segment DAC

Simulation results for the proposed DAC structure 1 indicate that the proposed architecture exhibits a fundamental limitation in its post-calibration DNL at the target resolution of $n_{DAC}=n-1$. While simply lowering the target resolution ($n_{DAC}$) improves the DNL metric, this approach presents an unfavorable trade-off between resolution and linearity. Analysis of the DAC’s transfer characteristic reveals that for a fixed MSB code, a single LSB step results in an output voltage change of approximately 0.92 LSB. To achieve superior DNL performance, this intra-segment step size must be reduced, thereby increasing the available redundancy for the calibration algorithm.

One effective method to reduce the step size is to decrease the effective resistance, $E_M$, in the MSB string DAC where the ISB string connects. To accomplish this while preserving the essential sub-radix nature required for calibration, this effective resistance value must be constrained to be less than $2r$ but greater than r. This is achieved in a modified architecture, referred to as DAC structure 2, by splitting each unit resistor r in the MSB string DAC into two parts, $r_A$ and $r_B$. The relationship between these resistors is defined as

$$r_A=\gamma r,r_B=(1-\gamma )r$$

(9)

where $\gamma <1$. The ISB and LSB string DACs remain unchanged. In this structure, for each MSB code, $S_w^M$, the high $V_2^I$ and low $V_1^I$ references of the ISB string DAC are connected to nodes, $S_w^M\left(A\right)$ and $S_w^M+1\left(B\right)$, respectively, in the modified MSB string. A schematic of the improved structure is shown in Figure 4.

The corresponding decoding scheme for the proposed DAC structure 2 is summarized in

Table 2. Summary of decoding scheme employed in proposed DAC structure 2.

Voltage (V)	Node Number	Segmented DACs
$V_2^I$	$S_w^M+1\left(B\right)$	MSB
$V_1^I$	$S_w^M\left(A\right)$	MSB
$V_2^L$	$S_w^I+1$	ISB
$V_1^L$	$S_w^I$	ISB
$V_{\mathrm{out}}$	$S_w^I$ is even: $S_w^L$	LSB
	$S_w^I$ is odd: $2^{n_L}-1-S_w^L$	LSB

.

Under the assumption that the resistors and switches are ideal, the output from the DAC can be expressed as

$$\begin{array}{c}{g}_{m1}{S}_w^L{V}_2^I+g_{m1}(2^{n_L}-S_w^L)V_1^I=g_{m1}{2}^{n_L}{V}_{\mathrm{out}}\end{array}$$

(10)

$$\begin{array}{c}{g}_{m1}{S}_w^L(V_2^I-V_1^I)+g_{m1}{2}^{n_L}{V}_1^I=g_{m1}{2}^{n_L}{V}_{\mathrm{out}}\end{array}$$

(11)

$$\begin{array}{c}{V}_{OUT}\left(S_W\right)={\displaystyle \frac{S_w^L}{2^{n_L}}}(V_2^L-V_1^L)+V_1^L\end{array}$$

(12)

where $g_{m1}$ is the transconductance of the LSB differential interpolator. Since the LSB is not a string DAC, there is no loading effect across the ISB. The ISB voltages can be expressed as

$$\begin{array}{c}{V}_1^L={\displaystyle \frac{S_w^I}{D_I}}(V_H^I-V_L^I)+V_L^I\end{array}$$

(13)

$$\begin{array}{c}{V}_2^L={\displaystyle \frac{S_w^I+1}{D_I}}(V_H^I-V_L^I)+V_L^I\end{array}$$

(14)

where $D_I$ is the total number of resistors in the ISB string DAC. Due to the loading effect of the ISB on the MSB string, the resistors in the MSB string across the ISB connection have their values altered. Taking that into consideration, the expressions for $V_H^I$ and $V_L^I$ are derived as

$$\begin{array}{c}{V}_H^I={\displaystyle \frac{S_w^M(1+\gamma )+E_m}{(2^{n_M}-1)(1+\gamma )+E_m}}{V}_{\mathrm{REF}},\end{array}$$

(15)

$$\begin{array}{c}{V}_L^I={\displaystyle \frac{S_w^M(1+\gamma )}{(2^{n_M}-1)(1+\gamma )+E_m}}{V}_{\mathrm{REF}}\end{array}$$

(16)

where

$$E_m={\displaystyle \frac{(2\gamma +1)D_I}{2\gamma +D_I+1}}$$

(17)

Thus, the overall output voltage of the improved DAC architecture is given by

$$V_{\mathrm{OUT}}={\displaystyle \frac{S_w^L{E}_m+2^{n_L}[S_w^I{E}_m+S_w^M(1+\gamma )]}{2^{n_L}{D}_I[(2^{n_M}-1)(1+\gamma )+E_m]}}{V}_{\mathrm{REF}}$$

(18)

3. Optimum Calibration (Binary Search Calibration)

The proposed optimum-chip calibration algorithm is as follows: For any desired post-calibration resolution $n_{\mathrm{DAC}}$, the INL of the n-bit DAC is first obtained pre-calibration. From the computed INL, the output of the DAC, $V_{\mathrm{out}}$, can be represented in the digital domain as $V_{\mathrm{out}}^{\mathrm{LSB}}$:

$$V_{\mathrm{out}}^{\mathrm{LSB}}\left(S_w\right)=S_w{\displaystyle \frac{2^{n_{\mathrm{DAC}}}-1}{2^n-1}}+\mathrm{INL}\left(S_w\right)$$

(19)

A linear $n_{\mathrm{DAC}}$-bit DAC must generate $2^{n_{\mathrm{DAC}}}-1$ unique voltages on a straight line. For this target resolution, the input code to the DAC is represented by C. For every C, the calibration scheme finds an $S_w$ that minimizes the error between C and $V_{\mathrm{out}}^{\mathrm{LSB}}\left(S_w\right)$. The code C is then mapped to this optimal $S_w$. This is performed for all $C\in [0,2^{n_{\mathrm{DAC}}}-1]$, thereby minimizing the post-calibration INL. The maximum of $V_{\mathrm{out}}^{\mathrm{LSB}}$ is capped at $2^{n_{\mathrm{DAC}}}-1$. For a code C, the optimal $S_w$ which generates the desired output is obtained as shown in (20).

$$S_w^{\mathrm{opt}}=\underset{S_w\in [0,2^n-1]}{argmin}\parallel V_{\mathrm{out}}^{\mathrm{LSB}}\left(S_w\right)-C\parallel$$

(20)

The optimization problem in (20) is solved via a binary search algorithm to obtain a mapping from C to $S_w^{\mathrm{opt}}$. This requires an initial sorting of the $V_{\mathrm{out}}^{\mathrm{LSB}}$ vector, which is a one-time cost [27,28]. The subsequent search for each C has a complexity of $O\left(n\right)$. The algorithm identifies which pre-calibration code ensures the desired linear response at the $n_{DAC}$-bit level. This mapping is repeated across the full code space, and the resulting calibrated codes are stored for subsequent usage. This one-time calibration eliminates the need for repeated re-calibration, which offers an efficient and robust solution for integrated systems.

4. Implementation

The proposed DAC architectures are implemented in the TSMC $180\mathrm{nm}$ process with a 5-bit MSB, 5-bit ISB, and 6-bit LSB, giving a pre-calibration resolution of $n=16$. For both designs, each unit resistor is a $1\mathrm{k}\mathsf{\Omega }$ poly-resistor, ensuring a high level of matching while reducing area overhead. For DAC structure 2, a $\gamma$ of 0.50 is chosen, setting both $r_A$ and $r_B$ to $500\mathsf{\Omega }$. This design sets the maximum post-calibration resolution, $n_{\mathrm{DAC}}$, to 15. Transmission gate switches are utilized in all string DACs. The decoders for the MSB and ISB stages are simple n-to-$2^n$ decoders. An external, ideal voltage source of $1.8\mathrm{V}$ is used to generate $V_{\mathrm{REF}}$.

5. Results

Simulations for both circuit designs were conducted in Cadence Spectre. To calibrate the design to a final resolution of $n_{DAC}=15$, the binary search algorithm described above was implemented using MATLAB. The overall output characteristics for DAC structure 1 is illustrated in Figure 5, showing the transfer curve for the target resolution prior to and after calibration. The calibrated design achieved an INL of 0.48 LSB (14.54 ppm) and a DNL of 0.92 LSB (27.96 ppm). Figure 6 and Figure 7 provide a detailed comparison of the INL and DNL plots, both before and after calibration. Furthermore, the stability of the LSB differential pair interpolator is confirmed by a measured gain of 108 dB and a phase margin of 66°.

DAC structure 2 achieves a significant improvement in linearity over both DAC structure 1 and the architecture in [25] at the nominal and PVT (Process, Voltage, Temperature) corners. Simulation results at the nominal corner show a post-calibration INL of 0.31 LSB (9.51 ppm) and DNL of 0.54 LSB (16.43 ppm). A detailed comparison of the pre- and post-calibration INL and DNL plots is provided in Figure 8 and Figure 9, while the overall transfer curve for the target resolution is shown in Figure 10. The stability of the design is supported by the robust performance of its LSB differential pair interpolator, which exhibits a measured gain of 108 dB and a phase margin of 66°, as depicted in Figure 11.

To verify the robustness of DAC structure 2 against non-idealities, a Monte Carlo simulation was performed. A total of 100 Monte Carlo runs were conducted to assess the impact of both process and mismatch variations. The number of Monte Carlo runs was chosen to provide a fair comparison with the architecture proposed in [25]. In each simulation run, component values were varied randomly; this included not only the unit resistors but also transistor parameters such as width and length, which models variations in switch resistance and differential interpolator. The post-calibration linearity results for the target resolution are summarized in Figure 12. The analysis of the 100 iterations shows a worst-case INL of 0.48 LSB and a worst-case DNL of 0.68 LSB, confirming the architecture’s resilience to process and mismatch effects.

The probability density function (PDF) plots for INL and DNL are presented in Figure 13. The simulation yields a mean ($\mu$) of 0.36 LSB and a standard deviation ($\sigma$) of 0.04 LSB for the maximum INL across 100 Monte Carlo runs. Similarly, the maximum DNL shows a mean of 0.48 LSB and a standard deviation of 0.11 LSB.

The dynamic performance of DAC structure 2 was evaluated through the spectral analysis of its output, both before and after calibration, as illustrated in the magnitude spectrum plots (Figure 14). The post-calibration spectrum demonstrates a substantial enhancement in signal integrity, characterized by a marked suppression of spurious tones and a significant reduction in harmonic distortion. This improvement is quantified by key performance metrics, with the Signal-to-Noise Ratio (SNR) increasing from $39.76$ dB to $91.51$ dB, the Spurious-Free Dynamic Range (SFDR) improving from $48.94$ dB to $104.90$ dB, the Signal-to-Noise and Distortion Ratio (SNDR) increasing from $39.11$ dB to $91.48$ dB, and the Total Harmonic Distortion (THD) reducing from $-47.71$ dB to $-112.28$ dB. Consequently, the Effective Number of Bits (ENOB) increased from 6.20 bits to 14.90 bits. These results underscore the efficacy of the proposed digital calibration algorithm in mitigating nonlinearities. The significant improvements across all measured dynamic performance metrics confirm that the calibration process not only enhances static linearity but also translates directly into a cleaner, more accurate analog output signal under dynamic conditions. The substantial increase in ENOB, in particular, validates the design’s ability to achieve high resolution.

6. Discussion

A data converter’s robustness against device mismatches and random manufacturing variations is primarily quantified by its static linearity metrics, namely, INL and DNL. For high-precision applications, achieving an INL below 0.5 LSB and a DNL of less than 1 LSB is a critical design target. The Monte Carlo simulation results confirm that our design comfortably meets these targets.

This represents a significant improvement over the prior state of the art. For instance, the architecture in [25] reported a worst-case post-calibration INL of 0.78 LSB and a DNL of 0.94 LSB for a 13-bit target resolution. An INL greater than 0.5 LSB can compromise a device’s effective resolution. Under the same post-calibration resolution, the proposed design achieves a worst-case INL of 0.24 LSB and a DNL of 0.38 LSB. This substantial enhancement is attributed to key architectural innovations.

A primary limitation in conventional segmented string DACs is the static loading that the LSB stage imposes on the preceding ISB string, which degrades DNL performance. The proposed architecture fundamentally overcomes this issue by implementing the LSB segment as an interpolating differential buffer. This approach eliminates any static loading from the LSB stage onto the ISB string DAC, directly contributing to the improved linearity. It is observed that the proposed design is comparable in terms of accuracy with other string DAC architectures present in the literature.

The proposed DAC structure 2 is compared to other interpolating string DAC designs from the literature, with a summary of the comparison provided in

Table 3. Comparison of the proposed design with the existing literature.

Parameter	ElConRus [12]	ITC [29]	TCAS-1 [23]	MWSCAS [25]	This Work
Technology (µm)	0.18	0.5	0.13	0.18	0.18
Resistor Material	∼	Poly	TaN	Poly	Poly
Architecture	Segmented string DAC	String DAC + calibration DAC	String DAC + interpolating amplifier	Segmented string DAC	String DAC + differential interpolator
Resolution (bits)	10	16	8	13	15
Output range (V)	1.8	5	3.3	1.2	1.2
INL (ppm/LSB)	9k/9.4	122/7.99	21/5.37m	95/0.78	16/0.48
DNL (ppm/LSB)	273/0.28	6.1/0.49	18/4.61m	124/0.94	21/0.68
Measurement	No	Yes	Yes	No	No

.

7. Conclusions

This paper introduces a 16-bit, three-segment string DAC that uses a redundancy-based architecture and on-chip digital calibration to enhance static linearity while minimizing area. The design’s key features include a split-resistor MSB stage, a redundancy-based ISB interpolator, and an LSB segment implemented with a folded-cascode amplifier that also serves as the output buffer. The design’s performance is validated through simulation, achieving post-calibration INL and DNL of less than ±1 LSB across process and mismatch variations. Subsequent work will focus on fabricating the design for empirical verification and characterization.