Injection-Locked Frequency Multipliers with Single Inductor Component

Abstract

This paper proposes a compact inductor design for LC-tank injection-locked frequency multipliers (ILFMs) fabricated using a 0.18 μm CMOS process. The ILFMs use an 8-shaped inductor with two lobes, suppressing the magnetic field generation. Its contents cover one ×2, one ×3, and one ×6 ILFM. The first ×2 ILFM circuit uses the orthogonal transformer consisting of an 8-shaped inductor and a non-twisted inductor. The total area is 1.137 × 0.797 mm². The input locking range is from the incident frequency of 1.6 to 3.0 GHz to provide a signal source from 3.2 GHz to 6 GHz. The second ×3 ILFM uses the orthogonal transformer and occupies an area of 1.29 × 0.76 mm². The output locking range is from 9 GHz to 19.8 GHz. This third ×6 ILFM uses a trifilar consisting of two 8-shaped inductors in perpendicular layout and a non-twisted inductor. The ×6 ILFMs show interference noise suppression via a core two-turn 8-shaped inductor and save die area. The die area is 0.843 × 0.981 mm². At V_DD = 1.3 V and an input power of 0 dBm, the output locking range is from 5.16 GHz to 5.388 GHz. In all the investigated ILFMs, no varactors are added to the LC resonator for a wide-band locking range design. The phase noises of the input signal and the output signal of the ILFM are in agreement with the theoretical value.

1. Introduction

Injection-locked frequency multipliers (ILFMs) are popular circuits used with phase-locked loops (PLLs) [1] to extend the operation frequency. Fundamentally, they cover ×2 ILFMs [2,3,4], ×3 ILFMs [5,6,7] and other high-modulus ILFMs. A 5.7 GHz single-stage LC-tank injection-locked frequency sixtupler (ILFS) [8] has been presented and it uses several octagonal inductors. Two recent millimeter (mm)-wave ILFSs [9] with the schematic as shown in Figure 1a uses five O-shaped inductors or 8-shaped inductors, where the latter is used for magnetic coupling noise suppression. A mm-wave ×6 ILFM as shown in Figure 1b uses a frequency doubler in series with a frequency tripler. The use of multi-inductors increases the die area of the ILFM core and the harmonic coupling between the ILFM-core inductors; it also increases the distance between circuits because of magnetic field coupling.

This paper designs three LC-tank ILFMs fabricated using the CMOS process and the circuit uses only one compact inductive device for die area saving. In the first designed ×2 ILFM, two inductors are configured as a low-coupling orthogonal transformer consisting of an 8-shaped inductor and a non-twisted inductor. The orthogonal transformer [10] uses one 8-shaped inductor and one non-twisted inductor sharing the same hollow area and with a low-coupling coefficient. Because of the low-K coefficient, the two inductors are regarded as two isolated inductors, so the occupied area of the transformer is small. In addition, the 8-shaped inductor [11] reduces the magnetic field radiation by the opposed magnetic field directions due to the two inductor lobes. The second designed ×3 ILFM also uses a low-coupling orthogonal transformer. The previous ×3 ILFM shows a small locking range [12] because it uses varactors to extend the tuning range, but the varactors reduce the locking range, and it uses one buffer filter to reduce harmonics. The present ×3 ILFM without varactors enhances the locking range and uses two buffer filters to reduce the harmonics. The two-coil inductor design can be extended to a three-coil inductor design for ILFMs to save die area. The third designed ×6 ILFM uses a three-coil low-coupling orthogonal trifilar. Experiment verifies the possibility of an orthogonal trifilar.

2. Multiply-by-2 ILFM

A conventional ×2 ILF can be designed with three spiral inductors. The section designs a compact ×2 ILFM with one inductive component.

2.1. ×2 Circuit Design with Single Inductive Component

The schematic of the first ×2 ILFM circuit is shown in Figure 2a. Figure 2b shows the circuit block diagram with a differential input/output injection-locked oscillator (ILO) stacked below a single-ended output ×2 FD. The cross-coupled nMOS transistors M₁ and M₂ and two-turn center-tapped 8-shaped inductors made of L₂, L₃, and parasitic capacitors form a VCO used as a first-harmonic ILO with two injection nFETs M₃ and M₄. The common-source V_v of M₅ and M₆ is a virtual ground for the fundamental signal. A differential injection signal at the frequency f_inj is applied to the gates M₃ and M₄. NFETs M₅ and M₆, and inductor L₁ form a balanced frequency doubler. The frequency doubler is based on the MOSFET used as a nonlinear amplifier, which generates the 2nd harmonic essential to the balanced frequency doubler. Transistor M₇ is the output buffer for the extraction of the 2 f_inj signal, and the locking range of the 1st harmonic ILO determines the locking range of the ILFD. Components C₁~C₃ are DC-blocking capacitors. Components R₁~R₃ are for DC biasing. V_bias is the gate bias voltage. The nMOS VCO is used as a 1st harmonic ILO with the output oscillation frequency locked to the signal at f_inj, in case the frequency f_inj falls in the locking range of the 1st harmonic ILO. No buffer is used for the ILO; this reduces the parasitic capacitance and increases the locking range.

Figure 3 shows the layout of the orthogonal transformer consisting of one two-turn 8-shaped inductor laid inside a one-turn non-twisted inductor. The centre-tapped two-turn 8-shaped inductor consists of a one-turn 8-shaped inductor in series with a one-turn 8-shaped inductor. The two lobes of the 8-shaped inductor generate the magnetic fields in the opposite direction, and the magnetic coupling between the one-turn inductor and the two-turn 8-shaped inductor is small. Figure 4a shows the simulated inductances of inductors L₁ and L₂. At 2.3 (4.6) GHz, the inductance of L₁ is 1.13 (1.37) nH, and the inductance of L₂ is 4.373 (5.23) nH. Figure 4b shows the simulated quality factors of inductors L₁ and L₂. The Q-factor is 5.0 (6.5). The differential mode (DM) K-factor is 0.025 (0.057).

2.2. Experiment of the ×2 ILFM

The die micrograph is shown in Figure 5. The total area, including the output buffer and the pads, is 1.137 × 0.797 mm². At V_DD = 1.5 V, the current/power consumption is 2.644 mA/3.966 mW. The setup employs a signal generator Keysight N5183A, CA, USA to provide a single-ended input signal, which is then converted to a differential signal using an external balun. The spectrum analyzer is an Agilent 4407B analyzer, CA, USA. Figure 6a shows the measured output full-span spectrum of the ×2 ILFM. The free-run output signal is at 4.27 GHz with an output power of −6.57 dBm. Figure 6b shows the measured output full-span spectrum of the ×2 ILFM under the locked condition. The output signal is at 4.2 GHz with an output power of −7.73 dBm. Figure 7 shows the measured output sensitivity of the ×2 ILFM at V_DD = 1.3, 1.4, 1.5 V. At V_DD = 1.3 V, the locking range is from 3.8 GHz to 7 GHz. Figure 8 shows the measured phase noises of the injection reference and the ×2 ILFM output signal. At 1/0.1/0.01 MHz offset frequency, the phase noises are −138.3/−114.94/−114.48 dBc/Hz and −133.59/−108.15/−108.09 dBc/Hz, respectively, for the input and locked output.

3. Multiply-by-3 ILFM

This section covers an ×3 ILFM with a 3-dimensional stacked orthogonal transformer, which is different from the previous ×3 ILFM [12] with a coplanar orthogonal transformer and one-band buffer filter. The ILFM can occupy a small area because the O-shaped inductor is stacked below the 8-shaped inductor. The present ×3 ILFM uses a new orthogonal transformer and buffers with dual-band filters for wide-band harmonic filtering. The present ILFM circuit uses no varactors for a wider locking range in accordance with the theory.

3.1. Circuit Design

Figure 9a shows the detailed schematic of the designed ×3 ILFM. Figure 9b shows the layout of the orthogonal transformer. The lack of varactors in shunt with inductor L₁ increases the locking range. One-turn eight-shaped inductor L₁ is shown in Figure 9a, and parasitic varactors form the main resonator. Figure 9b also shows the layout of the orthogonal transformer. Cross-coupled nMOS (M₁, M₂) are negative resistor emulators. V_DD is the supply voltage. NMOS (M₃, M₄) are injection FETs that form the frequency tripler with L₂. Configuring a one-turn 8-shaped inductor L₁ and a two-turn non-twisted L₂ as one orthogonal transformer saves die area. FETs (M₅, M₆) are common-source buffers. The series-tuned filter (L₃, C₃) and the parallel-tuned filter (L₅, C₇) suppress the undesired harmonics at the buffer’s output. The input frequency is ω_rf+ and ω_rf-, the frequency at node A is 2ω_rf, and the frequency at node B is 3ω_rf+. Figure 9a differs from the circuit shown in [12], as it utilizes no tank tuning varactors, allowing the locking range to be measured.

For the ÷1 ILO with a parallel RLC resonator [13], the locking range can be written as follows:

$$({\omega }_{RF}-{\omega }_o)={\displaystyle \frac{{\omega }_o{I}_{inj}}{2Q I_{osc}}},$$

(1)

where ω_o is the ILO free running oscillation frequency, ω_RF is the frequency of the RF injection signal, and Q is the quality factor of the tank at resonance. I_inj/I_osc is the injection/switching drain current to the tank. The input frequency locking range [14] derived from (1) is given by

$$({\omega }_{RF}-{\omega }_o)={\displaystyle \frac{g_m}{\mathrm{C}}},$$

(2)

where g_m is the equivalent transconductance of the switching FET, and C is the capacitive load connected to its source and drain. The capacitance reduction leads to the locking range enhancement.

Figure 9c shows the simulated Q-factor and inductance of the transformer in Figure 9b. At 16.5 GHz, simulated inductances are L₁ = 1.219 nH and L₂ = 2.269 nH. Simulated Q-factors are Q₁ = 20.247 and Q₂ = 6.283 nH, and the coupling coefficient is 0.03. The self-resonance frequency of L₁ is 37 GHz, and the self-resonance frequency of L₂ is 22.5 GHz. Figure 10a shows the simulated S₂₁ of the reference single-band filter and the implemented dual-band improved filters. It shows the simulated S₂₁ of the output buffer filter with (L₃, C₃) to short the 1st harmonic and (L₅ and C₇) to block the 2nd harmonic from the output. Figure 10b shows a simulated full-span spectrum without a filter. Figure 10c shows the simulated full-span spectrum with a filter. The 2nd harmonic is suppressed by 2.546 dB compared to that in Figure 10b, and the 1st harmonic is further suppressed.

Figure 11 shows a block diagram of the ×3 ILFM. The injection FETs M₃ and M₄ are switched on and off cyclically. We can express the drain current i_d1 (i_d2) of M₃ (M₄) by memory-less nonlinear Taylor series expansion, as shown below:

$$i_{d1}=i_0+a_1{\mathrm{v}}_{\mathrm{gs}}+a_2{\mathrm{v}}_{\mathrm{gs}}^2+a_3{\mathrm{v}}_{\mathrm{gs}}^3+a_4{\mathrm{v}}_{\mathrm{gs}}^4+\dots ,$$

(3)

where v_gs = A cos(ω_RFt) is the fundamental gate input signal. In first order approximation, the output drain current I_2inj = B cos(2ω_RFt). The filter L₁, parasitic capacitor C_p and −G_m form an oscillator. The mixer1 (M₃)/mixer2 supplies the 2nd drain harmonic current to the inductor L₅ to form a 2nd voltage at the node F₂, which is a virtual ground for the odd signals. The input signal ω_RF+ mixes with 2ω_RF to supply an output signal 3ω_RF+. The linear mixer M₃ (M₄) uses the input–output frequency relationship given by ω_RF+ + 2ω_RF = 3ω_RF+, where ω_RF+/3ω_RF+ is the frequency of the injection signal/the frequency of the mixer output signal.

3.2. Experimental Results

The ×3 ILFM has been designed in the TSMC 0.18 μm 1P6M CMOS technology. The die micrograph occupying an area of 1.129 × 0.76 mm² is shown in Figure 12. Figure 13a shows the measured free-run full-span spectrum. The carrier is at 13.91 GHz and its power is −5.318 dBm. Figure 13b shows the measured locked full-span spectrum. At V_DD = 0.7 V, the power consumption is 10.5 mW. The carrier is at 13.84 GHz and its power is −16.93 dBm. It contains the 1st harmonic with an output power of −37.58 dBm, the 2nd harmonic with an output power of −42.28 dBm, and the peak 3rd harmonic. Figure 14 shows the measured phase noise of the injection source at f_inj = 6.1 GHz. The phase noise at 1 MHz is −111.845 dBc/Hz. It also shows the measured phase noise of locked ILFT. The phase noise at 1 MHz is −103.38 dBc/Hz. At 100 K offset, the measured phase noise degeneration is close to the theoretical phase noise degeneration. At 1 M offset, the measured phase noise is beyond the theoretical phase noise and is caused by the phase noise of the free-running ×3 ILFM. Figure 15 shows the measured output sensitivity plot with different V_DD. As the V_DD increases, the output sensitivity plot shifts to a lower frequency.

4. Multiply-by-6 ILFM

A conventional ×6 ILF was designed with five spiral inductors. This section details a compact ×6 ILFM with one inductive component consisting of an orthogonal trifilar due to two 8-shaped inductors and one non-twisted inductor. One inductive trifilar [15] with one 8-shaped inductor was used in a power amplifier.

4.1. Circuit Design

The schematic of the ×6 ILFM circuit is shown in Figure 16. The circuit block diagram of the current-reused ×6 ILFM is similar to that shown in Figure 1b. Figure 1a uses the intrinsic frequency doubler. Figure 16 uses a balanced frequency doubler. The cross-coupled nMOS transistors M₁ and M₂ and two-turn center-tapped 8-shaped inductors made of L₂ and a parasitic capacitor form a VCO used as a first-harmonic injection-locked oscillator (ILO) with two injection nFETs M₃ and M₄. A differential injection signal at the frequency f_inj is applied to the gates of M₃ and M₄, with gate biasing at V_in, sharing a common non-twisted inductor L₃. The common-source node V_v of M₅ and M₆ is a virtual ground for the fundamental signal. NFETs M₅ and M₆, and one-turn 8-shaped inductor L₁ form the balanced frequency doubler. Transistor M₇ is the output buffer for the extraction of the 6f_inj signal, and the locking range of the 1st harmonic ILO determines the locking range of the ×6 ILFM. Components R₁~R₃ are for DC biasing, and V_bias is the gate bias voltage. The nMOS VCO is used as a 1st harmonic ILO with the output oscillation frequency locked to the signal at 3f_inj, in case the frequency 3f_inj falls in the locking range of the 1st harmonic ILO. No buffer is used for the ILO; this reduces the parasitic capacitance and increases the locking range.

Figure 17 shows the layout of an inductive passive. The outer two-turn non-twisted inductor is L₃. The inner one-turn twisted inductor is L₁. The intermediate two-turn 8-shaped inductor is L₂. The input of the two-turn 8-shaped inductor starts from the bottom right-hand outer turn and then goes to the left-hand inner turn of the top lobe. Figure 16 also shows the simulated current density distribution. The current at L₂ is the highest. At 5.3 GHz, as shown in Figure 18, the simulated inductance of L₁ (L₂, L₃) is 1.09 (6.17, 4.61) nH, and the simulated Q-factor of L₁ (L₂, L₃) is 5.23 (7.85, 5.73). The simulated coupling coefficient of k₁₂ (k₁₃, k₂₃) is 0.001 (0.002, 0.036), which indicates that the three inductors are almost orthogonal. The simulated self-resonant frequency of L₁ (L₂, L₃) is 17 (9, 8.3) GHz.

Figure 19a shows the simulated voltage waveforms under the locked condition. An injection signal is applied to the gate of M₃ (M₄). The frequency doubler is found at the common source of M₃ and M₄. The frequency tripler is found at the source of M₃. The frequency sixtupler is found at the drain of M₇. Figure 19b shows the simulated output sensitivity of the ×6 ILFM at three biases. The locking range at the injection gate bias V_in = 0.61 V is the largest. Figure 19c shows the simulated 6th, 2nd, and 3rd harmonic output power of the locked ×6 ILFM versus input power.

4.2. Experimental Results

The die micrograph is shown in Figure 20. The total area, including the output buffer and the pads, is 0.843 × 0.981 mm². At the power consumption of 13 mW, Figure 21a shows the measured free-run output spectrum of the unlocked ×6 ILFM at 5.21 GHz with an output power of −6.747 dBm. Figure 21b shows the measured free-run full-span output spectrum of the ×6 ILFM. It has the 1st harmonic at 2.65 GHz with an output power of −24.77 dBm. Figure 22a shows the measured locked output spectrum of the ×6 ILFM at 5.22 GHz with an output power of −7.318 dBm. Figure 22b shows the measured locked full-span output spectrum of the ×6 ILFM. It has a 3rd harmonic at 2.65 GHz with an output power of −23.49 dBm and a 6th harmonic at 5.22 GHz.

Figure 23 shows the measured phase noises of the locked ×6 ILFM at 0 dBm input power and injection reference. At 1 MHz offset, the phase noise of ILFS/injection reference is −125.87/−140.86 dBc/Hz. Figure 24 shows the measured output sensitivity of the ×6 ILFM biased at V_DD = 1.3 V with the output locking range, at 0 dBm input power P_INJ, from 5.16 GHz to 5.388 GHz. The locking range increases with P_INJ. Figure 25 shows the measured harmonic output power of the locked ×6 ILFM at f_in = 0.869 GHz; the measured harmonic output power is lower than the carrier output power by more than 17 dBm. Figure 26 shows the measured locking range output sensitivity. As V_DD increases, the sensitivity plot shifts to a lower frequency.

Table 1. Performance comparison of standalone CMOS LC ILFMs.

Ref. ×2	Tech (nm)	Inductor Structure	Pin (dBm)	Vdd(V) Pdis(mW)	Die Area (mm2)	FOM	Locking Range (GHz)
[4] TMTT 2016 ×2	65	Spiral tran	0	1/9	0.39 × 0.41	3.2	71~95.0 (28.9%)
[3] EuMIC 2022 ×2	45	Spiral indu	0	1/5–11	0.12	4.55~	14.0~17.6 (22.78%)
[2] JSSC 2010 ×2	65	Spiral indu	3	1/6	0.014	2.18	106~128 (13.1%) *
[12] ISOCC 2024 ×3	180	8-sha tran	0	0.65/3.25	1.146 × 0.484	10.75 **	7.2~10.25 (34.95%) **
[9] Access 2023 ×6	90	Spiral indu	0	0.4/9.03	0.49	1.13	39~43.2 (10.21%)
[8] Access 2022 ×6	180	Spiral indu	0	1/20.8	1.141 × 1.2	0.4947	5.62~6.23 (10.29%)
This 1 ×2	180	8-sha tran	0	1.5/3.966	1.137 × 0.797	15.347	3.2~6 (60.96%) *
This 2 ×3	180	8-sha tran	0	0.7/10.5	1.129 × 0.76	7.14	3~6.6 (75%) ***
This 3 ×6	180	8-s trifilar	0	1.3/13	0.843 × 0.981	0.3325	5.16~5.388 (4.32%)

FOM = lock range (percent)/ power (in mW). * Output frequency locking range. ** with frequency tuning. *** Input replaces output locking range. This (1, 2, and 3) refer to the three different frequency multiplier (×2, ×3, ×6).

compares the performance of the implemented ILFMs with an 8-shaped inductor against various CMOS ILFMs by using FOM = Lock Range (percent)/Power (in mW).

5. Conclusions

This paper reviews our LC-tank ILFMs with 8-shaped inductors for suppressing magnetic coupling noise, which utilize an orthogonal transformer to reduce die area. Compared to existing ILFMs, this paper utilizes single-inductor elements for the LC-tank ILFMs. The orthogonal low-k transformer was implemented in a ×2 and a ×3 ILFM, and the low-k trifilar was implemented in a ×6 ILFM to verify its function and conserve die area. All ILFMs exhibit a well-defined locking range and phase noise, and they also suppress coupling noise due to the use of an 8-shaped inductor in the ILO with a high voltage swing. The proposed inductor approach can be extended to mm-wave ILFM design.