Grain Boundary Engineering for High-Mobility Organic Semiconductors

Abstract

Grain boundaries are among the most influential structural features that control the charge transport in polycrystalline organic semiconductors. Acting as both charge trapping sites and electrostatic barriers, they disrupt molecular packing and introduce energetic disorder, thereby limiting carrier mobility, increasing threshold voltage, and degrading the stability of organic thin-film transistors (OTFTs). This review presents a detailed discussion of grain boundary formation, their impact on charge transport, and experimental strategies for engineering their structure and distribution across several high-mobility small-molecule semiconductors, including pentacene, TIPS pentacene, diF-TES-ADT, and rubrene. We explore grain boundary engineering approaches through solvent design, polymer additives, and external alignment methods that modulate crystallization dynamics and domain morphology. Then various case studies are discussed to demonstrate that optimized processing can yield larger, well-aligned grains with reduced boundary effects, leading to great mobility enhancements and improved device stability. By offering insights from structural characterization, device physics, and materials processing, this review outlines key directions for grain boundary control, which is essential for advancing the performance and stability of organic electronic devices.

1. Background and Introduction

In organic semiconductors, charge transport is not solely determined by molecular order or packing density [1,2,3,4,5,6,7,8], but is equally shaped by the underlying energetic landscape described by the density of states (DOS) [9,10,11,12,13,14,15]. While delocalized states in highly ordered crystalline systems support coherent band-like transport, structural imperfections and energetic disorder introduce localized states, which are commonly referred to as trap states within the band gap [16,17,18,19,20]. Among these imperfections, grain boundaries are especially critical as they often serve as sites for trap localization [21,22,23]. These localized states impact carrier mobility by temporarily capturing charges, thereby disrupting the flow of current [24,25,26]. Depending on their energetic position relative to the band edges, traps may be shallow, which still allows carriers to be thermally released, or traps may be deep, where recombination and permanent carrier loss become significant [27,28,29]. In addition to intrinsic disorder, the incorporation of guest molecules into the host matrix can further modulate trap behavior by introducing additional trap or anti-trap states [30,31,32]. As a result, understanding the formation and distribution of traps and particularly at grain boundaries becomes essential for interpreting the charge transport behavior in polycrystalline and amorphous organic semiconductors.

1.1. Grain Boundaries as Charge Carrier Traps

Here we begin by examining four representative DOS models commonly used to describe different classes of organic semiconductors: crystalline systems with well-defined band edges, weakly disordered materials with exponential tail states, and highly disordered polycrystalline or amorphous systems modeled using Gaussian or exponential distributions [33,34,35,36,37,38,39,40,41,42]. Beyond the DOS for extended states, localized trap states, which originate from structural imperfections, chemical impurities, or energetic disorder, also play a critical role in charge dynamics [43,44,45]. Shallow traps, located near the Highest Occupied Molecular Orbital (HOMO) or Lowest Unoccupied Molecular Orbital (LUMO) edges, can capture carriers temporarily and enable thermally assisted multiple-trap-and-release transport [46,47,48]. In contrast, deep traps act as recombination centers, which may reduce carrier lifetime and mobility [49,50,51,52]. Furthermore, depending on their relative energy levels, guest molecules incorporated into host lattices can introduce additional trap or anti-trap states, which can alter the transport behavior [32].

To illustrate how these states arise and influence charge conduction pathways in organic semiconductors, Figure 1a–d show four common types of DOS profiles used to describe the energetic distribution of electronic states in different classes of semiconductors. In Figure 1a, the DOS of a perfectly ordered crystalline semiconductor, such as crystalline silicon (c-Si), follows a parabolic distribution with sharply defined valence (E_V) and conduction (E_C) band edges, resulting in a well-defined energy gap. Figure 1b depicts a semiconductor with weak disorder, such as amorphous silicon (a-Si), where extended states gradually decay into the band gap and form exponential tail states. In such systems, the precise band edges are ill-defined, and a mobility edge is introduced to differentiate extended from localized states. Figure 1c shows the DOS in highly disordered semiconductors, including many polycrystalline organic semiconductors, where the DOS for the HOMO and LUMO levels resembles Gaussian functions. Here, the energy gap is defined between the onsets of the HOMO and LUMO tails. Finally, Figure 1d represents another model for disordered semiconductors, where the DOS decays exponentially from the HOMO and LUMO edges into the gap. These models highlight how structural disorder, molecular packing, and electronic localization determine the DOS shape, which in turn controls the charge transport behavior in the semiconductor systems.

Figure 1e illustrates the nature and transport implications of electronic traps in organic semiconductors. On the left, the trap DOS function shows the distribution of trap states within the band gap, with shallow traps (black) concentrated near the band edges and deep traps (red) located further away. These localized electronic states arise from imperfections in the semiconductor and are energetically distributed according to their depth from the conduction (LUMO) or valence (HOMO) band edges. Shallow traps, which are typically tail states, are situated within a few kT of the band edges and can often release trapped carriers back into the band via thermal activation, particularly in the multiple-trap-and-release process shown by the blue arrows. In contrast, deep traps, which are several kT away, act as recombination centers and are unlikely to thermally release carriers, reducing their mobility and lifetime. On the right, the spatial and energy diagram depicts transport mechanisms influenced by these traps: band-like transport occurs through delocalized states (black arrows), multiple trap and release involves transient trapping and release from shallow states (blue arrows), and hopping transport (orange arrows) occurs between localized states when trap density is high. This highlights how both the energetic depth and spatial distribution of traps fundamentally determine the dominant charge transport regime in organic semiconductors.

Figure 1f presents four hypothetical cases, shown from left to right, that illustrate how guest molecules incorporated into a host semiconductor lattice can generate trap or anti-trap states affecting charge transport. In the leftmost diagram, both electron and hole traps are introduced because the LUMO and HOMO levels of the guest fall within the energy gap of the host. This situation is exemplified by tetracene-doped anthracene crystals, where electron traps appear near the conduction band and hole traps appear near the valence band, leading to a decrease in mobility, especially for holes. In the second diagram, only hole traps are formed when the guest HOMO lies within the gap, as in the case of phenothiazine-doped anthracene, where a hole trap at 0.8 eV above the valence band was detected. The third diagram represents an energetically inert guest, whose ionization energy is higher and electron affinity is lower than those of the host, preventing the formation of traps. Though not directly associated with trapping, such guests still disturb the lattice locally and act as scattering centers, depending on their concentration. In the rightmost diagram, only electron traps are created by the guest molecule, with trap levels situated below the conduction band, as observed in anthracene doped with compounds like acridine and phenazine. Together, these cases show how the alignment of guest and host energy levels determines the trapping behavior and ultimately affects charge carrier mobility in organic semiconductors.

1.2. Grain Boundaries as Potential Barriers

Grain boundaries in organic semiconductors can also serve as electrostatic barriers that impede the movement of charge carriers by creating localized energetic obstacles [53,54,55]. These regions often trap carriers and generate a surrounding space-charge region, which repels other carriers of the same type. This leads to a built-in potential and local band bending, particularly downward in p-type semiconductors where holes are trapped [56]. The resulting energy barrier, often referred to as the barrier height, determines how easily carriers can move across the boundary [57,58]. Thermal activation enables carriers to overcome this barrier, while tunneling may become significant at lower temperatures.

Horowitz et al. explore the influence of grain boundaries on charge carrier mobility in polycrystalline organic thin-film transistors (OTFTs) made with vacuum-deposited oligothiophenes [59]. Their study reveals that grain boundaries serve as key sites for trap localization, which in turn act as energy barriers to carrier transport. Mobility in these polycrystalline films increases with grain size. In particular, small grains exhibit thermally activated mobility consistent with the presence of barriers at grain boundaries, while larger grains demonstrate temperature-independent mobility at low temperatures, suggesting a transition to tunneling-dominated transport across grain boundaries. The authors propose a model in which traps are not uniformly distributed throughout the film but are concentrated at grain boundaries. These boundaries create potential barriers that carriers must overcome either by thermal activation (dominant at high temperatures) or by quantum tunneling (dominant at low temperatures). The barrier height depends on the grain size relative to the Debye length, with larger grains resulting in more significant barrier effects. Experimental results from this study, including scanning electron microscopy and temperature-dependent mobility measurements, support this model and show a near-linear relationship between mobility and grain size.

Verlaak et al. presented a detailed model explaining how grain boundaries influence charge transport in polycrystalline organic semiconductor films, particularly in pentacene-based thin-film transistors [60]. The authors propose a grain boundary barrier model in which an energy distribution of interfacial trap states rather than a single trap level is responsible for charge trapping at grain boundaries. These trapped charges, located in the amorphous regions between crystalline grains, repel mobile charges of the same sign and lead to the formation of a space-charge region (SCR). The SCR generates a potential barrier that charge carriers must overcome via thermionic emission, which limits mobility. The model shows that the barrier height is influenced by both the density of trapped charges at the grain boundaries and the doping concentration in the grains. Higher doping results in better screening of trapped charges, thus reducing the SCR width and lowering the barrier, which enhances mobility. Unlike other models (e.g., multiple-trap-and-release or potential well models), this approach distinguishes itself by predicting that mobility is more strongly affected by dopant concentration than by gate voltage, due to the differing screening mechanisms involved. This behavior aligns with experimental observations where unintentionally doped films showed higher mobilities compared to purified ones with similar morphologies. Additionally, the model explains channel-length-dependent mobility, where shorter channels show higher mobility due to fewer grain boundaries and stronger local electric fields that lower the potential barrier. Overall, the findings underscore that grain boundaries are not just structural interruptions but electrostatic barriers shaped by trap distributions and doping, and they play a pivotal role in determining the transport properties of polycrystalline organic semiconductors.

1.3. Grain Width-Dependent Model

Controlling the grain width and grain boundary dimension of organic semiconductors is important in minimizing defects and deformities at crystalline grain boundaries. These defects and deformities can act as trap centers of charge, which adversely affect charge carrier transport. By increasing the grain size, there are fewer boundaries and defects, which expedites the transport of charge carriers. One way to assess the impact of grain boundary defects and deformities on organic semiconductor charge transport is through the “grain width-dependent mobility model” [61]. For instance, the channel can be expressed as having a length of L.

$$L=n{L}_G+(n-1)L_{GB}$$

(1)

The crystal length, $L_G$, and grain boundary length, $L_{GB}$, along with the number of grain boundaries, n, are used to calculate the total effective mobility, ${\mu }_E$. It is important to note that $L_{GB}$ has a small dimension of 1–2 nm and is connected in series. When L is much larger than $L_{GB}$, the expression for ${\mu }_E$ can be derived.

$${\displaystyle \frac{L}{{\mu }_E}}={\displaystyle \frac{L-(n-1)L_{GB}}{{\mu }_G}}+{\displaystyle \frac{(n-1)L_{GB}}{{\mu }_{GB}}}$$

(2)

The mobility of crystal grains and grain boundary are represented by ${\mu }_G$ and ${\mu }_{GB}$, respectively. Combining Equations (1) and (2) results in the following expression:

$${\displaystyle \frac{1}{{\mu }_E}}={\displaystyle \frac{1}{{\mu }_G}}+n({\displaystyle \frac{L_{GB}}{L{\mu }_{GB}}}-{\displaystyle \frac{L_{GB}}{L{\mu }_G}})$$

(3)

Given the enormous magnitude of n, the equation above approximates (n − 1) to n. There exists a correlation between the width of the grain, $W_G,$ and its length, $L_G$.

$$\mathit{sin}\theta ={\displaystyle \frac{W_G}{L_G}}={\displaystyle \frac{n{W}_G}{L}}$$

(4)

$$n={\displaystyle \frac{Lsin\theta }{W_G}}$$

(5)

Since $A={\displaystyle \frac{1}{{\mu }_G}}$ and $B=sin\theta L_{GB}({\displaystyle \frac{1}{{\mu }_{GB}}}-{\displaystyle \frac{1}{{\mu }_G}})$, Equation (5) can be merged into (3):

$${\displaystyle \frac{1}{{\mu }_E}}=A+{\displaystyle \frac{B}{W_G}}$$

(6)

The mobility model described in Equation (6) is known as the “grain width-dependent model”. It states that the effective total mobility ${\mu }_E$ increases proportionally with an increase in grain width. This means that a fixed channel with a larger grain width will have a higher effective mobility. To reduce the amount of crystalline defects and trap centers, it is preferable to have crystals with larger grain width given a fixed channel dimension. The dimension of organic crystal grains and organic semiconductor crystallization can be affected by several factors, including solvent choice, polymer additive, and external alignment and patterning.

Figure 2 further supports this model by directly visualizing the relationship between grain width and device performance in solution-processed 6,13-bis(triisopropylsilylethynyl)pentacene (TIPS pentacene) transistors. In Figure 2a, transfer characteristics of two devices reveal that the one with narrower grains (10 μm) exhibits more pronounced hysteresis and lower drain current, while the device with wider grains (300 μm) demonstrates enhanced current output and reduced hysteresis, highlighting the detrimental effect of frequent grain boundaries on charge transport. Figure 2b plots saturation mobility as a function of average grain width, showing a sharp increase in mobility beyond 6 μm, where the grain morphology transitions from equiaxed domains to elongated needle-like crystals. This morphological transition is illustrated in Figure 2c,d: needle-shaped grains are characterized by a long grain length L_G and narrower width W_G, oriented primarily along the axis, which minimizes the number of grain boundaries encountered along the transport path; in contrast, equiaxed grains, observed when W_G < 4 μm, lead to frequent grain boundary interruptions. Together, they demonstrate that promoting anisotropic, aligned grain growth is key to suppressing boundary-induced scattering and achieving higher mobility, in agreement with the grain width-dependent model.

1.4. Impact of Grain Boundary on Electrical Performance of OTFTs

Grain boundaries have a fundamental impact on charge transport in organic semiconductors by disrupting molecular packing and introducing localized trap states and energetic barriers [62,63,64,65,66]. In single-crystalline organic semiconductors, where conjugated molecules are tightly and uniformly arranged, carriers can move coherently through delocalized states, exhibiting band-like transport [67,68,69,70]. However, in polycrystalline films, the presence of grain boundaries interrupts these transport pathways, leading to carrier localization [71,72,73]. As a result, the transport mechanism transitions from band-like to thermally activated modes such as hopping or multiple trap and release, especially at higher temperatures where thermal energy assists carriers in overcoming the barriers posed by grain boundaries. This transition is reflected in the temperature dependence of mobility: while ideal band-like systems show decreasing mobility upon cooling, polycrystalline films with high grain boundary density often show the opposite trend. Moreover, grain boundaries can distort Hall effect measurements, suppressing Hall mobility relative to field-effect mobility due to their influence on free carrier distribution and motion [74,75,76,77]. Therefore, the density, orientation, and distribution of grain boundaries, which are largely determined by processing conditions, are key factors in defining whether charge transport in an organic semiconductor remains coherent or becomes trap-limited.

In addition to influencing charge transport, grain boundaries also degrade the electrical performance of OTFTs [78,79,80,81]. Grain boundaries serve as sites for charge trapping and potential barriers, which reduce mobility and shift the threshold voltage by requiring a higher gate voltage to induce a conductive channel. These trapped charges can elevate the off-state current, decreasing the on/off current ratio, which is an important figure of merit in transistor operation. Moreover, grain boundaries introduce charge instability that results in hysteresis between forward and reverse gate voltage sweeps, reflecting delayed charge responses and reduced switching reliability [82,83,84,85,86]. The negative impact of grain boundaries is most pronounced in the early layers of OSC films, where carriers are forced to move laterally through high-resistance boundaries. However, increasing the film thickness can allow vertical transport pathways that partially bypass the grain boundaries. Overall, grain boundaries compromise key performance indicators such as mobility, threshold voltage, current on/off ratio, and switching uniformity, making their control essential for high-performance organic transistor design.

Grain boundaries also pose a big challenge to the long-term stability of OTFTs, particularly in terms of operational and environmental robustness [87,88,89,90]. Under prolonged gate bias, grain boundaries act as preferential sites for charge trapping, leading to gradual shifts in threshold voltage, reduced mobility, increased subthreshold slope, and intensified hysteresis. These instability effects are amplified in devices with high grain boundary density, where more trapping sites accelerate performance degradation over time. In addition to operational instability, grain boundaries are highly sensitive to environmental conditions [91,92,93]. Exposure to ambient air allows oxygen and water molecules to infiltrate grain boundary regions, where they introduce additional trap states or interact with the OSC lattice, distorting its structure. These environmental interactions reduce mobility and alter threshold voltage, which undermines the storage stability of the devices. In contrast, single-crystal OTFTs, which lack grain boundaries, maintain much more stable electrical performance during extended storage. The underlying mechanisms include both the diffusion of small molecules into grain boundaries and the thermally driven rearrangement of OSC molecules at boundary regions into less optimal configurations. Therefore, grain boundaries are not only obstacles to immediate device performance but also active sites that accelerate long-term degradation under bias and environmental exposure.

The introduction provides an overview of the important role grain boundaries play in determining charge transport behavior in organic semiconductors. It explains that charge mobility is governed not only by molecular order but also by DOS. Various DOS models are discussed, ranging from ordered crystalline to highly disordered systems, along with the energetic and spatial characteristics of shallow and deep traps. This section also illustrates how guest molecules can introduce or suppress traps, influencing mobility. Grain boundaries are further shown to function as electrostatic barriers due to space-charge regions formed by trapped carriers, with their impact dependent on grain size and doping levels. The grain width-dependent mobility model is introduced to describe how grain size correlates with mobility, supported by experimental data from TIPS pentacene transistors. Finally, the section emphasizes the detrimental impact of grain boundaries on the performance and stability of OTFTs, highlighting their influence on mobility, threshold voltage, hysteresis, and degradation under bias and environmental exposure. This sets the stage for the review’s focus on strategies to mitigate grain boundary effects and optimize organic electronic device performance. The goal of this review is to explore how grain boundary engineering strategies influence charge transport in polycrystalline organic semiconductors and to establish structure-specific guidelines for optimizing device performance. Rather than testing a singular hypothesis, this work addresses a central question: how can processing methods be tailored to control grain boundary structure and reduce trap-related transport limitations? By comparing the effectiveness of these approaches across representative high-mobility semiconductors, we aim to extract generalizable principles that can inform future material-specific optimization and the broader design of high-performance organic electronic devices.

2. Methods for Grain Boundary Engineering

Controlling the crystallization behavior of organic semiconductors is essential for optimizing film morphology, grain size, and device performance. Among the many strategies available, the use of solution-based methods provides a highly tunable platform for influencing crystallization during film formation. This section explores three key approaches, including solvent choice, polymer additives, and external alignment techniques, which have proven effective in modulating grain width and boundary characteristics. The term “engineering” refers to the intentional manipulation of processing conditions to control grain boundary structure and morphology in order to optimize charge transport in organic semiconductors. By tailoring solvent properties, incorporating specific polymers, or applying physical alignment strategies, researchers can achieve precise control over crystal growth and microstructure, thereby enhancing the uniformity and electronic properties of organic semiconductor films.

2.1. Solvent Choices

The selection of solvents plays a role in regulating the crystallization behavior of organic semiconductors, leading to variations in grain size and boundary dimensions [94,95,96,97]. Solvents with high boiling points promote longer crystal growth times for organic semiconductors than those with low boiling points. When grown in high-boiling-point solvents, organic semiconductors typically exhibit wider grain widths and reduced grain boundaries. Using binary solvents is particularly intriguing for effectively manipulating semiconductor crystallization and grain size [98,99,100,101,102]. In binary solvents, two different solvents are used, one being the primary solvent and the other an additive. The dissimilarity in molecular structure between the solvents and their affinity influence the intermolecular interactions, such as solute/solvent, solute/solute, and solvent/solvent interactions, which determine the intensity of the solution [103,104,105]. Choosing the appropriate binary solvents requires consideration of the dielectric constant, boiling point, and Hansen’s solubility parameters, among other factors of the solvents. A higher polarity of the solvent and improved ability to stabilize charges in the solvent are a result of a large dielectric constant. When two solvents have similar boiling points, they can maintain a simultaneous evaporation profile, which allows for easier control of the crystallization process of organic semiconductors. The binary solvent affinity and solubility are determined by Hansen’s solubility parameters, which consider the polar component, dispersive component, and hydrogen bonding component as the intermolecular interaction force [106,107,108]. The mismatch parameter R can be calculated using ${\partial }_p$, ${\partial }_d$, and ${\partial }_h$:

$$R=\sqrt{∆{\partial }_P^2+∆{\partial }_d^2+∆{\partial }_h^2}$$

(7)

The smaller the mismatch parameter, as described in Equation (7), the better the solubility of a solute in a potential solvent with similar Hansen’s solubility parameters. On the other hand, low solubility is indicated by a large mismatch parameter.

2.2. Polymer Additives

Additives based on polymers, including amorphous, conjugated, and semicrystalline types, have been utilized to adjust the morphology, crystallization, alignment, and grain dimensions of organic semiconductors. This modulation enhances the device performance and charge carrier mobility of semiconductor devices. An interesting point to note is that these polymer additives can be used independently to regulate the semiconductor crystallization without any external alignment methods [109,110,111], which simplifies the experimental setup. In particular, amorphous polymers that enhance semiconductor morphology, decrease crystal misorientation and increase the size of grains have been reported, including poly(α-methylstyrene) (PαMS) [112,113,114,115], polystyrene (PS) [116,117,118,119,120,121], and poly(methylmethacrylate) (PMMA) [122,123,124,125,126,127,128]. Additionally, conjugated polymers such as poly(3-hexylthiophene) (P3HT) and regiorandom pentacene-bithiophene polymer (PnBT-RRa) [129,130,131,132,133,134,135,136,137,138] have similar effects to amorphous polymers in controlling semiconductor growth, morphology and grain size. Conjugated polymers facilitate intermolecular interactions with organic semiconductors, providing an extra way to reinforce π-π and hydrophobic interactions and manipulate morphological features. The resultant properties of the organic semiconductor/conjugated polymer mixed film can differ depending on several important material properties of the conjugated polymers, including their chemical structure, molecular weight, polydispersity, and regioregularity. Semicrystalline polymers, which possess properties from both amorphous and crystalline nature, provide a unique opportunity to fine-tune the crystallization and grain dimension of organic semiconductors.

2.3. External Alignment

In enhancing organic crystal growth in solution, morphology uniformity, and grain dimensions, external alignment and patterning methods are highly sought after. This has led to numerous studies, with various external alignment methods falling under the categories of substrate patterning [139,140,141,142], air flow [143,144], and blade coating [145,146,147,148]. In particular, substrate patterning-based methods utilize photolithography and/or surfactant treatment to alter substrate wettability, ultimately affecting solution dewetting behavior on the substrate. Crystallization in the deposited solution can be confined to wettable regions, allowing for easy tuning of the resulting grain dimension by controlling the wettability dimension. Techniques involving air or inert gas injection during the crystallization process of organic semiconductors can effectively modulate solute diffusion, improve crystal alignment, and enhance the long-range order of the semiconductors. These techniques can also reduce the coffee ring effect and tune the grain dimension. Blade coating, which uses a movable blade or substrate and a coating head, can control active layer thickness, morphology, contact resistance, and grain dimension by optimizing deposition speed, blade distance, and viscoelastic properties.

To summarize this section, grain boundary engineering in organic semiconductors can be effectively achieved through solvent optimization, polymer additive incorporation, and external alignment techniques. Each method offers unique advantages in tailoring crystal growth, improving grain orientation, and minimizing grain boundary density. Together, these strategies provide a useful way of controlling film morphology and enhancing charge transport properties, laying the foundation for high-performance organic electronic devices.

3. Case Studies of Grain Boundary Engineering

Grain boundaries represent one of the most significant bottlenecks in the performance of organic semiconductors, acting as both physical and energetic barriers to charge transport. This section presents a series of case studies that examine how grain boundary engineering has been employed across various benchmark small-molecule semiconductors, including pentacene, TIPS pentacene, diF-TES-ADT, and rubrene, with the goal of understanding and mitigating their detrimental effects. Through carefully designed experiments and advanced characterization techniques, these studies reveal how processing parameters such as deposition temperature, solvent system, polymer blending, and substrate treatment influence grain size, boundary density, alignment, and electrical properties. Collectively, they highlight that while grain boundaries can severely hinder charge mobility by introducing traps and increasing resistance, targeted engineering strategies, such as promoting large crystalline domains, reducing misorientation, or aligning grains, can enhance charge transport and device reliability.

3.1. Pentacene

Pentacene is a prototypical small-molecule organic semiconductor that has attracted extensive attention for its exceptional charge transport properties and well-defined molecular structure [149,150,151]. It consists of five linearly fused benzene rings, forming a highly conjugated planar backbone that facilitates strong intermolecular π-π stacking. Pentacene tends to form layered crystalline structures with anisotropic charge transport primarily along the molecular stacking direction. It is typically deposited via thermal evaporation, resulting in thin films with polycrystalline domains. Pentacene exhibits p-type semiconducting behavior with intrinsic hole mobilities often exceeding 1 cm²/Vs in optimized single-crystal devices [152,153,154,155]. These properties, combined with its relatively low fabrication cost and compatibility with large-area electronics, have made pentacene a benchmark material for thin-film transistors. However, despite its promising characteristics, pentacene thin films commonly exhibit polycrystalline morphologies, where the presence of grain boundaries introduces limitations [156,157,158,159,160,161,162]. These grain boundaries can act as energetic barriers and trap sites, which disrupt the continuity of charge transport pathways and lead to reduced mobility, increased contact resistance, and degraded device stability. Furthermore, the presence of structural disorder at these interfaces can enhance sensitivity to environmental factors such as moisture and oxygen. Understanding how grain boundaries influence the electrical behavior of pentacene is therefore important for improving the performance of organic electronic devices. In this section, we review several foundational studies that focus on the role of grain boundaries in pentacene and highlight their impact on charge carrier mobility, trap density, and environmental responsiveness, which provide insights into controlling crystallization and microstructure to mitigate grain boundary effects and unlocking the full potential of pentacene-based organic electronics.

Edura et al. explored how electrical transport differs across individual crystalline regions and the interfaces between them in pentacene films [163]. By combining electron beam and optical lithography, they fabricated microscale electrode layouts that enabled high-precision resistance and current measurements within isolated grain interiors and their adjoining boundaries. The active semiconductor layer was deposited using molecular beam epitaxy, yielding high-purity pentacene structures. Their findings revealed that current flow through a single crystal region was nearly ten times greater than across a boundary, with corresponding hole mobilities of 5 cm²/Vs within the grain and 0.3 cm²/Vs across the boundary. Resistance measurements further confirmed this disparity, estimating 10 MΩ for the grain and 100 MΩ at the grain interface. This study stands out for its direct and quantitative dissection of charge transport mechanisms within organic semiconductor microstructures. By separately characterizing intra-grain and inter-grain electrical properties, it provided some of the first clear experimental evidence quantifying the detrimental impact of grain boundaries on mobility. Moreover, the precise fabrication and measurement techniques demonstrated in this work offer a model approach for future studies on grain-level phenomena in organic thin-film devices. The large contrast in mobility and resistance highlights the critical role of microstructure in determining device performance, as well as the impact of engineering grain boundaries in high-performance organic electronics.

Schön et al. examined how variations in substrate temperature during deposition influence the microstructure and electronic behavior of pentacene films [164]. By adjusting the spacing between the evaporation source and the substrate, they effectively tuned the thermal conditions under which pentacene layers formed. This gradient in growth temperature led to systematic changes in crystal size, with higher thermal energy producing larger grains and reducing grain boundary density, as shown in the optical images of Figure 3. Devices constructed from single-crystal films exhibited peak hole mobility of 3.2 cm²/Vs. In contrast, polycrystalline films grown at progressively cooler temperatures demonstrated degraded performance, with mobilities falling to 2.4, 2.1, 1.2, and eventually 0.2 cm²/Vs. The data revealed that grain boundaries and associated trap states played a great role in suppressing charge transport as deposition temperature dropped. This research offers clear experimental validation of the relationship between processing temperature, film morphology, and device mobility, which makes it highly valuable for guiding thin-film fabrication in organic electronics. By directly linking thermal conditions to grain boundary formation and transport properties, this work provided a practical framework for optimizing semiconductor performance via deposition control. The stark mobility contrast between high- and low-temperature-grown films, which spanned over an order of magnitude, highlights the impact of grain boundary density on charge carrier flow. Moreover, their findings emphasize how trap density escalates with increased boundaries and show the degradation mechanisms that limit the performance and stability of OTFTs.

Minari et al. investigated how charge transport in pentacene is influenced by grain boundaries, based on single-crystal and polycrystalline films [165]. Their study demonstrated that transistors based on single-crystal pentacene exhibited a hole mobility of up to 2 cm²/Vs, which was approximately an order of magnitude higher than devices using polycrystalline pentacene as the active layer. The research also examined the activation energy as a function of applied gate voltage and charge carrier density. In polycrystalline films, the activation energy decreased as the gate voltage increased, indicating that charge transport was dominated by extrinsic traps at grain boundaries. Conversely, in single-crystal pentacene, the activation energy showed only a slight decrease at low gate voltages and remained nearly constant at higher voltages, suggesting that charge transport in these films was governed primarily by thermally activated polarons. This study provides direct evidence of how grain boundaries impact charge transport in organic semiconductors, particularly in pentacene-based devices. By comparing single-crystal and polycrystalline films, this work quantified the impact of grain boundaries on mobility and revealed that polycrystalline films suffer from charge trapping due to extrinsic defects. This work also highlights the importance of activation energy trends in understanding transport mechanisms, distinguishing between intrinsic polaron hopping in single crystals and extrinsic trap-limited transport in polycrystalline films. These insights are fundamental for optimizing the charge transport of organic electronic devices, as they address the need to minimize grain boundaries to achieve higher mobility and better device performance.

Weis et al. investigated how varying crystal sizes in pentacene films affect charge transport properties [166]. Utilizing thermal evaporation, they controlled the deposition rate to produce films with distinct mean crystal sizes: 0.3 µm at 0.5 Å/s and 0.1 µm at 10 Å/s. Field-effect transistor measurements revealed that larger crystals exhibited a hole mobility of 4.3 cm²/Vs, whereas smaller crystals showed a reduced mobility of 0.021 cm²/Vs. Steady-state voltammetry indicated an increased presence of defects, such as pentacene quinones, at the grain boundaries of films with smaller crystals, which suggests heightened sensitivity to environmental factors such as moisture and gases. This correlation between reduced crystal size, elevated defect concentration, and diminished conductivity shows the critical role of grain boundaries in determining the electrical performance of pentacene films. This research explained the impact of microstructural characteristics on the electrical behavior of organic semiconductors. By demonstrating that smaller grain sizes lead to increased defect densities and reduced charge mobility, the study highlights the importance of optimizing deposition conditions to achieve larger crystalline domains. Such optimization is essential for developing pentacene-based applications with improved stability in varying conditions and for enhancing the performance and stability of organic electronic devices.

Jin et al. investigated how grain size influences contact resistance and grain boundary trap density in pentacene-based thin-film transistors [167]. They thermally evaporated pentacene onto substrates at 20 °C and 80 °C and obtained grain sizes of 0.2–0.3 µm and 2–4 µm, respectively. The parasitic resistance was found to be 4.2 ± 0.2 kΩ cm for smaller grains and 1.2 ± 0.2 kΩ cm for larger grains. Correspondingly, grain boundary trap densities were (1.2 ± 0.3) × 10¹² cm⁻² and (5.6 ± 0.5) × 10¹¹ cm⁻², respectively. The highest mobility observed was 0.359 ± 0.002 cm²/Vs for the 80 °C substrate with a 10 µm channel length. This research explains the direct relationship between grain size and key electrical parameters in pentacene-based thin-film transistors. Understanding that larger grains reduce contact resistance and trap density provides valuable information for optimizing organic semiconductor charge transport in high-performance organic electronics.

3.2. TIPS Pentacene

TIPS pentacene is a solution-processable derivative of pentacene widely used in organic electronics [168,169,170,171,172,173,174]. Chemically, it consists of a pentacene backbone functionalized with bulky triisopropylsilylethynyl side groups at positions 6 and 13, which enhance solubility in common organic solvents and allow for low-temperature fabrication through techniques such as spin-coating, drop-casting, and inkjet printing [175,176,177,178,179]. Physically, TIPS pentacene tends to form needle-like or ribbon-shaped crystals with strong anisotropic growth, typically aligning along the crystallographic direction [180,181]. These crystals exhibit high degrees of π-π stacking, which is important for effective charge transport. Electrically, TIPS pentacene exhibits p-type semiconducting behavior, with reported hole mobilities usually reaching 1 cm²/Vs and above in optimized thin-film transistors [182]. While it generally shows lower intrinsic mobility compared to vacuum-deposited pentacene, its solution processability and environmental stability make it highly attractive for roll-to-roll organic electronics. Studying the grain boundaries in TIPS pentacene is essential because, as in other small-molecule semiconductors, the presence of grain boundaries can introduce structural and energetic disorder. These boundaries can trap charge carriers, impact long-range transport, and reduce device performance and reproducibility. Due to the solution-based nature of TIPS pentacene deposition, crystallization dynamics are highly sensitive to processing parameters, which can lead to variable grain morphology and boundary characteristics. As such, controlling and engineering grain boundaries, by means of solvent selection, polymer additives, substrate patterning, or annealing, is a key strategy to enhance mobility and stability.

Figure 4 shows the morphological evolution of TIPS pentacene films when blended with different types of polymer additives, including the amorphous polymer PαMS, conjugated polymer P3HT, and semicrystalline polymer PEO, which compares their roles in tuning crystal alignment, grain width, and boundary density [130,181,183]. In the pristine TIPS pentacene film (Figure 4a), randomly oriented crystal needles with poor coverage and large grain widths lead to grain boundaries and mobility variations. Figure 4b shows that blending TIPS pentacene with amorphous PαMS results in elongated, uniformly aligned crystals with nearly full channel coverage and long-range order. Although the grain width decreases slightly, the rigid alignment and vertical phase segregation improve mobility and consistency, with OTFTs reaching 0.26 cm²/Vs. In contrast, the conjugated polymer P3HT (Figure 4c) modulates crystallization through π-π and hydrophobic interactions, yielding diverse morphologies depending on loading. At 2% P3HT, TIPS pentacene forms aligned needles with reduced grain width, but increasing P3HT to 25-50% generates interlinked microwires with further narrowed grains, increasing boundary density. Still, the enhanced crystal order led to a mobility of up to 8.96 × 10⁻² cm²/Vs. Figure 4d demonstrates that semicrystalline PEO enables a unique mechanism of in situ competition between its own crystallization and that of TIPS pentacene, producing highly aligned needles and dense coverage at 5–10% loading. While the grain width remains higher than in P3HT blends, the improved uniformity and interconnectivity yield OTFT mobilities up to 2.5 × 10⁻² cm²/Vs. Therefore, while all three additives effectively control TIPS pentacene morphology and grain structure, each polymer highlights different mechanisms to enhance charge transport: PαMS excels in uniform alignment and consistency, P3HT offers strong grain narrowing through molecular interaction, and PEO achieves high film uniformity via crystallization competition.

According to a study by Lee et al. [184], the impact of grain boundaries on charge transport in TIPS pentacene inkjet-printed films was examined. In this research, a polyvinyl phenol polymer was first applied as the gate dielectric layer, and then gold was deposited as the source and drain contact electrodes. Next, TIPS pentacene solution was deposited onto the patterned contact electrodes via inkjet printing, while the substrate was held at various temperatures, including room temperature, 36 °C, 46 °C, and 56 °C. The resulting thin-film morphology of the inkjet-printed TIPS pentacene film is depicted in Figure 5. When grown at room temperature, crystals accumulated at the droplet contact line due to the coffee ring effect. Increasing the substrate temperature led to faster solvent evaporation, promoting crystals to grow uniformly from the droplet edge towards the center, resulting in more uniform morphology and crystal alignment. However, excessive evaporation at 56 °C led to smaller crystals with higher grain densities. An average hole mobility of 0.09 ± 0.04 cm²/Vs, 0.21 ± 0.05 cm²/Vs, and 0.07 ± 0.03 cm²/Vs was obtained from the inkjet-printed TIPS pentacene thin-film transistor based on substrate temperatures of 36 °C, 46 °C, and 56 °C, respectively. The mobility at 46 °C increased to 0.44 ± 0.09 cm²/Vs based on multi-drop TIPS pentacene devices, which incorporate grain boundaries in the same direction to minimize the impact of charge trapping sites.

3.3. diF-TES-ADT

Among small-molecule semiconductors used in organic electronics, diF-TES-ADT (2,8-difluoro-5,11-bis(triethylsilylethynyl)anthradithiophene) stands out for its exceptional combination of chemical tunability, physical order, and electronic performance [185,186,187]. This fluorinated anthradithiophene derivative exhibits high ambient stability, strong π-π stacking, and a planar molecular structure that promotes dense crystalline packing [188,189,190,191]. Physically, it forms large lamellar domains with a well-aligned edge-on orientation relative to the substrate, enabling efficient in-plane charge transport. The triethylsilylethynyl side groups enhance solubility, while fluorine substitution improves molecular ordering and air stability [192,193,194]. DiF-TES-ADT has demonstrated hole mobilities exceeding 1 cm²/Vs, making it one of the best-performing semiconductors in solution-processed organic field-effect transistors [195]. Despite its promising attributes, diF-TES-ADT films often exhibit polycrystalline morphologies where grain boundaries can impact charge transport. These boundaries act as traps and resistive barriers that interrupt charge percolation, degrade mobility, and introduce variability in device performance. In flexible electronics, they can also serve as mechanical weak points where cracks initiate under strain. Moreover, the distribution, alignment, and quality of these grain interfaces are highly sensitive to processing conditions such as solvent choice, additives, deposition techniques, and substrate treatment. Thus, understanding and controlling grain boundary formation in diF-TES-ADT is essential for optimizing both electrical and mechanical properties of devices. In this section, we review key studies that explore how solvent engineering, polymer blending, substrate templating, and structural mapping have been used to manipulate the crystallization behavior of diF-TES-ADT and reveal the central role grain boundaries play in limiting or enhancing performance.

Kim et al. investigated how grain boundary structure impacts both the electrical characteristics and mechanical durability of flexible OTFTs using diF-TES-ADT as the active semiconductor [94]. By employing chlorobenzene and toluene as processing solvents, they tuned the crystal morphology of the semiconductor films, resulting in distinct differences in grain size and orientation. Films processed with chlorobenzene exhibited smaller, highly aligned grains that initially supported slightly higher hole mobility (0.87 cm²/Vs) but contained a dense network of sharp grain boundaries. These boundaries introduced deep interfacial voids that acted as mechanical weak points, accelerating crack formation during repeated bending and leading to rapid device failure. In contrast, toluene-processed films formed larger, more randomly oriented grains with fewer, broader grain boundaries that provided better mechanical resilience, allowing devices to retain partial function after 10,000 bending cycles despite slightly lower initial mobility (0.84 cm²/Vs). Their results demonstrate that grain boundaries play a dual role of not only limiting charge transport by introducing trap sites and resistance, but also dictating mechanical robustness by serving as crack initiation points under strain. This study highlights the necessity of grain boundary engineering to achieve a balance between high electrical performance and long-term mechanical reliability in flexible organic electronics.

Rubinger et al. examined how the use of solvent additives influences the crystallization behavior and charge transport of diF-TES-ADT-based OTFTs, with a particular focus on how grain boundaries evolve with processing conditions [194]. By introducing varying volumes of the high-boiling-point additive dichlorobenzene (DCB) into chlorobenzene, they controlled the evaporation dynamics during film formation. The optical micrographs in Figure 6 illustrate a clear trend: as DCB content increases from 0% to 8%, the crystalline domains grow progressively larger and more continuous across the transistor channel. In additive-free films, grain boundaries are abundant, and the contrast between domains indicates misaligned molecular orientations. As DCB is added, slower solvent evaporation extends the crystallization window, facilitating improved molecular packing and domain alignment, which is evident from the more uniform optical contrast between adjacent grains. At 8% DCB, the resulting films display large petal-like domains with fewer boundaries and better orientation continuity, leading to an increase in mobility from 0.12 cm²/Vs to 0.34 cm²/Vs. However, at 10% DCB, excessive solvent retention leads to film dewetting and disrupted coverage, which degrades electrical performance. This work demonstrates that modulating crystallization kinetics through solvent engineering is a powerful strategy to minimize grain boundary density and misorientation, thereby enhancing carrier mobility in printed small-molecule semiconductors.

Naden et al. investigated how microstructural evolution in diF-TES-ADT/polymer blend organic transistors affects charge transport, with an emphasis on domain formation and interfacial boundaries [186]. Using scanning probe techniques such as atomic force microscopy (AFM) and Kelvin probe microscopy (KPM), they identified four distinct regimes of semiconductor crystallization, which ranges from large petal-like crystals nucleated on PFBT-treated Ag electrodes to needle-like and disordered crystallites that emerge further into the channel. Transistors with well-aligned, continuous petal-shaped domains exhibited higher electrical performance, including a peak hole mobility of 1.5 cm²/Vs and on/off ratios of 10⁵. In contrast, devices with disrupted domain connectivity, increased grain boundary density, and needle-like crystallites showed lower mobilities (down to 0.08 cm²/Vs), increased hysteresis, and steeper potential drops across grain interfaces. These findings emphasize that grain boundaries, especially those arising from late-stage nucleation and morphological defects, reduce charge transport by acting as resistive bottlenecks. The study offers direct visual and electrical evidence correlating domain continuity with transistor performance and shows the importance of controlling nucleation kinetics and domain alignment to minimize grain boundary-related degradation in organic transistors.

Li et al. performed spatially resolved structural analysis of diF-TES-ADT organic transistors to uncover how domain orientation and microstructural heterogeneity influence charge transport, particularly through grain boundary effects [187]. Using microbeam grazing incidence wide-angle X-ray scattering, they mapped crystallographic textures across devices with channel lengths of 20 μm and 80 μm. Their investigation focused on how processing conditions and substrate treatment impacted the presence and distribution of differently textured crystalline domains and their associated transport bottlenecks. Figure 7 is central to their grain boundary analysis. It presents a side-by-side comparison of microstructural maps from devices of two types: one in which films were grown under standard conditions (type 2), and another processed to enhance crystal continuity (type 1). In type 2 devices, the longer 80 μm channel displayed a spatial transition from the <001> to <111> crystal texture in the channel center. This shift was accompanied by a drop in the intensity of <001> lamellar diffraction, suggesting interrupted grain growth and high-angle misorientation. This break in texture continuity is interpreted as the presence of grain boundaries with disordered interfaces, which are regions likely to impact charge transport due to poor interdomain connectivity. In contrast, the shorter 20 μm type 2 channel retained the <001> texture throughout, indicating that <001>-oriented crystallites successfully bridged the entire span, reducing the likelihood of transport barriers. Type 1 devices, on the other hand, were engineered to promote unbroken <001> crystallization even across the 80 μm channel. These exhibited no detectable <111> textured grains and maintained consistent out-of-plane crystal sizes. Although a sharp increase in angular distribution (FWHM) was observed in the channel center, attributed to grain merging, there was no accompanying strain in the unit cell. Importantly, structural mapping showed that, even when optical and AFM images suggested gaps between domains, the underlying lamellar structure persisted, indicating that traditional imaging may not fully capture the extent of crystalline connectivity relevant to transport. This study directly links specific microstructural transitions, such as texture switching and orientation broadening, to the formation of internal transport barriers, effectively identifying grain boundaries as spatially resolvable limitations to charge mobility. By highlighting that misaligned grain interfaces, rather than just grain size alone, are key contributors to reduced device performance, this study offers a compelling case for using high-resolution structural techniques to optimize grain orientation and connectivity in organic semiconductors.

Salzillo et al. explored how the molecular weight and chemical identity of insulating polymer binders influence the crystallization behavior, morphology, and electronic properties of diF-TES-ADT-based organic field-effect transistors [190]. By blending diF-TES-ADT with PS and PMMA of varying molecular weights and depositing the films using bar-assisted meniscus shearing, they achieved a range of microstructures with distinct implications for charge transport. Devices incorporating low-molecular-weight PS (10K) exhibited the highest hole mobility (1.3 cm²/Vs), while PMMA-based devices showed much lower mobility (0.06 cm²/Vs), pointing to the strong influence of blend morphology on performance. Figure 8 provides detailed polarized optical microscopy and AFM comparisons of the thin-film morphologies. Blends with PS (especially 10K molecular weight) produced large, petal-like crystalline domains with clearly defined grain boundaries, forming relatively smooth films with low surface roughness. These well-developed grains with distinct boundaries are advantageous for lateral charge transport, giving rise to high carrier mobility. In contrast, PMMA-blended films displayed a fine-grained, dendritic microstructure with irregular, poorly connected domains and substantially rougher surfaces (RMS roughness 35 nm). These features indicate a high density of disordered grain boundaries that disrupt charge percolation pathways and contribute to interfacial scattering and trapping. The smaller, more fractured domains in PMMA-based blends also point to weaker interactions between the semiconductor and the insulating matrix, leading to poorer film formation and phase segregation. These findings emphasize the dual role of grain boundaries in organic semiconductors: while clearly defined, low-density grain boundaries in PS-based films can support efficient transport, the disordered and densely packed boundaries in PMMA-based blends act as bottlenecks that severely degrade charge mobility. The study demonstrates that both the lateral grain connectivity and vertical phase homogeneity are critical in defining grain boundary characteristics and, hence, device performance.

3.4. Rubrene

Rubrene (C₄₂H₂₈) is a widely studied organic semiconductor, valued for its high hole mobility, which can exceed 10 cm²/Vs in single crystals [196]. Its orthorhombic polymorph features a herringbone molecular packing that promotes strong π-π orbital overlap, enabling efficient in-plane charge transport [197,198,199]. However, when processed into thin films or polycrystalline forms, rubrene often suffers from reduced mobility due to the formation of grain boundaries as interfaces between misoriented crystalline domains that disrupt molecular packing and create energy barriers for charge carriers. These grain boundaries can act as trap sites or resistive bottlenecks, impacting the coherence of band-like transport and introducing thermally activated hopping behavior. As such, understanding and controlling the structure, density, and alignment of grain boundaries is critical for optimizing the electrical performance of rubrene-based organic electronic devices. This section explores recent efforts to characterize the nature of grain boundaries in rubrene films and their impact on charge transport across different morphologies and structural conditions.

Foggiatto et al. studied the local grain boundary structure in crystalline rubrene platelet and spherulite films by using scanning transmission X-ray microscopy [200]. As a result of different thermal annealing conditions, Figure 9a and Figure 9b show the polarized optical microscope images of the rubrene platelet and rubrene spherulite, respectively. Each domain in the rubrene platelet is a single-crystal orthorhombic grain with abrupt grain boundaries, whereas in rubrene spherulite, it is a continuous gradient of film with variations in in-plane orientations and more disordered and wider grain boundaries. Figure 9c shows a plot of the grain boundary in rubrene platelet and rubrene spherulite films. The grain boundary in both films showed misaligned orientations. The RMS in spherulite film is higher than that in the platelet due to the presence of rays from the nucleation sites, indicating the existence of more grain boundaries. Hole mobility values of 4 cm²/Vs and 1 cm²/Vs were reported from the thin-film transistors based on the rubrene platelet and rubrene spherulite, respectively.

Chapman et al. provided direct evidence of how grain boundaries and dislocations impact charge transport in rubrene organic semiconductors [201]. Using synchrotron-based X-ray topography and high-resolution diffraction, they revealed that even in visually uniform crystals, small-angle grain boundaries and linear dislocations can be present, which is identified as low-energy paths for dislocation formation due to their crystallographic orientation. These defects, which are not readily detectable by conventional polarized light microscopy, contribute to increased mosaicity and are likely responsible for the suboptimal mobilities observed in devices fabricated on these rubrene crystals. The study highlights the critical need for advanced structural characterization techniques in evaluating crystalline quality, emphasizing that improvements in grain boundary control are essential to approaching intrinsic mobility limits in organic molecular semiconductors like rubrene. Mobilities of rubrene were reported ranging from 1 to 13 cm²/Vs, with the variability attributed to microstructural imperfections that disrupt crystal continuity and span the active regions of field-effect transistors.

Kim et al. examined the relationship between crystal thickness, surface morphology, and charge transport in rubrene single crystals, which reveals that surface roughness as dense molecular step edges and macrosteps in thicker crystals can serve as effective charge-trapping sites analogous to grain boundaries [202]. They found that thin crystals (0.5 μm) with atomically smooth surfaces and low step densities achieved high hole mobilities averaging 7.1 cm²/Vs and low surface trap densities (9.6 × 10¹⁰ cm⁻²). In contrast, thick crystals (7 μm) exhibited reduced mobility (6.3 cm²/Vs) and elevated trap densities (5.8 × 10¹¹ cm⁻²), attributed to the disruption of in-plane charge transport by the step edges that force carriers to traverse the less conductive out-of-plane crystallographic direction. These step-induced morphological discontinuities function similarly to grain boundaries by interrupting molecular packing continuity and localizing traps, thus degrading transport even in structurally continuous single crystals. This work shows the importance of treating molecular step edges as quasi-grain boundaries in thick organic crystals and highlights the need for step edge engineering to fully realize the intrinsic transport potential of rubrene.

Euvrard et al. investigated the impact of grain boundaries on charge transport in rubrene thin films with varying degrees of structural order, ranging from amorphous to polycrystalline orthorhombic phases [196]. Figure 10a–c visually illustrates the morphological evolution: (a) shows orthorhombic rubrene platelets, where each grain is a large, single-domain crystallite with minimal internal misalignment; (b) presents orthorhombic spherulites, consisting of polycrystalline grains with varying orientation and high grain boundary density; and (c) displays triclinic spherulitic rubrene, which also contains numerous internal grain boundaries and disordered packing. These morphologies directly influence charge transport, as revealed in Figure 10d, where temperature-dependent conductivity measurements show that orthorhombic platelets exhibit the highest conductivity, while spherulitic and triclinic films suffer from increased disorder and resistivity. A key finding is that the thermally activated transport observed in orthorhombic platelets, despite their ordered crystallites, is attributed to energy barriers at grain boundaries, as schematically depicted in Figure 10e. The presence of these grain boundary-induced barriers limits charge mobility, with the orthorhombic platelet films exhibiting a Hall mobility of 2 cm²/Vs. In contrast, increased grain misalignment and disorder in spherulitic morphologies lead to higher activation energies and reduced mobility. This study highlights that even in ostensibly ordered polycrystalline films, grain boundaries serve as critical bottlenecks to transport, emphasizing the need for grain boundary engineering and optimized molecular packing to achieve high mobility in organic semiconductors.

This section reviews case studies demonstrating how grain boundary engineering strategies have been applied to key small-molecule semiconductors. These studies underscore the important role of processing conditions in controlling grain size, orientation, and trap formation, ultimately showing that mitigating grain boundary effects is essential for improving charge transport and device performance in organic semiconductors. The reviewed articles, along with the authors, type of organic semiconductors, result highlights and mobility, are summarized in

Table 1. Summary of the reviewed works, including the authors, semiconductor, result and mobility.

Author	Semiconductor	Result Summary	Mobility	References
Edura et al.	Pentacene	Charge transport across single grains was nearly ten times higher than across grain boundaries due to lower resistance	5 cm2/Vs	[183]
Schön et al.	Pentacene	Higher substrate temperatures led to larger grains, fewer boundaries, and improved charge mobility	3.2 cm2/Vs	[164]
Minari et al.	Pentacene	Single crystals showed intrinsic polaron hopping, while polycrystalline films were dominated by extrinsic trap-limited transport	2 cm2/Vs	[165]
Weis et al.	Pentacene	Smaller grain sizes increased defect concentration and reduced mobility, impacting sensitivity and performance	4.3 cm2/Vs	[166]
Jin et al.	Pentacene	Larger grains reduced contact resistance and grain boundary trap density, leading to enhanced charge transport	0.359 ± 0.002 cm2/Vs	[167]
He et al.	TIPS pentacene	Blending TIPS pentacene with PαMS, P3HT, and PEO enables tunable control over crystal alignment, grain width, and film uniformity via distinct mechanisms (amorphous confinement, π-π interaction, and crystallization competition, respectively).	0.26 cm2/Vs	[130,181,183]
Sun et al.	TIPS pentacene	Incorporating PBA into TIPS pentacene enhanced crystal alignment and increased grain width by approximately fivefold	0.11 cm2/Vs	[203]
Lee et al.	TIPS pentacene	Inkjet-printed TIPS pentacene films exhibited enhanced crystal alignment and charge mobility by aligning grain boundaries to reduce charge trapping	0.44 cm2/Vs	[184]
Kim et al.	diF-TES-ADT	Chlorobenzene-processed films had higher initial mobility due to smaller, aligned grains but failed quickly under mechanical stress due to sharp grain boundaries.	0.87 cm2/Vs	[94]
Rubinger et al.	diF-TES-ADT	Adding up to 8% dichlorobenzene to chlorobenzene improved crystallization and grain alignment in diF-TES-ADT films, increasing mobility, but excessive additive caused dewetting and performance degradation.	0.34 cm2/Vs	[194]
Naden et al.	diF-TES-ADT	diF-TES-ADT/polymer blend transistors with continuous, well-aligned petal-like domains exhibited higher mobility and lower hysteresis, while disrupted domain connectivity and grain boundaries severely degraded charge transport performance.	1.5 cm2/Vs	[186]
Li et al.	diF-TES-ADT	Misoriented grain boundaries, particularly those arising from crystalline texture transitions, severely limit charge transport, whereas promoting continuous grain alignment minimizes boundary-induced barriers and improves mobility.	Not reported	[187]
Salzillo et al.	diF-TES-ADT	Well-defined, low-density grain boundaries formed in PS-blended films enhance charge transport, while disordered, high-density grain boundaries in PMMA blends disrupt percolation pathways and reduce mobility.	1.3 cm2/Vs	[190]
Foggiatto et al.	Rubrene	Rubrene spherulites show a wider grain boundary structure with higher RMS	4 cm2/Vs	[200]
Chapman et al.	Rubrene	Small-angle grain boundaries and dislocation planes in rubrene single crystals degrade crystalline quality and likely limit charge transport.	13 cm2/Vs	[201]
Kim et al.	Rubrene	Densely packed molecular step edges in thicker crystals act as grain boundary-like defects that disrupt in-plane transport and increase trap density, thereby reducing charge mobility.	7.1 cm2/Vs	[202]
Euvrard et al.	Rubrene	Grain boundaries in polycrystalline rubrene films act as energy barriers that limit charge mobility, particularly in orthorhombic spherulitic morphologies, despite overall crystallinity.	2 cm2/Vs	[196]

. The studies included in Table 1 were selected to represent a broad range of grain boundary engineering strategies applied to high-mobility small-molecule organic semiconductors. These works were chosen based on their experimental clarity, relevance to key themes discussed in this review, and availability of reported mobility values and structural characterization. Together, they provide a comparative overview of how different processing approaches influence film morphology and device performance.

4. Conclusions and Outlook

Grain boundaries are a critical limiting factor in the performance of organic semiconductor devices, particularly in polycrystalline films where they serve as structural and energetic disruptions to charge transport. This review highlights the dual role of grain boundaries, which act as charge trapping sites and electrostatic barriers, that suppress mobility, introduce hysteresis, and compromise both the operational and environmental stability of OTFTs. Across materials systems including pentacene, TIPS pentacene, diF-TES-ADT, and rubrene, it is evident that reducing grain boundary density and misorientation is essential for achieving near-intrinsic transport properties. Strategies such as solvent engineering, polymer additives, and external alignment have been shown to successfully tune crystallization behavior, modulate grain width, and enhance domain connectivity, resulting in substantial mobility gains. The selection of an effective grain boundary regulation strategy is closely tied to the intrinsic structural characteristics of each organic semiconductor. For example, materials with pronounced anisotropic crystal growth, such as TIPS pentacene and diF-TES-ADT, respond well to alignment techniques and polymer additives that facilitate directional crystallization and long-range order. In contrast, semiconductors such as rubrene, which are highly sensitive to processing conditions, could benefit more from solvent engineering to control nucleation density and minimize grain boundary formation. Understanding the molecular packing behavior, crystallization dynamics, and trap susceptibility of a given material is essential for selecting the most suitable engineering approach. In addition, while this review focuses on OTFTs, the grain boundary engineering strategies discussed, such as solvent optimization, polymer blending, and alignment techniques, are broadly applicable to other organic semiconductor devices. In organic photovoltaics, for instance, controlled crystallinity and reduced trap density can enhance charge separation and transport, leading to higher power conversion efficiency. Similarly, in organic light-emitting diodes and sensors, improved molecular ordering can contribute to better charge injection, reduced non-radiative losses, and enhanced operational stability. Therefore, this review offers insights into the design and optimization of a wide range of organic electronic devices.

Despite these advancements, various challenges remain. Future efforts should focus on in situ characterization techniques to dynamically monitor grain boundary formation during film growth, and on developing unified metrics for grain boundary quality beyond width alone, such as misorientation angle, defect density, and boundary chemistry. Moreover, the interplay between grain boundaries and mechanical durability in flexible devices deserves deeper investigation, especially under cyclic strain and real-world conditions. The integration of machine learning with process control could further accelerate the discovery of optimal processing windows for minimizing grain boundaries. Ultimately, the rational design of grain boundary architectures, informed by both empirical data and theoretical modeling, will be key to unlocking the full potential of organic semiconductors in next-generation electronic applications.