Short Circuit Withstand Time Screening of 1.2 kV Commercial SiC MOSFETs: A Non-Destructive Approach ^†

Abstract

SiC MOSFETs are becoming increasingly popular due to their superior material properties, but they lack the required reliability and ruggedness for safe applications. One of the biggest challenges in short-circuit (SC) reliability of the commercial devices and hence in the SC protection circuit design is the variability of SC withstand time (SCWT) among the devices from the same vendor, even with the same lot and batch number. In this work, a novel SC screening methodology has been presented to remove devices with lower SCWT from a pool of devices without damaging the reliable ones. The SC screening methodology has been developed using Sentaurus TCAD simulation, which is further verified using commercial devices. This work can potentially reduce field failure and, as a result, can enhance the reliability of the SiC MOSFETs in real-world applications.

1. Introduction

Silicon carbide metal oxide semiconductor field-effect transistors (SiC MOSFETs) are increasingly favored in high-power and high-temperature applications due to their exceptional material properties like wide bandgap, high thermal conductivity, and large critical breakdown field [1]. To successfully implement SiC MOSFETs in practical applications, such as electric vehicles (EVs), it is essential to meet industry reliability and ruggedness standards ensuring safe operation. Short-circuit (SC) ruggedness is extremely critical for the safety of the EVs as SC event can lead to a catastrophic failure within a few microseconds.

Due to the presence of high interface trap density at SiC/SiO₂ interface, which is almost two orders higher in magnitude compared to Si [2], commercial SiC MOSFETs utilize shorter channel length (~0.5 µm) to trade-off conduction performance [3]. However, the emerging short channel effects, such as drain induced barrier lowering (DIBL) and channel length modulation (CLM), cause higher peak current, leading to more heat generation during SC events [4,5,6]. A combination of higher heat generation and smaller chip area leads to a poorer SC ruggedness. As a result, the SC withstand time (SCWT) of commercial SiC MOSFETs is significantly lower than that of their Si counterparts [7].

After the investigation of SC failure of commercial 1.2 kV SiC MOSFETs by Castellazia et al. [8], numerous efforts have been made to study the SC reliability of SiC MOSFETs. Wang et al. [9] discussed the effect of temperature and drain bias on SCWT and proposed an electrothermal model to estimate the lattice temperature distribution during SC event. The effect of gate and drain bias on SCWT has been extensively explored in the literature, and depending on the voltage level, two unique failure mechanisms, namely gate oxide failure and thermal runaway [10,11,12,13] have been developed. Yao et al. [14] investigated the SC failure of 1.2 kV SiC MOSFETs with planar and trench gate structures in the light of electrical, thermal, and mechanical stress. Under mid-voltage level (~400 V), the failure happens due to the interlayer dielectric cracking, whereas at ~800 V, the device burns out. Current technological advancements have demanded the application of 1.2 kV SiC MOSFETs under a constant drain voltage (V_ds) of 800 V, especially in traction inverters in EVs [15], where the dominant SC failure mechanism is thermal runaway.

Detailed understanding of the SC failure mechanism has further inspired the improvements in device design. Han et al. [16] studied the effect of channel length (L_ch) on SCWT of 1.2 kV planar 4H-SiC MOSFET by varying L_ch from 0.3 µm to 1.1 µm. A sensitivity study by Nayak et al. [17] revealed a strong dependency of JFET width (W_JFET) on SCWT. Yu et al. [18], in a recent work, have demonstrated the impact of device design and fabrication parameters variation in SCWT of a planar MOSFET. The analysis has shown that channel length and gate oxide thickness alteration predominantly affect the SCWT of the device. Even a minor 10% variation in L_ch can alter the SCWT by ~0.5 μs. From the perspective of device fabrication, the probability of channel length variation due to misalignment is considerably higher merely due to the complexity of the processing itself which cannot be controlled beyond a certain degree. Xing et al. [3] conducted a comprehensive investigation on commercial devices and discussed different methods to improve SC reliability from the perspective of both device design and circuit design. The device design methods encompass the implementation of shielded MOSFET [19] and MOSFET with an embedded source resistor [20], whereas circuit solutions involve fast SC detection, BaSIC methodology [21], and RSCS method [22]. The Baliga short-circuit improvement concept (BaSIC) [23] in its simplest form utilizes an additional non-linear element to enhance the SCWT of the device without enduring major impact on on-state and switching performance. A non-linear element with lower on-resistance is connected in series with the source electrode of the power SiC MOSFET, facilitating the damping of the saturation current in a smaller value and therefore the SCWT improves. The PCB-based Rogowski current sensor for short circuit protection (RSCS technique) [22] employs a large bandwidth (>20 MHz) Rogowski coil in conjunction with a signal processing circuit. The combination can identify short circuit failures under a sub-microsecond, markedly surpassing the efficacy of typical DeSat protection circuits. Consequently, total reliability enhances. Furthermore, novel MOSFET designs like planar MOSFET with deep p-well structure [24], MOSFET with retrograded channel doping [25], and Schottky barrier diode (SBD)-embedded MOSFET with smaller cell pitch and JFET width [26] have been reported that can further improve SC reliability and SCWT.

To ensure the safe operation of SiC MOSFETs in applications, it is essential to implement a highly sensitive and rapid SC protection circuit. However, device structure, fabrication techniques, and fast switching speed pose significant challenges due to their impact on reliability. Zhang et al. [27] reviewed that the fast-switching speed of SiC MOSFETs demands enhanced noise suppression that often trades-off the protection circuit response time. Developing a reliable and fast SC protection circuit becomes further complicated due to the variability of the SCWT among commercial devices from the same vendor, even with the same batch and lot number. The initial simulation study has demonstrated that this variability can be correlated to the slight variation in L_ch caused by the misalignment during the fabrication process [17]. Traditional SC measurement methodology is destructive in nature. Therefore, it is necessary to develop a new non-destructive screening method to screen out the devices having lower SCWT from a batch without damaging the reliable ones.

In this work, a novel SC screening method is proposed and demonstrated by utilizing commercially available 1.2 kV SiC MOSFETs with planar-gate structure. The experimental results show that the proposed method can effectively identify and remove devices with low SCWT. Additionally, the key electrical parameters of the devices experiencing the screening process have been extracted and analyzed. The results indicate that the new method barely degrades the reliability of the devices. Hence, it can be implemented in real-world applications.

2. SCWT Variation

2.1. Device Under Test (DUT)

Commercial 1.2 kV SiC MOSFETs with planar-gate structure from Vendor D and Vendor F have been utilized in this study. The device parameters are presented in

Table 1. Datasheet Details of Commercial 1.2 kV SiC Planar MOSFETs.

Vendor	Vendor D	Vendor F
Device type	Planar	Planar
Rated Voltage (kV)	1.2	1.2
Rated Current (A)	20	7.6
Typical Threshold Voltage (V)	3.5	2.5
Typical On Resistance (mΩ)	189	350
Number of Devices Tested	30	23

. Before the SC measurement, each device has undergone typical electrical characterization to obtain threshold voltage (V_th) and on-resistance (R_on) using a Keysight B1506A Power Device Analyzer (Keysight Technologies, Colorado Springs, CO, USA). The V_th of these devices has been extracted by using the linear extrapolation method [28] at V_ds = 100 mV, whereas R_on is calculated at V_gs = 20 V and V_ds = 1.5 V.

2.2. Short Circuit Test Evaluation

A typical short circuit experimental setup [29] is shown in Figure 1. Three 100 µF thick film DC-link capacitors are connected in parallel with the DC source to provide stable DC voltage to the device under test (DUT). A 1 µF decoupling capacitor with low equivalent serial inductance (ESL) and resistance (ESR) is provided to ensure high frequency switching. The turn-on and turn-off times of the DUT are controlled by external gate resistors. To ensure controlled turn-on and turn-off, 10 Ω gate resistors are employed. The drain-to-source transient current (I_ds) is measured using a PEM CWT3 Rogowski coil with a sensitivity of 10 mV/A and a rated peak current of 600 A. Additionally, current limiting resistors of 5 kΩ and bleeding resistors of 66 kΩ are utilized in the setup for enhanced safety. SC measurements have been carried out at V_ds = 800 V and V_gs = 20 V. The turn-on pulse width started from 0.5 µs and slowly increased with a step of 0.1 µs until the device failure is observed. The failure time is defined as the SCWT for that specific device. The consistency of the measurement is carefully controlled by keeping the experimental setup unchanged for all the devices.

2.3. SCWT Variation in Commercial 1.2 kV SiC MOSFETs

Figure 2 shows the SCWT variation in commercial 1.2 kV SiC MOSFETs from Vendor D and Vendor F. For consistency, DUTs have been carefully selected to have the same lot and batch number. The variation in SCWT for Vendor D and Vendor F are 1.0 µs and 0.5 µs, respectively.

The variations in V_th and R_on across the DUTs are shown in Figure 3. DUTs from Vendor D have V_th variation in ~2 V whereas V_th variation in Vendor F is ~0.3 V. R_on variation is ~25-mΩ for both the vendors across the devices. The variation in SCWT as a function of channel length (L_ch) has been initially studied by Han et al. [16]. In this work, a parallel between the L_ch with corresponding specific on-resistance (R_on-sp), SCWT, and the peak current during SC event (I_peak) has been reported. Moreover, I_peak depends on the V_th of the device. As a result, the variation in SCWT as a function of R_on and I_peak is considered, as shown in Figure 4. Although R_on and I_peak impact SCWT, they lack the sensitivity needed to establish a correlation with SCWT of the devices. Hence, it is hard to effectively utilize them for removing devices with low SCWT. Therefore, a novel SC screening method is introduced in this paper.

3. SC Screening Methodology

3.1. Simulation Study of Planar-Gate 1.2 kV SiC MOSFETs

To understand the effect of channel misalignment on SCWT, a simulation study has been performed using Sentaurus TCAD, and the results are discussed below. Figure 5 shows the generic half-cell structure of a 1.2 kV planar-gate SiC MOSFET.

The device has an average L_ch of 0.5 µm with a gate oxide thickness (t_ox) of 50 nm. The misalignment effect has been simulated by considering the L_ch variation from 0.35 µm to 0.7 µm with a step of 0.05 µm. The misalignment is considered to be happening during the dry etching process, where the variation occurs at the N⁺ source side [17]. Therefore, the JFET width (W_JFET) and half the cell width are kept constant at 2 µm and 4.5 µm, respectively, under all conditions. The key parameters related to the MOSFET structure are shown in

Table 2. Details of Simulated 1.2 kV SiC Planar MOSFETs.

Parameter	Value	Unit
Tdrift	10	µm
NN−drift	8 × 1015	cm−3
NP+	1 × 1019	cm−3
NP-well	1 × 1018	cm−3
NN+	1 × 1019	cm−3
Nchannel	2 × 1017	cm−3
NJFET	1 × 1016	cm−3
NN+substrate	2 × 1018	cm−3
Lch (avg.)	0.5	µm
½ WJFET	1.0	µm
tox	50	nm
½ Wcell	4.5	µm

.

For a reliable short circuit transient electrochemical simulation, thermodynamic models have been considered along with a traditional drift-diffusion model. Fermi statistics, Auger recombination, and the band gap narrowing model have been introduced from the literature. Moreover, to establish non-isothermal simulation, thermal parameters related to thermal conductivity and specific heat capacity have been calibrated using the literature and experimental result [3,17]. Some of the typical models and related parameters [30] are shown in

Table 3. Typical Simulation Parameters.

Model	Parameter	Value	Unit
Lattice Heat Capacity	cv	10	J/(K-cm3)
	cv_b	1.75 × 10−3	J/(K2-cm3)
	cv_c	1 × 10−9	J/(K3-cm3)
	cv_d	−6.6 × 10−4	J/(K3-cm3)
Thermal Conductivity	1/kappa	1	K-cm/W
	1/kappa_b	4.9662 × 10−4	cm/W
	1/kappa_c	0.35 × 10−6	cm/(W-K)

.

A typical SC characteristic as a function of transient time under V_ds = 800 V and V_gs = 20 V is shown in Figure 6a. The red curve shows the drain current density (J_ds) in A/cm², under the described condition. Figure 6b represents the variations in drain current density and junction temperature as functions of transient time. The red curve displays J_ds in A/cm² and the blue curve represents the lattice temperature in K. Initially (t₁~t₂), J_ds increases due to the improvement of the inversion channel mobility with temperature and achieves a maximum value of J_ds-peak. Beyond that (t₂~t₃), J_ds reduces as phonon scattering becomes predominant, resulting in a net reduction in carrier mobility [3,31]. When the device is turned off (t₃~), the off-state drain leakage current due to thermally generated carriers remains [9,12] in the device, which eventually leads to the failure of the device. The variations in simulated SCWT and J_ds-peak as functions of L_ch are shown in Figure 7. Under the same applied gate pulse, the device with a higher J_ds-peak induces higher temperature. Higher temperature results in more drain leakage current, hence lower SCWT is achieved.

The effect of lattice heating and temperature-dependent mobility during the SC period can be extracted by utilizing the J_ds versus transient time characteristics under the SC condition. Figure 8 shows the SC characteristics of two simulated devices with L_ch = 0.35 µm (SD₁) and 0.7 µm (SD₂) having SCWT of 1.7 µs and 6.4 µs, respectively. It can be clearly seen that SD₂ has lower J_ds-peak and higher SCWT compared to SD₁. The degradation of simulated drain current after J_ds-peak, which is the drain current slope (slope: A/cm²-s), can be mathematically expressed as

$$slope={\displaystyle \frac{(J_{ds-peak}-J_{ds-min})}{∆t}},$$

(1)

where J_ds-min and Δt are the pre thermal runaway current density and the time required to reach from J_ds-peak to J_ds-min, respectively. The overall effect of the increased lattice temperature and the non-negligible drain leakage current during the SC event can be expressed as a ratio of J_ds-peak to the slope and termed as the SCWT correlation parameter P_TDM. It can be mathematically represented as

$$P_{TDM}={\displaystyle \frac{J_{ds-peak}}{slope}}.$$

(2)

At a device level, for the activation of thermal runaway failure process, the device needs to reach a critical junction temperature (T_j,cri) [32]. As SC is a dynamic process, the junction temperature (T_j) is affected by the drain current density (J_ds) and time. Hence, the term P_TDM can be considered as an electrical probe that captures the net variation in T_j and can be correlated to the failure time of the device. Figure 9 shows the variations in slope and P_TDM as functions of SCWT and L_ch. The result illustrates that P_TDM and SCWT have strong correlation as L_ch varies, indicating the possibility to reliably use P_TDM as the screening parameter to remove devices with weak SCWT due to the channel misalignment in commercial SiC MOSFETs.

3.2. Proposed SC Screening Method

Based on the simulation analysis, a novel non-destructive SC screening methodology for 1.2 kV commercial SiC MOSFETs is proposed and graphically presented in Figure 10. For a successful SC screening, the key component is to establish the optimized screening parameter P_TDM using a small batch from a pool of devices having the same lot and batch number. The vital steps of P_TDM optimization are determining the test pulse width at which the screening can reliably perform (t_screen) and setting the minimum SCWT to screen out poor devices. Furthermore, the usability of the screened devices needs to be confirmed by comparing different electrical parameters pre- and post-screening. Upon establishing the P_TDM range needed for the reliable devices, a single pulse of t_screen can be used to remove devices that have less SCWT than the pre-determined minimum value, without damaging the reliable ones from the same pool. This section discusses the technique to optimize the P_TDM for a minimum SCWT of 1.9 µs in 1.2 kV SiC MOSFETs from Vendor D and Vendor F.

3.2.1. Determining Screening Pulse Width

To efficiently screen out devices with lower SCWT, the screening pulse width (t_screen) needs to be optimized. The beginning of the thermal runaway can be detected by the existence of tail current and change in current slope caused by the thermally generated carriers due to the presence of high voltage and temperature [13]. To successfully screen out devices with low SCWT, t_screen should be able to capture this phenomenon without destroying the devices. As a result, in our work, t_screen has been set to (t_scmin − 0.2 µs), where t_scmin represents the minimum SCWT from the same batch of devices. The t_screen is calculated to be 1.5 µs and 1.6 µs for Vendor D and Vendor F, respectively.

3.2.2. Determining Screening Parameter and SCWT Correlation

For the next step, each DUT has undergone a traditional SC measurement under V_ds = 800 V and V_gs = 20 V. An initial gate pulse of t_screen is applied, which is then incremented by a step of 0.1 µs until failure is observed. The behavior of the commercial devices under screening pulse can be explained by considering two devices from Vendor D with a SCWT of 1.7 µs (D₁) and 2.7 µs (D₂), as shown in Figure 11.

Figure 12 represents the behavior of D₁ and D₂ when subjected to t_screen = 1.5 µs. It can be clearly seen that, under the same experimental conditions, devices with different SCWT show variations in peak current (I_peak), peak current position in the time scale (t_peak), and current slope beyond I_peak. Using the theory developed by the simulation study, P_TDM under t_screen can be defined as

$$P_{TDM}={\displaystyle \frac{I_{peak}}{slope}},$$

(3)

$$\mathrm{where}slope={\displaystyle \frac{(I_{peak}-I_{min})}{∆t}}\mathrm{and}\Delta t=t_{screen}-t_{peak}.$$

(4)

Here, I_min and Δt are the pre-turn-off current and the time required to reach from I_peak to I_min, respectively. It can be clearly seen that, under a constant t_screen, the value of Δt and hence slope depends on the t_peak. The variation in Δt for D₁ and D₂ having different t_peak is also presented in Figure 12 as Δt_D1 and Δt_D2, respectively.

Figure 13a displays the SCWT as a function of P_TDM (s) for Vendor D while applying t_screen = 1.5 µs. It is apparent that, to successfully identify devices with SCWT greater than or equal to 1.9 µs, the range of P_TDM should be less than 1.8 s, as shown by the arrow. Similar analysis has been carried out for Vendor F while applying t_screen = 1.6 µs, as shown in Figure 13b. To successfully find out devices with SCWT greater than or equal to 1.9 µs for Vendor F, the range of P_TDM should be greater than 2.4 s.

It is evident that the range of P_TDM is different for different vendors. The variation in P_TDM is affected by device design parameters such as die area, die volume, channel design, active area design, gate oxide thickness and quality, interface defect state density, doping profile, device fabrication process, and temperature diffusion process, etc., [33,34,35]. As a result, P_TDM needs to be experimentally determined by each vendor.

3.2.3. Effect of Screening Process

The effect of screening pulse (t_screen) on device characteristics has been examined by measuring and comparing V_th, R_on, gate leakage current (I_gss), and drain to source leakage current (I_dss) of a small batch of devices from each vendor before and after applying the t_screen. The variation in I_dss due to screening is presented in Figure 14. The variations in all the other static parameters have been condensed in

Table 4. Comparison of Static Parameters Before and After the Screening Process for Vendor D and Vendor F.

Vendor	Threshold Voltage (V)		On-Resistance (mΩ)		Gate Leakage Current (nA)
	Pretest	Post- Screening	Pretest	Post- Screening	Pretest	Post- Screening
D	7.2	7.2	116.25	116.25	0.081	0.051
F	6.11	6.12	318.2	321.1	27.5	27.1

. All results are representative in nature.

Furthermore, the generation of any additional interface defect states due to the screening has been studied by calculating the energy-dependent interface trap density ($D_{\mathrm{i}\mathrm{t}}\left({\phi }_{\mathrm{s}}\right)$) near the SiC/SiO₂ interface on the same set of devices. The $D_{\mathrm{i}\mathrm{t}}$ profiles have been obtained by using the subthreshold region in transfer characteristics [36] at room temperature. The mathematical analysis to calculate $D_{\mathrm{i}\mathrm{t}}\left({\phi }_{\mathrm{s}}\right)$ is described below.

The subthreshold region drain current,

$$I_{ds}=I_0{e}^{{\displaystyle \frac{q{V}_{gs}}{nkT}}}\left(1-e^{{\displaystyle \frac{q{V}_{ds}}{kT}}}\right),$$

(5)

and the ideality factor n are given as

$$n={\displaystyle \frac{q}{2.3kT}}{\left({\displaystyle \frac{\partial log{I}_{DS}}{\partial V_{gs}}}\right)}^{-1}=1+{\displaystyle \frac{C_D+C_{it}}{C_{ox}}},$$

(6)

where $C_{\mathrm{D}}$ is depletion capacitance, $C_{\mathrm{o}\mathrm{x}}$ is oxide capacitance, and $C_{\mathrm{i}\mathrm{t}}$ is the interface trap capacitance per unit area.

The energy-dependent interface trap density is given as

$$D_{it}\left({\phi }_s\right)={\displaystyle \frac{C_{it}}{q}},$$

(7)

and the energy distribution of the trap level ${(E}_{\mathrm{c}\mathrm{s}}-E_{\mathrm{T}})$ is

$$E_{cs}-E_T={\displaystyle \frac{E_g}{2}}-q\left({\phi }_F-{\displaystyle \frac{2.3kT}{q}}\log \left[{\displaystyle \frac{I_{DS}\left(2{\phi }_F\right)}{I_{DS}\left({\phi }_s\right)}}\right]\right),$$

(8)

where surface potential (${\phi }_{\mathrm{s}}$) is in the range of ${\phi }_{\mathrm{F}}$ < ${\phi }_{\mathrm{s}}$ < ${2\phi }_{\mathrm{F}}$ and ${\phi }_{\mathrm{F}}$ is the Fermi potential.

Using (7) and (8), $D_{\mathrm{i}\mathrm{t}}\left({\phi }_{\mathrm{s}}\right)$ for sample devices from Vendor D and Vendor F have been extracted before and after applying t_screen, and the representative results are shown in Figure 15. Comparison of different static parameters before and after applying the screening pulse along with the extracted room temperature $D_{\mathrm{i}\mathrm{t}}$ profile close to the conduction band edge ${(E_{\mathrm{c}\mathrm{s}}-E}_{\mathrm{T}}$~0.1 eV) indicates that no significant degradation happened due to the screening process and the devices can be further utilized in applications safely.

4. Conclusions

This work has successfully demonstrated a novel non-destructive short-circuit (SC) screening methodology for 1.2 kV SiC power MOSFETs to screen out devices with low SC withstand time (SCWT) without damaging the reliable ones. A new screening parameter P_TDM has been introduced that captures the SCWT variation during the SC event and shows a strong correlation with SCWT. This theoretically established correlation has been further verified experimentally using state-of-the-art 1.2 kV SiC MOSFETs with a planar-gate structure from commercial vendors. It has been determined that, for each vendor, the screening parameter P_TDM needs to be recalibrated for successful screening. Furthermore, the effect of SC screening on the devices’ static characteristics has been studied. The results indicate that the proposed screening method does not degrade or damage the devices under test. Successful implementation of this method at a commercial level will be able to remove the unwanted devices having low SCWT without damaging the reliable ones; hence, it can notably improve the safety and consistency of commercial SiC MOSFETs in real-world applications.