A Reflection-Based Ultra-Fast Measurement Method for the Continuous Characterization of Self-Heating for Advanced MOSFETs

Abstract

As semiconductor devices approach the sub-10 nm technology node, the self-heating effect (SHE) induced by confined geometries (e.g., FinFETs and nanosheet FETs) has emerged as a critical bottleneck affecting both performance and reliability. This challenge has prompted extensive research efforts to develop advanced characterization methodologies to investigate this effect and its corresponding influence on the device’s reliability issues. In this paper, we propose reflection-based ultra-fast measurement techniques for the continuous monitoring of the self-heating effect in advanced MOSFETs. With this approach, the self-heating effect-induced degradation of transistor drain current and the real-time temperature change can be continuously captured using a digital phosphor oscilloscope on a nanosecond scale. The thermal time constant of 17 ns and the thermal resistance of 34,000 K/W have been extracted for the short channel transistors used in this study with the help of this new characterization method. This reflection-based method is useful for the fast extraction of the thermal time constant and thermal resistance and for the continuous monitoring of current degradation as well as the real-time temperature. Therefore, this new characterization method is beneficial for the evaluation of the self-heating effect in advanced ultra-scaled MOSFETs.

1. Introduction

The self-heating effect (SHE) has been studied for more than 40 years [1,2,3]. At a macroscopic level, the drain current flow through a channel will generate heat and cause a local temperature rise. At the microscopic level, hot carriers undergo a scattering process in which they exchange energy with phonons, resulting in a local temperature rise [4]. Advanced CMOS technologies, such as Fully Depleted Silicon-On-Insulator (FDSOI), Fin Field-Effect Transistors (FinFETs), and Gate-All-Around Field-Effect Transistors (GAA-FETs), suffer from severe self-heating problems due to their ultra-scaled device dimensions, high power consumption, and poor heat dissipation [5,6,7,8,9]. The rise in device channel temperature is given by $T_{\mathrm{r}\mathrm{i}\mathrm{s}\mathrm{e}}=P_{\mathrm{D}}·R_{\mathrm{t}\mathrm{h}}=\left(I_{\mathrm{D}}·V_{\mathrm{D}}\right)\cdot R_{\mathrm{t}\mathrm{h}}$, where $R_{\mathrm{t}\mathrm{h}}$ is the thermal resistance [10,11].

Hot Carrier Injection (HCI) and Bias Temperature Instability (BTI) are temperature-sensitive reliability issues in advanced nodes [12,13,14]. The SHE will degrade the saturation current and hence overestimate HCI degradation without temperature correction [15]. The SHE-induced high device temperature will exacerbate BTI’s contribution to the measured HCI degradation [6,16] and accelerate BTI recovery [17]. As the SHE is critical for the accurate characterization of transistor performance and reliability as well as circuit simulations [18], plenty of studies have been conducted to systematically study the SHE, including analytical and electrical methods. The thermal elements of analytical methods, such as Picosecond Imaging Circuit Analysis (PICA) [19], Scanning Thermal Microscopy [20], and Micro-Raman Spectroscopy [21], are associated with the luminescence or phonon process. In contrast, the thermal elements of electrical methods, such as the gate resistance method [22], pulsed I-V method [23], and AC conductance method [24,25], are associated with transistor basic electrical parameters. Each method has its own advantages and disadvantages depending on the characterization requirements and test setup.

Analytical methods have the characteristics of fast measurement speed and high time resolution in capturing self-heating phenomena. However, they usually require converting the change in optical signals to electrical parameters, which is challenging and non-straightforward, to realize accurate self-heating characterization. Electrical techniques have the advantage of directly characterizing the influence of the SHE on electrical parameters. However, the gate resistance method needs a good layout design. The conventional pulsed I-V method generally may not be sufficient to investigate the device with a thermal time constant ${\tau }_{\mathrm{t}\mathrm{h}}<100$ ns. And the AC conductance method needs to convert the frequency domain result to the time domain.

In this paper, we propose a reflection-based ultra-fast characterization method for continuously monitoring the self-heating-induced degradation of transistor drain current. This method is compatible with basic transistor radio frequency (RF) measurements with the benefit of high temporal resolution. In this method, the high-frequency signal reflection is utilized instead of elimination, which is a common handling approach in RF tests.

Compared with traditional I-V measurement methods, the proposed reflection-based methodology enables dynamic real-time monitoring of the drain current degradation caused by the self-heating effect at the nanosecond scale. Additionally, accurate extraction of the thermal time constant can be efficiently performed. The overall measurement setup is structurally simple and seamlessly integrable with standard radio frequency (RF) test platforms, indicating strong potential for scalable and extended applications in advanced device characterization.

2. Experimental Setup

A reflection-based ultra-fast measurement methodology has been proposed for transistors’ I-V measurement on the nanosecond scale, which shows its significant potential in heat-free measurements. Note that in this study, heat-free means local self-heating has minimal impacts on the basic electric performance and reliability behavior since it takes several nanoseconds for local self-heating to increase the average channel temperature [5]. Figure 1a shows the adopted measurement setup. In order to achieve ultra-fast measurement, the generation of applied voltage pulses with a steep rise edge (small t_r) and the instant capture of the corresponding output during the rise edge are essential. In this work, a small t_r value of 200 ps is adopted. A high bandwidth arbitrary waveform generator (AWG) with multiple channels is used to supply voltage pulses to both gate and drain terminals through two separate channels, V_CH1 and V_CH2. The pick-off tee used here eliminates unnecessary reflection and acts as a power divider. A high bandwidth digital phosphor oscilloscope (DPO) is used to capture both incident and reflection signals. An RF probe with a 50 Ω impedance match is used in the gate pad, whereas a normal RF probe without an impedance match is used in the drain pad, as schematically shown in Figure 1b. To perform wafer-level RF measurements, short channel transistors used in this study are designed as a ground–signal–ground (GSG) layout, as shown in Figure 1c.

The pulse rise time is set to 200 ps to ensure that waveform acquisition occurs well within the initial nanoseconds of the device’s operation, before significant self-heating effects take place. The 1 m transmission line introduces a ~10 ns delay, enabling clear separation between incident and reflected waveforms. All components in the signal path are impedance-matched to 50 Ω to minimize undesired reflections and maintain signal integrity. These configurations support the underlying assumption that the Device Under Test (DUT) remains in a near-isothermal state during the early measurement window.

3. Reflection-Based Characterization Methodology

3.1. Reflection in the System

In this configuration, the signal of the gate side has no reflection from the AWG to the gate pad, ensuring its signal integrity. As for the drain side, there is a natural reflection due to the discontinuous resistance at the device drain terminal. This impedance mismatch inevitably leads to a signal reflection, which is mainly utilized to perform the measurements. All the three resistances, namely R₁, R₂, and R₃, have a value of 16.7 Ω.

According to the transmission line theory, an electromagnetic wave will reflect at any point where the impedance is not matched. The reflection coefficient Γ is generally defined as $\Gamma =(Z_{out}-Z_{in})/\left(Z_{\mathrm{o}\mathrm{u}\mathrm{t}}+Z_{\mathrm{i}\mathrm{n}}\right)=V_{\mathrm{r}\mathrm{e}\mathrm{f}\mathrm{l}\mathrm{e}\mathrm{c}\mathrm{t}\mathrm{i}\mathrm{o}\mathrm{n}}/V_{\mathrm{i}\mathrm{n}\mathrm{c}\mathrm{i}\mathrm{d}\mathrm{e}\mathrm{n}\mathrm{t}}$. Figure 2 shows a waveform reflection sequence diagram. The input waveform named $V_{\mathrm{i}\mathrm{n}\mathrm{p}\mathrm{u}\mathrm{t}}$ will first be reflected at the ${\Gamma }_1$ point and then go through the pick-off tee. It is divided into two identical parts called $V_{inci}$. One of the incident waveforms arrives at the DPO through $R_3$, and the other will be reflected at the device’s ${\Gamma }_3$ point. The reflected waveform called $V_{\mathrm{r}\mathrm{e}\mathrm{f}\mathrm{l}}$ will arrive at the DPO with a time delay of $2\Delta t$, where $\Delta t$ is the time needed for the signal to pass through the one-meter-long transmission line once. In this configuration, V_inci represents the signal reaching the drain side of the DUT, while V_refl is the waveform reflected due to the impedance mismatch at the device terminal, and both are measured at the DPO through the pick-off tee. The incident and reflection waveforms will be superimposed together, which obeys the principle of vector superposition. The superimposed incident and reflection waveforms were separated according to the calibration procedure described in the calibration section. These waveforms are then used to calculate the device-side reflection coefficient ${\Gamma }_3$, which captures the impedance mismatch at the DUT terminal. According to the transmission line theory, the incident and reflected components satisfy $V_{\mathrm{i}\mathrm{n}\mathrm{c}\mathrm{i}}=V_{\mathrm{i}\mathrm{n}}(1+\Gamma )$ and $V_{\mathrm{r}\mathrm{e}\mathrm{f}\mathrm{l}}=V_{\mathrm{i}\mathrm{n}}·\Gamma$. Based on this, the channel resistance $R_{\mathrm{C}}$, drain voltage $V_{\mathrm{D}}$, and drain current $I_D$ are computed using the expressions shown in Figure 3. Each equation in Figure 3 corresponds to a specific step in the drain current extraction process. Specifically, Equation (1) computes the incident voltage V_inci arriving at the drain terminal of the DUT based on the input waveform and the reflection coefficient ${\Gamma }_1$ at the first impedance discontinuity. Equation (2) calculates the reflected voltage V_refl, which is influenced by multiple stages of impedance mismatch and contains information about the DUT’s internal channel resistance through the reflection coefficient Γ₃. Equation (3) determines the drain voltage V_D, derived from the superposition of the incident and reflected signals, expressed as $V_D=V_{inci} · (1+{\Gamma }_3)$. Equation (4) then applies Ohm’s law to obtain the drain current I_D using the relationship $I_{\mathrm{D}}=V_{\mathrm{D}}/R_{\mathrm{C}}$, where R_C is the extracted channel resistance. Finally, Equations (5)–(9) define the reflection coefficients Γ₁, Γ₂, and Γ₃ and the equivalent parallel resistances R_P1 and R_P2, which are essential for modeling the signal path and enabling accurate computation. This complete formulation provides a transparent and physically grounded approach for extracting real-time current characteristics from high-speed waveform measurements.

The formulas used to compute the drain current I_D are as follows:

$$V_{\mathrm{inci}}={ V}_{\mathrm{input}}(1+{\Gamma }_1){\displaystyle \frac{R_{\mathrm{P}1}}{R_1+R_{\mathrm{P}1}}}{\displaystyle \frac{Z_0}{Z_0+R_3}}$$

(1)

$$V_{\mathrm{refl}}={ V}_{\mathrm{input}}(1+{\Gamma }_1){\displaystyle \frac{R_{\mathrm{P}1}}{R_1+R_{\mathrm{P}1}}}{\displaystyle \frac{Z_0}{Z_0+R_2}}{\Gamma }_3(1+{\Gamma }_2){\displaystyle \frac{R_{\mathrm{P}2}}{R_2+R_{\mathrm{P}2}}}{\displaystyle \frac{Z_0}{Z_0+R_3}}$$

(2)

$$V_{\mathrm{D}}={ V}_{\mathrm{input}}\left(1+{\Gamma }_1\right){\displaystyle \frac{R_{\mathrm{P}1}}{R_1+R_{\mathrm{P}1}}}{\displaystyle \frac{Z_0}{Z_0+R_2}}(1+{\Gamma }_3)$$

(3)

$$I_{\mathrm{D}}={\displaystyle \frac{V_{\mathrm{D}}}{R_{\mathrm{C}}}}$$

(4)

$${\Gamma }_{1 }={\displaystyle \frac{R_1+R_{\mathrm{P}1}-Z_0}{R_1+R_{\mathrm{P}1}+Z_0}}$$

(5)

$${\Gamma }_{2 }={\displaystyle \frac{R_2+R_{\mathrm{P}2}-Z_0}{R_2+R_{\mathrm{P}2}+Z_0}}$$

(6)

$${\Gamma }_3={\displaystyle \frac{R_{\mathrm{C}}-Z_0}{R_{\mathrm{C}}+Z_0}}$$

(7)

$$R_{\mathrm{P}1}=1/({\displaystyle \frac{1}{R_3+Z_0}}+{\displaystyle \frac{1}{R_2+Z_0}})$$

(8)

$$R_{\mathrm{P}2}=1/({\displaystyle \frac{1}{R_1+Z_0}}+{\displaystyle \frac{1}{R_2+Z_0}})$$

(9)

Parameter Definitions:

In Equations (1)–(9), the following symbols are used:

• V_inci: The incident voltage reaching the drain side of the DUT (unit: V).
• V_refl: The reflected voltage due to impedance mismatch at the DUT (unit: V).
• Γ₁, Γ₂, Γ₃: The reflection coefficients at different impedance discontinuities, with dimensionless ratios defined as $\Gamma =(Z-Z_0)/\left(Z+Z_0\right)$, where Z is the local impedance and Z₀ = 50 Ω is the characteristic impedance.
• R_C: The channel resistance of the DUT, extracted from the waveform superposition (unit: Ω).
• V_D: The instantaneous drain voltage at the device terminal (unit: V).
• I_D: The drain current calculated using Ohm’s law (unit: A).
• R₁, R₂, R₃: The resistors in the pick-off tee, each 16.7 Ω.
• R_P1, R_P2: Parallel equivalent resistances of the resistive divider branches (unit: Ω).
• Z₀: The characteristic impedance of the transmission line, fixed to 50 Ω.

3.2. The Calibration of the Measurement System

The waveforms generated by the AWG are shown in Figure 3a, labeled as V_CH1 and V_CH2, respectively. V_CH2 is generated by the AWG CH1 channel and applied to the device gate terminal directly, whereas V_CH2 is generated by the AWG CH2 channel and applied to the device drain terminal through a pick-off tee, as shown in Figure 2. Figure 3b shows the real waveform used in our test. The waveform was carefully tuned to ensure the voltage variation remained within 2 mV across a total swing of 850 mV (less than 0.24%), ensuring sufficient stability for reflection-based measurement.

A standard 50 Ω resistor and floating transmission line replace the device under test to calibrate the divider losses and cable losses, as shown in the upper right in Figure 2. The superimposed incident and reflection waveforms were extracted from the DPO readout data based on the reference waveforms. V_50Ω data is used as the incident waveform, and ($V_{\mathrm{device}\mathrm{o}\mathrm{n}}-V_{50\mathrm{\Omega }}$) data is used as the reflection waveform. The separated incident and reflection waveforms are shown in Figure 3c.

4. Results and Discussion

The proposed methodology is demonstrated to characterize the self-heating effect of commercial-ready scaled transistors. Figure 4 shows the drain current degradation versus the time at different chuck temperatures, ranging from 223 K to 373 K. The drain current I_D decreases rapidly at the first 50 ns once the device is on, which can be mainly attributed to the local self-heating and elevated device temperature. The 63.2% current degradation is used as a criterion to extract the thermal time constant ${\tau }_{\mathrm{t}\mathrm{h}}$, corresponding to the classic solution of a first-order thermal RC network under a step power input, where the thermal time constant τ_th is defined as the time required for the temperature to rise to 63.2% of its final steady-state value. And the ${\tau }_{\mathrm{t}\mathrm{h}}$ value of the devices in Figure 4 is about 17 ns.

The drain current at time zero, shown as circles in Figure 4, was used as the heat-free current at different chuck temperatures. By changing the chuck temperature, a cluster of I_D traces was obtained. And the heat-free current can be extracted for different chuck temperatures. Therefore, the heat-free current versus the chuck temperature can be derived, as shown in Figure 5a. This relationship can be modeled as a linear relationship of the heat-free drain current to chuck temperature as $I_{\mathrm{h}\mathrm{e}\mathrm{a}\mathrm{t}\text{-}\mathrm{f}\mathrm{r}\mathrm{e}\mathrm{e}}=\alpha T_{\mathrm{c}\mathrm{h}\mathrm{u}\mathrm{c}\mathrm{k}}+\beta$ mathematically. And the real-time temperature of the device is evaluated by $T_{\mathrm{d}\mathrm{e}\mathrm{v}\mathrm{i}\mathrm{c}\mathrm{e}}\left(t\right)=\left(I_{\mathrm{r}\mathrm{e}\mathrm{a}\mathrm{l}\mathrm{t}\mathrm{i}\mathrm{m}\mathrm{e}}\left(t\right)-\beta \right)/\alpha$ with the fitting parameters $\alpha =-0.0027$ mA/K and $\beta =3.6$ mA. Specifically, $\alpha$ and $\beta$ are obtained by performing linear regression between the heat-free drain current (extracted at $t=0$) and the chuck temperature, as shown in Figure 5a. The linear fitting yields $\alpha = -0.0027$ mA/K and $\beta =3.6$ mA, with a high $R^2$ value indicating good agreement. These parameters are treated as constants over the tested temperature range (223 K to 373 K) due to the strong linearity observed.

The steady temperature versus chuck temperature is shown in Figure 5b. Here, the steady temperatures are extracted from the temperature at 100 ns, where thermal generation and dissipation come to an equilibrium state. The device channel temperature change at different levels of device power dissipation is shown in Figure 5c. Red dots were acquired by changing the chuck temperature at constant V_G and V_D values. Blue squares were acquired at the same 273 k value but with different V_D values for various powers.

To characterize the thermal resistance $R_{\mathrm{t}\mathrm{h}}$, we first calculated the real-time temperature using the extracted α and β values and then fit the temperature rise ($\Delta T=T_{\mathrm{d}\mathrm{e}\mathrm{v}\mathrm{i}\mathrm{c}\mathrm{e}}-T_{\mathrm{c}\mathrm{h}\mathrm{u}\mathrm{c}\mathrm{k}}$ [K]) against power dissipation ($P_{\mathrm{D}}\left[W\right]=I_{\mathrm{D}}\left[\mathrm{A}\right]·V_{\mathrm{D}}\left[V\right]$) based on the relation $\Delta T\left[\mathrm{K}\right]=R_{\mathrm{t}\mathrm{h}}[\mathrm{K}/\mathrm{W}]·P_{\mathrm{D}}\left[\mathrm{W}\right]$, where ΔT is the increasing temperature and $P_D$ is power dissipation. The thermal resistance extracted from the experiment data is about $3.4\times {10}^4$ K/W, which is reliable compared with previous results of ultra-scaled MOSFETs [9,15]. The steady-state current degradation in this study is primarily ascribed to self-heating, while other slow degradation mechanisms are considered negligible due to the short test duration and fixed bias conditions. To improve measurement reliability, the setup was optimized based on a previously validated reflection-based nanosecond-scale method, with key error sources being systematically addressed. All signal paths were impedance-matched to 50 Ω, except for the drain side, where intentional mismatch enabled the extraction of reflection signals. Calibration using two terminations (50 Ω load and floating) confirmed the accuracy of the reflection coefficient model. The architecture further distinguishes the primary reflection point (${\Gamma }_3$) from parasitic ones (${\Gamma }_1, {\Gamma }_2$), which are effectively suppressed via the pick-off tee.

Previous comparative studies [26] showed that this method yields a slightly higher drain current (~14%) than commercial systems such as the B1500 due to reduced thermal stress under nanosecond pulses. With impedance control, timing synchronization, and waveform averaging, measurement uncertainty is minimized, ensuring accurate thermal parameter extraction.

Compared with the conventional SHE characterization method, the proposed reflection-based ultra-fast technique exhibits notable advantages in both temporal resolution and experimental simplicity. Analytical techniques such as Micro-Raman Spectroscopy and PICA offer high spatial and temporal resolution but rely on indirect optical-to-electrical conversions, which often require complex calibration and are difficult to integrate into standard test platforms. Moreover, as device dimensions continue to be scaled into the deep sub-10 nm regime, optical-based methods such as Micro-Raman and PICA face intrinsic limitations due to the laser spot size and heat diffusion effects, which constrain their spatial resolution and localization accuracy. Under such extreme nanoscale conditions, the reflection-based electrical method proposed in this study operates independently of optical alignment and the laser spot size, offering strong dimensional scalability. As a result, it is particularly well-suited for dynamic thermal characterization in ultra-scaled transistor structures. Electrical techniques, including the gate resistance method, pulsed I-V measurements, and AC conductance methods, are more directly tied to transistor electrical behavior but suffer from critical limitations. For instance, conventional pulsed I-V methods typically lack the time resolution necessary to resolve sub-100 ns thermal transients, and AC conductance measurements require complex post-processing to convert frequency-domain data into time-domain thermal responses [27]. In contrast, our method enables the direct, real-time monitoring of drain current degradation due to self-heating by utilizing high-frequency signal reflections—a phenomenon usually suppressed in RF measurements. This not only circumvents the complexity of optical calibration and frequency-domain transformations but also allows for seamless integration with existing RF measurement setups. The demonstrated ability to extract thermal time constants as short as 17 ns highlights the method’s suitability for emerging nanoscale transistor technologies, making it a promising tool for fast, accurate, and scalable self-heating characterization.

The measurement setup is structurally simple and compatible with standard RF test platforms, making it highly integrable and scalable. These features highlight the method’s potential as a reliable and efficient tool for next-generation transistor thermal reliability assessment and circuit-level modeling.

Benefiting from its nanosecond-scale temporal resolution and sensitivity to transient signal behavior, the method demonstrates strong potential in both RF and High-Performance Computing (HPC) domains. In RF systems, it can be used for a rapid analysis of signal reflections and impedance discontinuities. In HPC platforms, it may assist in evaluating signal integrity issues in high-speed interconnects and memory interfaces, thereby contributing to improved system stability and reliability.

This work provides not only a novel perspective for self-heating evaluation but also a practical foundation for future research and industrial implementation in nanoscale device diagnostics [28].

5. Conclusions

This paper presents a reflection-based, ultra-fast method for the non-intrusive characterization of self-heating effects (SHEs) in advanced FinFET devices. By analyzing waveform reflections within a standard RF-accessible structure, the method enables the real-time monitoring of drain current degradation with nanosecond-scale temporal resolution. The extracted thermal time constant of approximately 17 ns underscores the need for high-speed measurements for heat-free characterization. Compared to conventional approaches, the proposed technique eliminates the need for optical setups or frequency-domain modeling, offering enhanced simplicity, accuracy, and compatibility with future nanoscale CMOS technologies.