Nominalization of Split DC Link Voltage Dynamics in Three-Phase Three-Level Converters Operating Under Arbitrary Power Factor with Restricted Zero-Sequence Component

Abstract

The paper focuses on linearization of split DC link voltage dynamics and balancing their respective average values in three-phase three-level AC/DC converters. It was recently demonstrated that both AC-side current magnitude and operating power factor impact the dynamics of partial DC link voltage difference, imposing the time-varying behavior of split DC link voltages when a typical linear time-invariant compensator, e.g., proportional or proportional–integrative, is utilized. Consequently, robust split DC link voltage balancing loops would be beneficial. The case of a bandwidth-restricted (DC in a steady state) zero-sequence component employed as a control signal to equalize average partial DC link voltages is considered in this work. It is proposed to nominalize the dynamics of partial DC link voltage difference by means of a linear disturbance observer based on a frequency-selective filter so that the modified dynamics become linear and nearly nominal from a compensator point of view. As a result, the closed-loop response becomes time-invariant—a desirable characteristic of any practical system. Simulations validate the proposed methodology applied to a 10 kVA T-type converter model.

1. Introduction

The vital role of three-phase multilevel converters [1,2,3] in different industrial applications has been greatly acknowledged recently [4,5,6,7,8,9]. Referring to applications rated 10–100 kVA [10,11,12], the three-level three-phase topology (either unidirectional or bidirectional) has been recognized as a practical alternative to three-phase two-level converters [13,14,15,16] due to its reduced chip area requirements [17,18,19], improved electro-magnetic immunity [20] and better efficiency [21]. On the other hand, it should be emphasized that three-level converters typically employ split DC links [22,23,24,25]. Thus, their control structures must contain either an extra control loop [26,27] or dedicated additional hardware [28] in order to perform equalization (or balancing) of the partial DC link voltages. Considering the former case, the balancing process of partial DC link voltages is formed by two sub-tasks: the mandatory equalization of corresponding average components and the non-mandatory yet desired reduction in corresponding pulsating constituents. The task of control-only-based equalization is carried out by injecting certain zero-sequence components into the balanced set of three modulating signals generated by the main controller [29]. In order to fulfill the above-mentioned mandatory sub-task requirement, it is necessary to manipulate the DC component of the injected zero-sequence signal [24,30]. On the other hand, the fulfillment of the above-mentioned non-mandatory sub-task requires the zero-sequence signal to contain a significant high-frequency pulsating component, which may not be allowed in the case of, e.g., a four-wire topology, or in cases where parasitic stray capacitances are high enough to give rise to significant leakage currents [31,32]. In this brief, only the mandatory sub-task requirement is fulfilled; therefore, the zero-sequence signal is restricted to the DC component only in a steady state. It was shown in [33] that AC-side current magnitude impacts the dynamics of partial DC link voltage equalization loops in the case of their operation under a unity power factor. In [34], a numerical approach was used to derive a generalized expression of normalized ripple energy as a function of the power factor, which could then easily be utilized for assessments of split DC link voltage behaviors for certain DC link capacitances and reference voltages. This was carried out in [35], where a methodology for determining the minimum split DC link capacitance for a family of three-phase, three-level grid-connected bidirectional AC-DC converters operating under an arbitrary power factor under the restriction of DC-only zero-sequence injection was proposed. The minimum capacitance value was derived from the boundary condition, ensuring that the mains voltage remained below or equal to the capacitor voltage at all times. It was also revealed that operation with the lowest expected leading power factor should be employed as the design operating point. In [36], it was then identified that, in the case of operational power factor variation, the dynamics of the latter partial DC link voltage equalizing loop are influenced as well. Since a linear time-invariant controller (LTI) is typically employed as a partial DC link voltage equalization loop compensator, the corresponding closed-loop dynamics would possess operating-point-dependent characteristics. Such behavior is highly undesirable in multi-loop control structures due to the mutual influence between the loops. As a remedy, this technical note suggests adding an additional degree of freedom to the controller in order to nominalize the dynamics [37] by means of a linear disturbance observer [38,39] based on a frequency-selective filter. The proposed algorithm allows the plant “seen” by the loop compensator to become nearly LTI [40,41,42]. Consequently, the resulting closed-loop dynamics become LTI as well, so that the convergence rate is nearly the same throughout the whole operation range. It should be emphasized that, according to the literature review, the disturbance-observer-based equalization of partial DC link voltages in systems operating under arbitrary power factors under the restriction of DC-only zero-sequence injection has not been considered so far. Consequently, a short discussion regarding loop compensators and the proposed disturbance observer filter is presented, demonstrating that the latter must be formed by two terms possessing low-pass and band-stop behavior, respectively, to attain the above-mentioned nominal performance [43,44]. Simulation results are presented to demonstrate the initial feasibility and correctness of the proposed method.

2. Materials and Methods

2.1. Converter Under Study

A generalized topology of the type of three-phase three-level AC-DC converter under study is shown in Figure 1 (the discussion is kept as general as possible to demonstrate the applicability of the proposed method to any converter belonging to this topology). Multiple possible realizations of single-pole triple-throw switches sw_A, sw_B and sw_C may be found in, e.g., [29]. The split DC link of the converter is realized by two capacitances C_DC1 and C_DC2, with their corresponding voltages denoted as v_DC1 and v_DC2, respectively. Total DC link voltage is symbolized by v_DC = v_DC2 + v_DC1. The neutral points of the AC-side and split DC link voltages are symbolized as N and O, respectively (the two may either be connected or isolated from each other). The AC-side filters would typically be L-type or LCL-type, which are equivalent when switching-cycle-averaged values are of interest. Moreover, even though an AC-to-DC energy flow direction is assumed in the subsequent discussion, the analysis is valid for the reversed power flow direction as well. Referring to Figure 1, AC-side steady-state voltages and currents (all signals discussed below are switching-cycle-averaged) are assumed to obtain the following form,

$$\begin{array}{c}{\overrightarrow{v}}_{RST}(t)=\left(\begin{array}{c}{v}_{RN}(t)\\ v_{SN}(t)\\ v_{TN}(t)\end{array}\right)=V_M\left(\begin{array}{c}\sin \left({\omega }_{0}t\right)\\ \sin \left({\omega }_{0}t-\theta \right)\\ \sin \left({\omega }_{0}t+\theta \right)\end{array}\right)\hspace{0.17em}\\ {\overrightarrow{i}}_{RST}(t,\phi )=\left(\begin{array}{c}{i}_R(t,\phi )\\ i_S(t,\phi )\\ i_T(t,\phi )\end{array}\right)=I_M\left(\begin{array}{c}\sin \left({\omega }_{0}t-\phi \right)\\ \sin \left({\omega }_{0}t-\theta -\phi \right)\\ \sin \left({\omega }_{0}t+\theta -\phi \right)\end{array}\right)\end{array}$$

(1)

with $\theta =2\pi /3$; V_M and I_M representing voltage and current magnitudes, respectively; ω₀ symbolizing base frequency; and $\phi$ denoting an arbitrary phase.

Converter switches are operated by pulse-width-modulating signals of the form (neglecting voltage drops across AC-side filters)

$${\overrightarrow{m}}_{RST}(t)=\left(\begin{array}{c}{m}_R(t)\\ m_S(t)\\ m_T(t)\end{array}\right)\approx \left(\begin{array}{c}{M}_R(t)\sin \left({\omega }_{0}t\right)\\ M_S(t)\sin \left({\omega }_{0}t-\theta \right)\\ M_T(t)\sin \left({\omega }_{0}t+\theta \right)\end{array}\right)+m_0(t)$$

(2)

with

$${\overrightarrow{M}}_{RST}(t)=\left(\begin{array}{c}{M}_R(t)\\ M_S(t)\\ M_T(t)\end{array}\right)=V_M\cdot \left\{\begin{array}{cc}{v}_{DC1}^{-1}(t),& {\overrightarrow{v}}_{RST}(t)>0\\ v_{DC2}^{-1}(t),& {\overrightarrow{v}}_{RST}(t)<0\end{array}\right.$$

(3)

denoting the phase modulation indexes and m₀(t) symbolizing the zero-sequence component, respectively. As mentioned above, this brief assumes that only an m₀(t) containing a DC component in a steady state is allowed (i.e., equalization of average rather than instantaneous split DC link voltage is targeted). Defining the sum and the difference of partial DC link voltages as

$$v_{DC1}(t)+v_{DC2}(t)=v_{DC}(t)$$

(4)

and

$$v_{DC1}(t)-v_{DC2}(t)=\Delta v_{DC}(t),$$

(5)

respectively, the following is found:

$$\begin{array}{l}{v}_{DC1}(t)={\displaystyle \frac{1}{2}}\left(v_{DC}(t)+\Delta v_{DC}(t)\right),\\ v_{DC2}(t)={\displaystyle \frac{1}{2}}\left(v_{DC}(t)-\Delta v_{DC}(t)\right).\end{array}$$

(6)

Partial DC link voltage dynamics are then defined by (cf. Figure 2)

$$\begin{array}{cc}{C}_{DC1}{\displaystyle \frac{d{v}_{DC1}}{dt}}=i_1(t)-i_{DC1}(t),& C_{DC2}{\displaystyle \frac{d{v}_{DC2}}{dt}}=-\left(i_2(t)+i_{DC2}(t)\right),\end{array}$$

(7)

where

$$\begin{array}{cc}{i}_1(t)=i_{A1}(t)+i_{B1}(t)+i_{C1}(t),& i_2(t)=i_{A2}(t)+i_{B2}(t)+i_{C2}(t)\end{array}$$

(8)

with

$$\begin{array}{cc}{\overrightarrow{i}}_{ABC1}(t)=\left(\begin{array}{c}{i}_{A1}(t)\\ i_{B1}(t)\\ i_{C1}(t)\end{array}\right)=\left\{\begin{array}{cc}{\overrightarrow{i}}_{RST}(t),& {\overrightarrow{i}}_{RST}(t)>0\\ 0,& {\overrightarrow{i}}_{RST}(t)<0\end{array},\right.& {\overrightarrow{i}}_{ABC2}(t)=\left(\begin{array}{c}{i}_{A2}(t)\\ i_{B2}(t)\\ i_{C2}(t)\end{array}\right)=\left\{\begin{array}{cc}0& {\overrightarrow{i}}_{RST}(t),>0\\ {\overrightarrow{i}}_{RST}(t),& {\overrightarrow{i}}_{RST}(t)<0\end{array}.\right.\end{array}$$

(9)

Combining (6) with (7), defining

$$C_{DC}={\displaystyle \frac{1}{2}}\left(C_{DC1}+C_{DC2}\right), \Delta C_{DC}={\displaystyle \frac{1}{2}}\left(C_{DC1}-C_{DC2}\right)$$

(10)

and rearranging yields,

$$C_{DC}{\displaystyle \frac{\Delta d{v}_{DC}}{dt}}=\underset{i_{12}(t)}{\underbrace{i_1(t)+i_2(t)}}-\underset{\Delta i_{DC}(t)}{\underbrace{\left(i_{DC1}(t)-i_{DC2}(t)\right)}}-\underset{\Delta i_{CAP}}{\underbrace{\Delta C_{DC}{\displaystyle \frac{d{v}_{DC}}{dt}}}}=i_{12}(t)-\Delta i_{DC}(t)-\Delta i_{CAP}.$$

(11)

Elaborating (9), the following is found [35]:

$$\begin{array}{l}{i}_{12}(t)\hspace{0.17em}=m_0(t)i_0(t)-i_{11}(t),\\ i_0(t)=-\left(i_R(t)\mathrm{sgn}\left(v_R(t)\right)+i_S(t)\mathrm{sgn}\left(v_S(t)\right)+i_T(t)\mathrm{sgn}\left(v_T(t)\right)\right)\\ i_{11}(t)=i_R(t)\left|m_R(t)\right|+i_S(t)\left|m_S(t)\right|+i_T(t)\left|m_T(t)\right|\end{array}$$

(12)

with

$$\mathrm{sgn}\left(x(t)\right)=\left\{\begin{array}{cc}1,& x(t)>0\\ 0,& x(t)=0\\ -1,& x(t)<0\end{array}\right..$$

(13)

Hence (cf. (11) and (12)), the partial DC link voltage difference dynamics of the converter under study are given by

$$C_{DC}{\displaystyle \frac{\Delta d{v}_{DC}}{dt}}=m_0(t)i_0(t)-\left(i_{11}(t)+\Delta i_{DC}(t)+\Delta i_{CAP}\right),$$

(14)

as shown in Figure 3. Analyzing (12), the following is found [35]:

$$\begin{array}{cc}{i}_0(t)=\underset{i_{0,DC}}{\underbrace{{\displaystyle \frac{6}{\pi }}{I}_M\cos \phi }}+I_M{\displaystyle \sum _{n=1,odd}^{\infty }{\beta }_{6n}\sin (6n{\omega }_{0}t+{\psi }_{6n}),}& i_{11}(t)=M{I}_M{\displaystyle \sum _{n=1,odd}^{\infty }{\alpha }_{3n}\sin \left(3n{\omega }_{0}t+{\delta }_{3n}\right)}\end{array}$$

(15)

with β_6n, ψ_6n, α_3n and δ_3n being functions of φ. Observing the right-hand-side components of (14) while taking (15) into account, the following may be concluded:

• In case the zero-sequence component m₀(t) only contains a DC component in a steady state, only a DC component of i₀(t) (i.e., i_0,DC in (15)) should be considered as the control gain.
• The current i₁₁(t) contains no DC component in a steady state; hence, it cannot be counteracted by m₀(t).
• A non-zero Δi_DC reflects an unbalanced partial DC link loading, given in a steady state by

$$\Delta i_{DC}(t)=\Delta i_{DC,0}+\Delta i_{DC,HF}(t).$$

(16)

Hence, only its average component Δi_DC,0 may be offset by m₀(t). On the other hand, the corresponding zero-average pulsating component Δi_DC,HF (if present) cannot be worked against by m₀(t).

4.

In an AC-side balanced three-phase system, the total DC link voltage is constant in a steady state [26]. Therefore, Δi_CAP (cf. (11)) is expected to be zero in a steady state and does not have to be treated by m₀(t).

Consequently, (14) may be rewritten as

$$\begin{array}{l}{C}_{DC}{\displaystyle \frac{\Delta d{v}_{DC}(t)}{dt}}={\displaystyle \frac{6}{\pi }}{I}_M\cos \phi \cdot m_0(t)-\Delta i_{DC}(t)-\Delta i_{AC}(t),\\ \Delta i_{AC}(t)=-m_0(t)I_M{\displaystyle \sum _{n=1,odd}^{\infty }{\beta }_{6n}\sin (6n\omega t+{\psi }_{6n})}+M{I}_M{\displaystyle \sum _{n=1,odd}^{\infty }{\alpha }_{3n}\sin \left(3n\omega t+{\delta }_{3n}\right)}+\Delta i_{CAP}.\end{array}$$

(17)

It is then evident that the optimal zero-sequence component is given by

$$m_0(t)={\displaystyle \frac{\Delta i_{DC}(t)}{\frac{6}{\pi }{I}_M\cos \phi }}.$$

(18)

Moreover, it should be emphasized that even if the average values of the partial DC link voltages are equalized (i.e., Δi_DC is fully counteracted), the corresponding voltages would still contain ripple components imposed by the non-compensated term Δi_AC(t). The interested reader is referred to [34] for additional details.

2.2. Partial DC Link Voltage Equalization Problem

According to (17), a simplified block diagram of partial DC link voltage difference dynamics is depicted in Figure 4.

Typically, a proportional (or proportional–integrative) controller is employed to compensate the partial DC link voltage difference loop. Considering the former (for brevity), with gain given by K, closed-loop responses to a step-like variation in Δi_DC and to a non-zero initial condition Δv_DC(0) are obtained as

$$\begin{array}{cc}\Delta v_{DC}(t)=-{\displaystyle \frac{\Delta i_{DC}}{\frac{6}{\pi }K{I}_M\cos \phi }}\left(1-\exp (-{\displaystyle \frac{t}{\tau }})\right)+\Delta v_{DC}(0)\exp (-{\displaystyle \frac{t}{\tau }}),& \tau ={\displaystyle \frac{C_{DC}}{\frac{6}{\pi }K{I}_M\cos \phi }}\end{array}$$

(19)

respectively, so that both the steady-state error (imposed only by Δi_DC) and the convergence time constant τ depend on both the AC-side current magnitude I_M and power factor cosφ. It may be concluded that the equalization process cannot be accomplished with zero load and/or zero power factor since the system loses controllability under these conditions. Denoting the apparent and active power processed by the converter as S [VA] and P [W], respectively, the following is found:

$$P=S\cos \phi ={\displaystyle \frac{3}{2}}{V}_M{I}_M\cos \phi \Rightarrow I_M={\displaystyle \frac{2}{3}}{\displaystyle \frac{P}{V_M\cos \phi }}={\displaystyle \frac{2}{3}}{\displaystyle \frac{S}{V_M}}.$$

(20)

Hence,

$$I_M\cos \phi ={\displaystyle \frac{2}{3}}{\displaystyle \frac{P}{V_M}}={\displaystyle \frac{2}{3}}{\displaystyle \frac{S}{V_M}}\cos \phi ,$$

(21)

i.e., the left-hand-side term in (21) remains constant only if the active power is kept constant. This is not the case in practice, where a converter is often imposed to operate, e.g., with nominal rated apparent power yet with different power factors. It is evident from (19) that operation with rated current I_M = I_M,R at a unity power factor cosφ = 1 yields the smallest steady-state error and the shortest convergence time constant, given by

$$\begin{array}{cc}\Delta v_{DC}(t\to \infty )=-{\displaystyle \frac{\Delta i_{DC}}{\frac{6}{\pi }K{I}_{M,R}}},& \tau ={\displaystyle \frac{C_{DC}}{\frac{6}{\pi }K{I}_{M,R}}}\end{array}$$

(22)

respectively. Unfortunately, the dynamics of the partial DC link voltage equalization process would vary significantly under non-constant loading, as follows from (19). Moreover, operation with de-rated loading or under a non-unity power factor would deteriorate the two performance merits in (22). It may not be convenient (or possible) to estimate the instantaneous power factor and subsequently compensate it using, e.g., a feedforward action to maintain nominal performance. Consequently, it is further suggested to nominalize the partial DC link voltage difference plant (i.e., bring it to approximately LTI form) by means of a disturbance observer in order to yield nearly similar closed-loop performance throughout the whole operation range without relying on power factor measurement, as follows.

2.3. Disturbance-Observer-Based Nominalization

Rearranging (17) as

$$\begin{array}{l}{C}_{DC}{\displaystyle \frac{\Delta d{v}_{DC}}{dt}}=\left({\displaystyle \frac{6}{\pi }}{I}_M\cos \phi +{\displaystyle \frac{6}{\pi }}{I}_{M,R}-{\displaystyle \frac{6}{\pi }}{I}_{M,R}\right)m_0(t)-\Delta i_{DC}(t)-\Delta i_{AC}(t)\\ ={\displaystyle \frac{6}{\pi }}{I}_{M,R}{m}_0(t)-\left(({\displaystyle \frac{6}{\pi }}{I}_{M,R}-{\displaystyle \frac{6}{\pi }}{I}_M\cos \phi )m_0(t)+\Delta i_{DC}(t)\right)-\Delta i_{AC}(t)\end{array}$$

(23)

and applying the Laplace transform yields

$$\Delta v_{DC}(s)={\displaystyle \frac{6}{\pi }}{\displaystyle \frac{I_{M,R}}{C_{DC}s}}\left(m_0(s)-m_{DC}(s)-m_{AC}(s)\right)$$

(24)

with

$$\begin{array}{l}{m}_{DC}(s)=(1-{\displaystyle \frac{I_M\cos \phi }{I_{M,R}}})m_0(s)+{\displaystyle \frac{1}{\frac{6}{\pi }{I}_{M,R}}}\Delta i_{DC}(s),\\ m_{AC}(s)={\displaystyle \frac{1}{\frac{6}{\pi }{I}_{M,R}}}\Delta i_{AC}(s)\end{array}$$

(25)

denoting lumped DC and AC disturbance terms [44,45,46], respectively. Recall that it is desired to eliminate the influence of m_DC without affecting that of m_AC to impose the DC-only content of m₀ in a steady state. Consequently, splitting the zero-sequence signal as

$$m_0(s)=m_{0,R}(s)+{\tilde{m}}_{DC}(s)$$

(26)

with the latter denoting the lumped DC disturbance estimate, and using this with (24) results in

$$\Delta v_{DC}(s)={\displaystyle \frac{6}{\pi }}{\displaystyle \frac{I_{M,R}}{C_{DC}s}}\left(m_{0,R}(s)+{\tilde{m}}_{DC}(s)-m_{DC}(s)-m_{AC}(s)\right)\cong {\displaystyle \frac{6}{\pi }}{\displaystyle \frac{I_{M,R}}{C_{DC}s}}\left(m_{0,R}(s)-m_{AC}(s)\right)$$

(27)

in cases where the estimate in (26) is accurate. The resulting dynamics (27) are evidently independent of both AC-side current magnitude I_M and power factor cosφ, as desired. It is then proposed to obtain the lumped DC disturbance estimate in (26) as follows. According to (24), the following is found:

$$m_{DC}(s)=m_0(s)-{\displaystyle \frac{\pi }{6}}{\displaystyle \frac{C_{DC}}{I_{M,R}}}s\Delta v_{DC}(s)-m_{AC}(s).$$

(28)

Unfortunately, (28) cannot be used as is in (26) due to the following issues:

-

Non-causality;

-

Noisy derivative action;

-

Unknown m_AC(t).

In order to solve the above-mentioned issues, (24) is first rewritten as

$$m_{DC}(s)+m_{AC}(s)=m_0(s)-{\displaystyle \frac{\pi }{6}}{\displaystyle \frac{C_{DC}}{I_{M,R}}}s\Delta v_{DC}(s).$$

(29)

Then, a lumped DC disturbance estimate is obtained by passing (29) though an LTI filer G(s), as in [47,48,49,50,51]

$${\tilde{m}}_{DC}(s)=G(s)\left(m_{DC}(s)+m_{AC}(s)\right)=G(s)m_0(s)-{\displaystyle \frac{\pi }{6}}{\displaystyle \frac{C_{DC}}{I_{M,R}}}sG(s)\Delta v_{DC}(s).$$

(30)

Using the estimate (30) with (27), the following is found:

$$\Delta v_{DC}(s)={\displaystyle \frac{6}{\pi }}{\displaystyle \frac{I_{M,R}}{C_{DC}s}}\left(m_{0,R}(s)-\left(1-G(s)\right)m_{DC}(s)-\left(1-G(s)\right)m_{AC}(s)\right).$$

(31)

Obviously, causality is no issue anymore due to the non-zero delay introduced by the filter G(s). Note that the filter transfer function G(s) must be strictly proper in order to have sG(s) be at least proper. In addition, G(s) must be capable of passing the components of m_DC(t) while blocking the constituents of m_AC(t). Consequently, in order to have

$$\begin{array}{cc}\left(1-G(s)\right)m_{DC}(s)\approx 0,& \left(1-G(s)\right)m_{AC}(s)\approx m_{AC}(s),\end{array}$$

(32)

the filter G(s) may be formed by the two following terms

$$G(s)=G_1(s)G_2(s),$$

(33)

with G₁(s) possessing low-pass characteristics to have |G₁(ω)| ≈ 1 within the bandwidth of m_DC(s), and G₂(s) possessing multi-notch characteristics to have

$$\left|G_2(\omega )\right|=\left\{\begin{array}{cc}0,& \omega =n{\omega }_0\\ 1,& elswhere\end{array}\right.$$

(34)

for any relevant value of n. Once the system is nominalized, the corresponding loop gain would be given by

$$L(s)\cong {\displaystyle \frac{6}{\pi }}{\displaystyle \frac{I_{M,R}}{C_{DC}s}}K.$$

(35)

The loop crossover frequency ω_C should then be selected at least one decade below that of the lowest frequency component of i_AC(t) to ensure frequency decoupling. Consequently, K should be selected as

$$\left|L({\omega }_C)\right|={\displaystyle \frac{6}{\pi }}{\displaystyle \frac{I_{M,R}}{C_{DC}{\omega }_C}}K=1\Rightarrow K={\displaystyle \frac{\pi }{6}}{\displaystyle \frac{C_{DC}{\omega }_C}{I_{M,R}}}.$$

(36)

The overall resulting closed-loop block diagram is depicted in Figure 5.

3. Example

In order to demonstrate the proposed methodology feasibility, consider the 10 kVA LCL-filter-based three-phase three-level T-type converter shown in Figure 6, operating at 50 kHz switching frequency with v_DC = 800 V DC. Partial DC link capacitances of 440 μF each were used. AC components of the modulation signals (2) were applied to operate the power stage in semi-open-loop so that its AC side generated a balanced, three-phase, 50 Hz, 400 V supply (i.e., V_M = 230$\sqrt{2}$ V, I_M,R = 16$\sqrt{2}$ A). The LCL filters were formed by L_f1 = 340 μH and L_f2 = 10 μH inductors, as well as C_f = 10μF capacitors. The value of m₀(t) was generated in a closed-loop fashion as shown in Figure 5. According to (17), the lowest harmonic component of Δi_AC(t) resides at 150 Hz; hence, the crossover frequency was selected one decade below, i.e., ω_C = 2π∙15 rad/s. Consequently, cf. (35),

$$K={\displaystyle \frac{\pi }{6}}{\displaystyle \frac{C_{DC}{\omega }_C}{I_{M,R}}}=0.001$$

(37)

was selected. Moreover, it was recently revealed in [43] that m_AC(t) is dominated by third and ninth harmonics. Consequently, the frequency-selective filter G(s) was selected as [47,52]

$$G(s)=\underset{G_1(s)}{\underbrace{{\displaystyle \frac{{\omega }_f}{s+{\omega }_f}}}}\underset{G_2(s)}{\underbrace{{\displaystyle \frac{s^2+{\left(3{\omega }_0\right)}^2}{s^2+6\xi {\omega }_{0}s+{\left(3{\omega }_0\right)}^2}}{\displaystyle \frac{s^2+{\left(9{\omega }_0\right)}^2}{s^2+18\xi {\omega }_{0}s+{\left(9{\omega }_0\right)}^2}}}}$$

(38)

with ω_f = 1 kHz and ξ = 0.1. It is well-evident that the filter possesses unity gain at low frequencies and zero gain at third and ninth base frequency harmonics, cf. (33).

Two sets of simulations (PSIM 2023 software) were carried out under both a unity power factor for different loadings and under rated loading for different values of the power factor. The first simulation set was carried out utilizing a proportional controller only; the second simulation set was carried out employing a combination of the same proportional controller and the proposed disturbance observer. All the simulations were set up as follows: The reference value of split DC link voltage difference ${∆v}_{DC}^{*}$ in Figure 5 was set to 50 V at t = 0 s and then reduced to 0 V at t = 1 s. Transients corresponding to the first simulation set (utilizing proportional controller only) around t = 1 s are depicted in Figure 7 (partial DC link voltages, their differences and corresponding signals with filtered high-frequency ripple) for different values of AC-side current magnitude under unity power factor operation and in Figure 8 for different values of the power factor under rated AC-side current magnitude operation. Transients corresponding to the second simulation set (utilizing the same proportional controller as above and the proposed disturbance converter) around t = 1 s are depicted in Figure 9 for different values of AC-side current magnitude under unity power factor operation and in Figure 10 for different values of the power factor under rated AC-side current magnitude operation. Corresponding 2% settling times t_s are indicated in all Figures and summarized in

Table 1. Summary of settling times, proportional controller only (Figure 7 and Figure 8).

${\mathit{I}}_{\mathit{M}}$	cosφ	ts [ms]
$I_{M,R}$	1	35
${0.5I}_{M,R}$	1	70
$0.25I_{M,R}$	1	140
$0.1I_{M,R}$	1	350
$I_{M,R}$	0.5	70
$I_{M,R}$	0.25	140
$I_{M,R}$	0.1	350

and

Table 2. Summary of settling times, proportional controller with disturbance observer (Figure 9 and Figure 10).

${\mathit{I}}_{\mathit{M}}$	cosφ	ts [ms]
$I_{M,R}$	1	35
${0.5I}_{M,R}$	1	37
$0.25I_{M,R}$	1	39
$0.1I_{M,R}$	1	41
$I_{M,R}$	0.5	37
$I_{M,R}$	0.25	39
$I_{M,R}$	0.1	350

, respectively.

4. Discussion

Observing Figure 7, it may be concluded that since an AC-side current magnitude reduction implies a loading decrease, the ripple components of the partial voltages lessen as expected. In addition, the corresponding convergence rate also reduces with AC-side current magnitude reduction under proportional-only control, as anticipated from (19). It was also expected from (19) that the AC-side current magnitude and power factor would have the same influence on the convergence rate. This is well-verified by Figure 8, where the filtered values of the partial voltages and their corresponding difference converge with similar rates to those of Figure 5, even though the partial voltage ripples increase in Figure 8, as opposed to Figure 7. It should be mentioned that the fact that partial voltage ripples increase upon operating power factor reduction while keeping the apparent power unchanged was recently revealed in [35]. To conclude, the influence of the AC-side current magnitude and power factor on partial DC link voltage dynamics is clearly evident in Figure 7 and Figure 8. On the other hand, it may be concluded by examining Figure 9 and Figure 10 that while the behavior of the partial DC link voltage ripples under the proposed proportional + disturbance observer control remains similar to that under proportional-only control (as expected), the corresponding DC components converge with nearly the same nominal time constant (cf. (22)) irrespective of either AC-side current magnitude or power factor, as desired. This is due to the nominalization action of the proposed disturbance observer based on a frequency-selective filter. As a result, the closed-loop dynamics of split DC link voltage balancing become nearly linear and time-invariant, as desired. This validates the proposed methodology successfully.

5. Conclusions

It is well-known that both AC-side current magnitude and operating power factor impact the dynamics of partial DC link voltage difference. As a result, employing a typical linear time-invariant compensator yields time-varying behavior for split DC link voltages. It was hence shown in this work that the use of a disturbance observer in addition to the typical linear controller allows us to nominalize the dynamics of the split DC link voltage equalization loop. As a result, the closed-loop convergence rate remains almost the same over the whole operating range, at the expense of a more complicated controller structure. Such a characteristic simplifies the tuning process of other (typically multiple) control loops employed. Simulations carried out by applying the proposed methodology to a 10 kVA T-type converter successfully validated the revealed findings. Future work on the subject should include an in-depth analysis of the proposed methodology in terms of attainable convergence rate under finite switching/sampling rate constraints, examining the feasibility of its application to converters operating with unrestricted zero-sequence components and providing corresponding experimental verification. It is expected that real-world systems (e.g., inverters, motor drives, EV chargers, etc.) adopting the proposed methodology would benefit from improved reliability and safety, reduced harmonic content and prolonged capacitor lifetime.