Pisla, M.-A.; Enache, B.-A.; Argyriou, V.; Sarigiannidis, P.; Voicila, T.-I.; Seritan, G.-C.
High-Speed SMVs Subscriber Design for FPGA Architectures. Electronics 2025, 14, 2135.
https://doi.org/10.3390/electronics14112135
AMA Style
Pisla M-A, Enache B-A, Argyriou V, Sarigiannidis P, Voicila T-I, Seritan G-C.
High-Speed SMVs Subscriber Design for FPGA Architectures. Electronics. 2025; 14(11):2135.
https://doi.org/10.3390/electronics14112135
Chicago/Turabian Style
Pisla, Mihai-Alexandru, Bogdan-Adrian Enache, Vasilis Argyriou, Panagiotis Sarigiannidis, Teodor-Iulian Voicila, and George-Calin Seritan.
2025. "High-Speed SMVs Subscriber Design for FPGA Architectures" Electronics 14, no. 11: 2135.
https://doi.org/10.3390/electronics14112135
APA Style
Pisla, M.-A., Enache, B.-A., Argyriou, V., Sarigiannidis, P., Voicila, T.-I., & Seritan, G.-C.
(2025). High-Speed SMVs Subscriber Design for FPGA Architectures. Electronics, 14(11), 2135.
https://doi.org/10.3390/electronics14112135