A 0.6 V 68.2 dB 0.42 µW SAR-ΣΔ ADC for ASIC Chip in 0.18 µm CMOS

Abstract

This paper presents a successive approximation register (SAR) and incremental sigma-delta modulator (ISDM) hybrid analog-to-digital converter (ADC) that operated at a minimum voltage supply of 0.575 V. A thorough analysis of the non-linearities caused by PVT variations and common-mode voltage (VCM) shifts in the ISDM stage is presented. The ADC employs an improved high-precision double-bootstrapped switch, and the synchronous clock is also double-bootstrapped to work under the low supply voltage. A modified merged capacitor switching (MCS) approach is presented to maintain a stable VCM at the differential input. The chip was fabricated using a 0.18 µm CMOS process, with a core area of 0.21 mm². It consumed only 0.42 µW at a 0.6 V supply and a sampling rate of 10 kS/s, which achieved an effective number of bits (ENOB) of 11.03. The resulting figure of merit (FOM_W) was 20.05 fJ/conversion-step, which is the lowest reported for ADCs of this architecture in a 0.18 µm process.

1. Introduction

In recent years, the design of low-power analog-to-digital converters (ADCs) [1,2,3,4,5,6,7,8] has been a focal point, with applications spanning various fields, including biomedical sensors [9,10,11,12,13,14] and wireless sensors. These ADCs are commonly employed for online monitoring, detection, the prevention of various diseases, and wireless communication. At the same time, they must meet the criteria for cost effectiveness, high resolution, and extended life. Since they are often integrated into devices that function independently of external power sources for long durations, with sampling rates below 10 kHz, they must also adhere to strict standards for low voltage, minimal power consumption, and compact size. The successive approximation register (SAR) ADC, due to its simple structure and ease of integration, is commonly used to achieve medium-to-high precision [15,16,17,18]. However, as the demand for resolution increases, the accuracy of SAR ADCs is limited by $kT/C$ and comparator noise. A sigma-delta ADC can achieve over 10-bit accuracy through noise shaping and oversampling techniques [19,20,21,22]. The time-domain incremental sigma-delta modulator (ISDM) [23] incorporates the residue from all comparisons through the passive summation method after SAR conversion to achieve a higher signal-to-noise ratio (SNR) at the cost of lower power consumption and relaxed noise requirements. Hence, combining SAR ADCs with ISDM ADCs is feasible to achieve conversions of more than 10b. In [24], a first-order noise shaping was completed by a high-gain gated delay oscillator, which employs time-domain integration techniques. However, in reality, voltage-to-time conversion in such circuits is subject to non-linearities arising from PVT variations and common-mode voltage (VCM) shifts. These limitations hinder further improvements in ADC accuracy by the ISDM stage, while detailed investigations into these non-linear effects remain scarce in the literature.

In recent years, improving the linearity of bootstrapped switches has been a focal point in high-precision ADC design [25,26,27,28,29]. The low supply voltage may lead to subthreshold leakage currents due to the narrowing gap with the $Vth$ of the MOSFET. To reduce the leakage current of the sampling switch, ref. [30] proposes a double-boosted S/H with adaptive body voltage biasing, in which an additional gate is implemented for input isolation at the holding phase to minimize the signal-dependent channel leakage during conversion. At the holding phase, the gate and body nodes of cascaded sampling switches are connected to ground [31]. However, owing to non-idealities in the layout design, the gate voltage of the sampling switch cannot be precisely driven to ground, thereby still potentially causing a subthreshold leakage current. Therefore, it affects the overall linearity of the ADC. In low-power signal conversion, the low threshold voltages and the low sampling rate can exacerbate the impact of leakage currents during the holding phase, thus reducing the overall accuracy.

To address the issues mentioned above, we present a 13-bit hybrid ADC. The contributions of this work can be summarized in the following aspects:

(1)

A thorough analysis of the ISDM non-linear effect: First, the kickback noise of the voltage-controlled delay line (VCDL) was analyzed, which caused the VCM shift at the differential input of the ISDM stage. Then, the impact of PVT variations and VCM-induced shifts on the non-linearity of the ISDM stage was thoroughly investigated. Since the ISDM stage was highly sensitive to VCM shifts, this paper further proposes a modified merged capacitor switching (MCS) scheme to maintain a constant VCM during the conversion process, thereby mitigating non-linearity degradation.

(2)

A 13-bit hybrid bottom-plate sampling ADC architecture: The design first employed the presented bootstrap switches for bottom-plate sampling to reduce the leakage current. A 10-bit SAR ADC with the MCS scheme was then introduced to maintain the differential output of the VCDL at a constant common-mode level, thereby mitigating non-linearity and eliminating the need for a dedicated VCM voltage. This was followed by a 4-bit conversion performed by the ISDM ADC, including 1 redundant bit, resulting in an overall resolution of 13 bits.

(3)

Solid testing result of the low-power-consumption ADC: The chip testing results indicate that the circuit consumed a minimum power of 0.42 µW at a sampling rate of 10 kHz, with a supply voltage of 0.6 V. These findings demonstrate the robustness of our circuit. With a core area of 0.21 mm² in 0.18 µm CMOS technology, the SNDR was measured at 68.2 dB, and the FOMw of 20.05 fJ/conversion-step was the lowest reported for ADCs of this architecture in a 0.18 µm process.

This brief is organized as follows: Section 2 introduces the overall architecture of the SAR ISDM ADC, Section 3 analyses the non-linearities of the ISDM stage, and Section 4 presents the circuit implementation of the SAR–ISDM ADC. Section 5 showcases the measurement results. Finally, Section 6 concludes this paper.

2. Architecture Review of the SAR–ISDM ADC

Low-power ADCs are widely used in biomedical applications due to their stringent energy and noise requirements. In processing electrocardiogram (ECG) signals, as shown in Figure 1, the typical signal flow starts with an analog front-end (AFE) for signal amplification and filtering, followed by digitization using a low-power ADC, such as the proposed SAR–ISDM ADC. The resulting digitized ECG waveform can then be analyzed in the digital domain.

The basic architecture of a SAR–ISDM ADC, as shown in Figure 2, consists of five parts: a sample and hold switch; a capacitive digital-to-analog converter (CDAC); a voltage-controlled oscillator (VCO), which consists of a voltage-to-time (V2T) converter and a switch; a comparator; and SAR logic. The input voltage is sampled and held constant during the conversion, with the accuracy of the ADC dependent on how precisely this held voltage is maintained. Then, the SAR ADC stage uses the binary search algorithm by switching the CDAC to several voltage levels for the comparators. Next, the SAR logic generates control signals for the CDAC switches through the registers based on the comparator’s results, thereby producing the next set of voltage levels.

Taking the differential input case in Figure 2 as an example, when the first comparison result shows $V_{IP}>V_{IN}$, the CDAC generates voltages of $V_{IP}-{\displaystyle \frac{V_{ref}}{2}}$ and $V_{IN}+{\displaystyle \frac{V_{ref}}{2}}$ (where $V_{ref}$ is the reference voltage provided externally). The comparison then continues, finally generating voltages of $V_{IP}-{\displaystyle \frac{m}{2·2^n}}$ and $V_{IN}+{\displaystyle \frac{m}{2·2^n}}$, where n is the resolution of the SAR ADC and the integer m is the quantized result of this differential voltage.

The switches in the two VCOs remain open and the V2T converter transforms the voltages on the top plates of the CDAC into the time domain. The magnitudes of the voltages are converted into the durations of the pulse delay in the i-th loop:

$$T_{IP}=V2T·(V_{IP}-{\displaystyle \frac{k}{2·2^i}})+T_{DC}$$

(1)

$$T_{IN}=V2T·(V_{IN}+{\displaystyle \frac{k}{2·2^i}})+T_{DC}$$

(2)

where $V2T$ is the voltage-to-time amplification factor and $T_{DC}$ is the delay constant. The pulses are then fed into the comparator in the form of 0/1. In the ISDM stage, a VCO is formed by closing the switch. The differential residual voltage $V_{res\_sar}$ remaining on the top plates of the CDAC passes through the V2T converter to the VCO. In each subsequent loop, the incremental voltage on the ISDM capacitor is combined with the residual voltage entering the VCO, where they are summed with the previous delay of time $T_{SDM\left[i\right]}$ before being passed to the comparator for quantization, as shown in the following equations:

$$\begin{array}{cc}\hfill V_{IP}\left[i\right]-V_{IN}\left[i\right]& =V_{res\_sar}(@i=1)\hfill \\ \hfill & =V_{res\_sar}+{(-1)}^{Q_{out}[i-1]}·V_{ISDM}(@i>1),\hfill \end{array}$$

(3)

$$T_{SDM\left[i\right]}=\sum _{n=1}^{i}V2T(V_{IP}\left[n\right]-V_{IN}\left[n\right]).$$

(4)

As shown in Figure 3, the transfer function with the noise injection in the ISDM stage is written as follows:

$$D_i\left(z\right)=z^{-1}(V_{in}\left(z\right)+V_{n,VTC}\left(z\right)+{\displaystyle \frac{T_{n,Osc}\left(z\right)}{A_{VTC}}})+(1-z^{-1})({\displaystyle \frac{T_{n,CMP2}\left(z\right)}{A_{VTC}}}+{\displaystyle \frac{Q_2\left(z\right)}{A_{VTC}}})$$

(5)

where $V_{n,VTC}\left(z\right)$, $T_{n,Osc}\left(z\right)$, $T_{n,CMP2}\left(z\right)$, and $Q_2\left(z\right)$ denote noise sources from the voltage-to-time converter, the oscillator, time comparator, and the quantization noise. It can be seen that the larger the voltage-to-time conversion gain $A_{VTC}$, the stronger the noise suppression and the higher the accuracy of the ISDM stage.

As shown in Figure 4, our design employs a two-stage conversion comprising a SAR ADC followed by an ISDM ADC. The first stage, the SAR ADC, features 11 conversion cycles with a redundant bit in its CDAC, achieving a 10-bit quantization. The second stage utilizes an incremental sigma-delta architecture with a VCO accumulator and a single-unit switch capacitor for incremental subtraction [23]. This stage involves a total of 16 comparisons, resulting in a 4-bit quantization. The ISDM ADC shares one redundant bit with the SAR stage, achieving a total resolution of 13 bits. To enhance the sampling precision, a bottom-plate sampling technique is employed, effectively avoiding the participation of parasitic capacitance at the input of the comparator in the sampling process and mitigating charge injection. To reduce the leakage charge from the sampling switch during the hold phase, a modified double-bootstrapped switch with a negative gate voltage is employed. Since the high level of the synchronous clock may not be sufficient to turn on the switch connecting the VCM to the capacitor top plate at low supply voltages, another modified double-bootstrapped switch is presented to increase the high level of the clock. In order to reduce the usage of VCM during the conversion, a modified MCS approach is presented.

3. Non-Linearity Analysis of the ISDM Stage

3.1. VCM Shift Induced by Kickback Noise

As shown in Figure 5, the schematic of VCDL illustrates that when the input clock signal $CLK\_in$ transitions from 0 to 1, the voltage at node D drops to 0, and the voltages at nodes A, B, and C gradually decrease. The delay from $CLK\_in$ to $CLK\_out$ is controlled by the gate voltages $V_{\left[i\right]}$ of transistors $M_1$, $M_2$, and $M_3$. A higher $V_{\left[i\right]}$ results in a shorter delay. When $CLK\_in$ transitions from 1 to 0, the PMOS transistor turns on and $CLK\_out$ is reset to 0, during which the delay is independent of $V_{\left[i\right]}$.

However, during the transition of $CLK\_in$, the voltage $V_{\left[i\right]}$ also changes. This is due to the voltage variations at nodes A, B, C, and D, which are capacitively coupled to $V_{\left[i\right]}$ through capacitances $C_{gd1}$, $C_{gd2}+C_{gs2}$, $C_{gd3}+C_{gs3}$, and $C_{gs4}$, respectively, leading to charge redistribution at node $V_{\left[i\right]}$. For example, when $CLK\_in$ transitions from 0 to 1, the voltage $V_{\left[i\right]}$ decreases. The differential voltages $in$ and $ip$ decrease proportionally to the ratio of the aforementioned capacitances to the total terminal capacitance, and these capacitances depend on the size of the transistors. Consequently, the VCM of the differential pair also decreases. The variation in $V_{\left[i\right]}$ is shown in Figure 6. When the rising edge of the clock in the VCO propagates through a five-stage VCDL, the voltages at nodes $in$ and $ip$ decrease. When the clock in the VCO is reset to 0, the voltages at nodes $in$ and $ip$ show increments. The total VCM offset reached 1.89 mV.

3.2. The VCM- and PVT-Sensitive V2T Term

The added delays of the differential nodes $T_{outp\left[i\right]}$ and $T_{outn\left[i\right]}$ are formulated as [23]

$$T_{outp\left[i\right]}=T_{DC}+(V_{P\left[i\right]}-V_{com})V2T$$

(6)

$$T_{outn\left[i\right]}=T_{DC}+(V_{N\left[i\right]}-V_{com})V2T$$

(7)

where $T_{DC}$ and $V2T$ are the delay constant independent of $V_{\left[i\right]}$ and the voltage-to-time constant, respectively.

$$\Delta T_{outn\left[i\right]}=T_{outp\left[i\right]}-T_{outn\left[i\right]}=(V_{P\left[i\right]}-V_{N\left[i\right]})\times V2T$$

(8)

where $\Delta T_{outn\left[i\right]}$ means the added time difference of the oscillator. However, the $V2T$ term, which directly affects the quantization accuracy, is not independent of VCM. Figure 7 presents the differential responses measured for $V2T$ under VCM = 322 mV, 323 mV, 324 mV, and 325 mV at TT (27 °C). As the VCM increased, the delay in $V2T$ decreased. A 1 mV shift in the VCM resulted in a horizontal shift of $T_{DC}$ throughout the $V2T$ response range, and a 3 mV VCM shift could lead to a $V2T$ variation of 8.3%, indicating that the VCDL module was highly sensitive to variations in the VCM. As shown in Figure 6, the impact of kickback noise on the VCM of $V_{\left[i\right]}$ in the VCDL module is illustrated. A 1.89 mV common-mode shift caused by kickback noise led to significantly different voltage-to-time characteristics across the five VCDL stages.

Figure 8 also shows the $V2T$ linearity measured under different supply voltages (0.6 V, 0.65 V, and 0.7 V). It can be observed that supply voltage fluctuations have a substantial impact on $V2T$ behavior, with variations up to 5.2%. Furthermore, lower supply voltages resulted in worse linearity. Figure 9 illustrates the effect of process corners at SS (110 °C) and FF (−40 °C). The difference in $V2T$ caused by the process variation could reach up to 10.15×.

$$16T_{res\_ISDM}=\sum _{i=1}^{16}V2T\left(i\right)·V_{res\_SAR}+\sum _{i=2}^{16}V2T\left(i\right)·{(-1)}^{Q_{out}[i-1]}{\displaystyle \frac{8}{16}}{V}_{LSB}.$$

(9)

where $T_{res\_ISDM}$ is the time difference measured after the ISDM stage, which has the aforementioned relationship with the ISDM output. Here, as analyzed above, $V2T\left(i\right)$ is a PVT-sensitive term and is also affected by the VCM variation in each conversion, which degrades the accuracy of the ISDM output.

Now, let

$${\displaystyle \frac{1}{16}}\sum _{i=1}^{16}V2T\left(i\right)=\overline{V2T}.$$

(10)

Then, in the ideal case, the residual in the voltage domain can be represented in terms of $V_{res\_ISDM\_i}$:

$$16\overline{V2T}·V_{res\_ISDM\_i}=16\overline{V2T}·V_{res\_SAR}+\sum _{i=2}^{16}\overline{V2T}·{(-1)}^{Q_{out\_i}[i-1]}{\displaystyle \frac{8}{16}}{V}_{LSB}.$$

(11)

In the actual case, the residual in the voltage domain can be represented in terms of $V_{res\_ISDM\_a}$:

$$16\overline{V2T}·V_{res\_ISDM\_a}=16\overline{V2T}·V_{res\_SAR}+\sum _{i=2}^{16}V2T\left(i\right)·{(-1)}^{Q_{out\_a}[i-1]}{\displaystyle \frac{8}{16}}{V}_{LSB}.$$

(12)

Then, the error residual delay time after the ISDM stage can be represented as

$$T_{res\_ISDM\_error}=16\overline{V2T}·V_{res\_ISDM\_i}-16\overline{V2T}·V_{res\_ISDM\_a}$$

(13)

Then, the error voltage can be represented as

$$V_{res\_ISDM\_error}={\displaystyle \frac{1}{16}}\sum _{i=2}^{16}({(-1)}^{Q_{out\_i}[i-1]}-{\displaystyle \frac{V2T\left(i\right)}{\overline{V2T}}}·{(-1)}^{Q_{out\_a}[i-1]}){\displaystyle \frac{8}{16}}{V}_{LSB}.$$

(14)

It can be observed that the magnitude of the error voltage is solely related to the linearity of the $V2T$ transfer curve under this PVT and VCM, despite the fact that the $V2T$ transfer curves differ under different PVT conditions (of course, the magnitude of $V2T$ under different PVT conditions affects the suppression of other noise, but the impact of other noise is not considered for now). Here, we focus solely on the effect of the $V2T$ linearity on the accuracy of the ISDM ADC.

Now, assume that each point on the $V2T$ curve deviates from $\overline{V2T}$ by an error of $ϵ$. The largest deviation, $V_{\mathrm{res}\_\mathrm{ISDM}\_\mathrm{error}}$, occurs at the midpoint of the curve. Now, consider the worst-case scenario when the maximum error of $V2T$ is $ϵ$, and $V_{\mathrm{res}\_\mathrm{ISDM}\_\mathrm{a}}$ and $V_{\mathrm{res}\_\mathrm{ISDM}\_\mathrm{i}}$ differ by exactly $1V_{\mathrm{LSB}}$:

$$8\overline{V2T}-7\overline{V2T}=7(1+ϵ)\overline{V2T}-8(1-ϵ)\overline{V2T}.$$

(15)

It can be concluded that the value of $ϵ$ is 13%. At this point, error codes ranging from 6 to 11 will appear (in the ISDM outputs $Q_2\sim Q_{16}$). Considering only the $V2T$ non-linearity and quantization noise, let $V_{LSB\_ISDM}=▵$; the total noise power can be calculated using

$$P_{noise}=6\times {\displaystyle \frac{1}{15\Delta }}{\int }_{-{\displaystyle \frac{\Delta }{2}}}^{{\displaystyle \frac{\Delta }{2}}}{(e+{\displaystyle \frac{\Delta }{8}})}^{2}de+9\times {\displaystyle \frac{1}{15\Delta }}{\int }_{-{\displaystyle \frac{\Delta }{2}}}^{{\displaystyle \frac{\Delta }{2}}}{e}^{2}de.$$

(16)

Approximating that $V_{\mathrm{res}\_\mathrm{SAR}}$ follows a uniform distribution, its signal power can be calculated using

$$P_{signal}={\displaystyle \frac{1}{12}}{(8▵)}^2.$$

(17)

The accuracy that can be improved by the ISDM stage is

$${\displaystyle \frac{10lo{g}_{10}\frac{P_{signal}}{P_{noise}}}{6.02}}\approx 2.49.$$

(18)

Therefore, considering only the effect of $V2T$ non-linearity, when the non-linearity error reaches 13%, it can cause a 0.51-bit drop in the overall effective number of bits (ENOB). However, under the same PVT conditions, the non-linearity of the $V2T$ curve is much smaller than 13%. Thus, it is sufficient to control the impact of the VCM shift on the non-linearity of the $V2T$ curve. To maintain the VCM, the circuit we propose is introduced below.

4. Circuit Implementation

4.1. Modified MCS for CDAC

Ref. [23] used the monotonic switching procedure for the ISDM stage; however, this resulted in a single-sided voltage swing of ±8 LSB, which led to a VCM shift. As previously analyzed, this causes an inconsistency in the $V2T$ function across different quantization levels, which, in turn, leads to non-linearity. To maintain a constant VCM, this work presents a modified MCS approach.

Taking the switching of a 3-bit ADC as an example, the traditional MCS scheme [32] based on bottom-plate sampling is shown in Figure 10a. First, the input signal is sampled on the bottom plate of the DAC capacitor. Before the first comparison begins, the top plate of the DAC capacitor is disconnected from $VCM$, the bottom plate of the capacitor is switched to $VCM$, and the top plate of the capacitor regenerates the differential voltage for the first comparison. The voltages of $in$ and $ip$ are

$$V\left(in\right)\left[0\right]=2VCM-Vip,$$

(19)

$$V\left(ip\right)\left[0\right]=2VCM-Vin.$$

(20)

When $V\left(in\right)>V\left(ip\right)$, the bottom plate of the $2C$ capacitor at the $in$ terminal switches to the reference voltage $Vn$, while the bottom plate of the $2C$ capacitor at the $ip$ terminal switches to the reference voltage $Vp$. According to the conservation of charge, the voltages of $in$ and $ip$ at this time are

$$V\left(in\right)\left[1\right]={\displaystyle \frac{5}{2}}VCM-Vip,$$

(21)

$$V\left(ip\right)\left[1\right]={\displaystyle \frac{3}{2}}VCM-Vin,$$

(22)

and the total energy drawn from $VCM$ and $Vp$ during this process $0-t_1$ is

$$\begin{array}{cc}\hfill E_{0-t_1}& ={\int }_0^{t_1}{i}_{Vp}\left(t\right)Vpdt+{\int }_0^{t_1}{i}_{VCM}\left(t\right)VCMdt\hfill \\ \hfill & =-Vp·4C·\left[\right(V\left(in\right)\left[1\right]-Vp)-(V\left(in\right)\left[0\right]-VCM\left)\right]\hfill \\ & -VCM·4C·\left(V\right(in\left)\right[1]-V(in\left)\right[0\left]\right)-VCM·4C·\left(V\right(ip\left)\right[1]-V(ip\left)\right[0\left]\right)\hfill \\ & =C·V{p}^2.\hfill \end{array}$$

(23)

In this scheme, the bottom plate of the CDAC capacitor needs to switch between the input voltage and three reference voltages. This paper presents a modified MCS strategy. As shown in Figure 10b, each capacitor is split into two equal capacitors. During the reset phase, they are connected to the reference voltages $Vp$ and $Vn$, respectively, which is equivalent to connecting both capacitors to $VCM$. When $V\left(in\right)>V\left(ip\right)$, it only needs to connect one of the split capacitors at the $in$ terminal to $Vn$ and one at the $ip$ terminal to $Vp$ to achieve the same voltage conversion at the capacitor’s top plate. Two sets of D flip-flops control the switching of these capacitor bottom-plate switches. After being set/reset, their values are 1/0, respectively. Each set stores the comparator results and their complements, as shown in Figure 11. The four output signals—$QP$, $QPb$, $QN$, and $QNb$—respectively control the four capacitor switches for each bit in the SAR ADC stage.

The asynchronous clock is derived by feeding the comparator outputs to a NAND gate, and the inverter delay line to form a ring oscillator. The period of the comparator’s asynchronous clock is determined by the comparison time of the latch, the reset time, and the conversion time of the CDAC. The rising edge of the NAND gate output generates $E{N}_i$, which controls the register to store every bit.

Although this approach doubles the number of capacitors, it eliminates the need to maintain an additional reference voltage during the conversion phase. Moreover, it ensures that the comparator inputs remain at the common-mode level. The energy consumption is the same as the MCS approach.

4.2. Bootstrapped Switch

Due to the low supply voltage, a two-stage bootstrapping was employed for $Vgs$ to drive the sampling switch, as shown in Figure 12a. In this switch design, the primary types of leakage current considered are reverse-biased junction leakage $I_{junction}$, gate-induced drain leakage $I_{GIDL}$, and subthreshold leakage $I_{sub}$, as shown in Figure 12d. While the magnitudes of these leakage currents tend to decrease with a reduction in the gate-to-source voltage, it should be noted that the effect may vary depending on specific conditions. The inverter and capacitor on the right side reduce the voltage during the holding phase to less than 0 V, thus minimizing the effect of leakage currents.

When the clock is at a high level, the sampling switch is in the holding phase, and both bootstrapping capacitors $C_{boot1}$ and $C_{boot2}$ are charged to $U_0$. When the clock is at a low level, the sampling switch is in the track phase, and the initial voltage across the two capacitors in series is $2U_0$. The schematic is simplified in Figure 12b. If the three bootstrapping capacitors used in the circuit are of the same size $C_{boot}$, then the gate voltage $V_{boot}^{\prime }$ of the MOS transistor stabilizes, as shown in Equation (1), and at this point, $C_{down}$ is charged to $U_0$:

$$V_{boot}^{\prime }={\displaystyle \frac{C_{boot}}{2C_p+2C_g+C_{boot}}}2U_0.$$

(24)

In the subsequent clock cycle, when the clock is low, the sampling switch remains in the hold phase. As shown in Figure 12c, the top plate of $C_g$ + $C_p$ (gate capacitance and parasitic capacitance) is connected to the bottom plate of $C_{down}$, causing the gate node voltage of $M_2$ to transition to $V_{off}^{\prime }$:

$$V_{off}^{\prime }={\displaystyle \frac{-C_{boot}^2}{(2C_p+2C_g+C_{boot})(C_p+C_g+C_{boot})}}{U}_0.$$

(25)

During the holding phase, the source-to-drain voltages of $M_1$, $M_3$, and $M_4$ decrease to below 0 V. To prevent the substrate voltage from exceeding the source–drain voltage, as shown in Figure 12e, thereby avoiding the reverse breakdown of the PN junction between the source or drain and the substrate, $M_1$, $M_3$, and $M_4$ employ deep N-well NMOS transistors, with their substrates connected to the node Z with the lowest voltage. Post-simulation results show that during the hold mode with a sampled signal of 0.58 V, the improved bootstrapped switch reduced the voltage drop caused by leakage current from 19 µV to 2 µV compared with the traditional double-bootstrapped switch, as shown in Figure 13. The comparison of the bootstrapped voltages is shown in Figure 14. Figure 15 and Figure 16 compare the sampling linearity of the conventional double-bootstrapped switch and the improved bootstrapped switch. The improved switch achieved a 4 dB increase in the SFDR, with the ENOB improved from 13.8 bits to 14.2 bits, which resulted in a total enhancement of 0.4 bits.

Since our bottom-plate sampling ADC operates at a low supply voltage, the switch connecting $VCM$ to the top plate of the capacitor may not be turned on properly when controlled by the high level of $CLK$ at $VDD$. Therefore, we needed to raise the high voltage level of the synchronization clock to ensure proper control of the connection between $VCM$ and the capacitor top plate while maintaining the speed. The circuit diagram is shown in Figure 17a, where we adopted the principle of a double-bootstrapped switch to raise the high level of $CLK$ to $3VDD$. When $CLK$ is high, the two capacitors are charged to $U_0$, while $CLK\_out$ outputs 0. When $CLK$ transitions to low, $CLK\_out$ outputs $3VDD$. Figure 17b illustrates the switch used to connect VCM to the top plate of the DAC capacitor.

4.3. Comparator

As shown in Figure 18, the two-stage structure of the latch blocks the impact of kickback noise during the comparison. When $CLK$ is high, the comparison takes place. Upon completion, one output goes high while the other goes low. When $CLK$ transits to low, both outputs are reset to a high level. The outputs are fed into a NOR gate to generate the completion signal for the comparison/reset.

4.4. CDAC

The overall circuit of the DAC is depicted below and consists of two main parts: the DAC for the SAR ADC and the DAC for the ISDM ADC. Figure 4 illustrates the connection between the switch array and the capacitor array.

The layout of the capacitor array demands symmetry. Since the lower bits of the CDAC are more sensitive to capacitive mismatch, they are placed at the center of the CDAC layout. Although maintaining strict symmetry typically requires a centroid distribution, this approach can result in overly complex wiring. A one-dimensional symmetric distribution is employed in this design to reduce the wiring complexity. In this configuration, the lower capacitors are positioned centrally, while the higher capacitors are symmetrically arranged at the ends, surrounded by dummy capacitors. The layout of the input single-ended CDAC is illustrated in Figure 19.

The capacitor switch array consists of 23 combinations of capacitors and switches. In the SAR ADC, the capacitors serve dual purposes: during sampling, their bottom plates are connected to the input signal, and during conversion, they are connected to either the high or low level of the reference voltage, as mentioned in Section 2. In contrast, the capacitors in the ISDM ADC are used solely for digital-to-analog conversion.

The capacitor array’s design is based on static characteristics (INL, DNL), considering the capacitance mismatch provided by the process. The size of each individual cell is designed accordingly. On the other hand, the size of the switch array is designed based on timing requirements. Each unit capacitor is implemented with a 4 μm × 4 μm MIMCAP.

5. Measurement Results

After completing the layout design, parasitic parameters were extracted and post-layout simulations of the circuit were performed. This paper selected simulation results from three extreme process corners: SS (−40 °C), TT (27 °C), and FF (85 °C) for analysis. The simulation results, shown in

Table 1. The post-layout simulation results of the ADC (@VDD = 0.6 V, Fs = 10 kS/s).

	TT (27 °C)	SS (−40 °C)	FF (85 °C)
ENOB [bit]	12.03	11.79	12.3
SNDR [dB]	74.1	72.7	75.8
SFDR [dB]	86.3	82.2	88.5
Power [µW]	0.38	0.36	0.41

, were obtained at a power supply voltage of 0.6 V, with an input differential signal amplitude of 1.2 V, a frequency of 101 Hz, and a sampling frequency of 10 kS/s. Due to the presence of parasitic capacitance and resistance in the layout, the overall linearity of the ADC decreased compared with the pre-layout simulations, and the power consumption increased. In the SS process corner, the threshold voltage of the MOS transistors was relatively high, which resulted in a slower ADC conversion speed and poorer overall linearity compared with the TT process corner but with lower power consumption. In the FF process corner, the threshold voltage of the MOS transistors was lower, which led to a larger transconductance and higher current under the same input voltage, which resulted in a faster ADC conversion speed but higher power consumption.

The chip was fabricated using a 0.18 µm CMOS process, with microphotographs shown in Figure 20. The total chip area measured 1.04 mm², with a core area of 0.21 mm². To ensure stable power supply voltages and suppress noise and fluctuations on the power lines, decoupling capacitors that corresponded to digital and analog supplies were added on the upper and lower sides of the overall layout.

Figure 21 and Figure 22, respectively, show the measurement block diagram of our ADC and the photos of the on-site tests. The signal was generated by a high-linearity audio signal generator and fed into our ADC module through a single-ended to differential low-noise amplification circuit, with the clock generated by an arbitrary waveform generator. The ADC output was captured by an NI digital acquisition card and processed through MATLAB R2022a (Version 9.12) for the FFT transformation and dynamic/static analysis.

The chip-testing result shows that the 13-bit hybrid architecture ADC could operate with a minimum supply voltage of 0.575 V. At a supply voltage of 0.75 V, the sampling rate could reach 100 kS/s. Figure 23 shows the fast Fourier transform (FFT) spectrum of the ADC with a supply voltage of 0.6 V, input amplitude of 1.16 V, frequency of 101 Hz, and a sampling rate of 10 kS/s. The effective number of bits (ENOB) was 11.03 bits, the signal-to-noise and distortion ratio (SNDR) was 68.19 dB, the spurious-free dynamic range (SFDR) was 84.37 dB, and the total harmonic distortion (THD) was −81.69 dB. With a power consumption of 0.42 μW (2% for the sample and hold, 37% for the DAC, 42% for the ISDM, and 19% for the digital control), the figure of merit (FOM) used for comparison was calculated using the following formula:

$$FOM={\displaystyle \frac{Power}{2^{ENOB}\ast f_s}}.$$

(26)

Figure 24a illustrates the measured ENOB as a function of the input amplitude for the proposed 0.18 µm SAR ADC (with an input frequency of 101 Hz). The ENOB increased with the input amplitude, while the drop observed at 1.2 V was because the input signal exceeded the ADC’s full-scale range. Figure 24b shows the measured SNDR and SFDR versus the input frequency, demonstrating an SNDR of no less than 68.15 dB at a sampling rate of 10 kS/s.

Table 2. Performance comparison with the state-of-the-art ADCs.

	TCAS2 [24]	VLSI [33]	TCAS1 [34]	JSSC [23]	This Work
Process [nm]	40	14	180	90	180
ADC type	SAR–ISDM	NS-SAR	SAR	SAR	SAR–ISDM
Supply [V]	0.9	1.0	0.75	1.2	0.6 (min. 0.575 V)
$f_s$ [S/s]	50 M	400 M	10 k	50 M	10 k
Resolution [bit]	13	10	11	13	13
SFDR [dB]	72.2	81.2	72.0	85	84.4
SNDR [dB]	67.3	66.2	60.5	71	68.2
Power [µW]	2590	2800	0.25	4200	0.42
FOMw [fJ/conv.-s]	16.76	25.3	28.8	29.0	20.05

presents the test results of the designed ADC in this study compared with similar recent works. Our ADC exhibited high linearity and achieved high effective bits at lower supply voltages compared with other work, with the lowest FOM_W among similar architectures and accuracy in the same process. Ref. [24] employed a high-gain gated-delay oscillator; however, its SNR performance was degraded due to PCB-induced non-linearity. Ref. [33] utilized more comparisons to suppress the comparator noise, which resulted in increased power consumption. Ref. [34] adopted a pure SAR architecture to achieve high resolution, but its power consumption quadrupled for each additional bit of resolution. In our SAR–ISDM design, all building blocks operated in the subthreshold region, and thus, achieved a higher power efficiency in the 0.18 µm process. A high-linearity bootstrapped switch and a modified MCS scheme were employed to mitigate the non-linearity caused by the VCM shift, which achieved a high SNR.

Compared with JSSC [23], the large $V2T$ delay analyzed in Section 3 in the 0.18 µm process limited the maximum achievable sampling rate. The large transistors in the 0.18 µm process resulted in a higher parasitic capacitance, which led to increased power consumption, greater kickback noise, and more significant VCM shifts. Moreover, the VCM- and PVT-sensitive nature of the $V2T$ further degraded the performance. In addition, a 3-bit ISDM ADC and a 10-bit SAR ADC were employed in our design, whereas the work in JSSC [23] used a 2-bit ISDM and an 11-bit SAR ADC (plus 2-bit redundancy). The limited resolution and performance of the ISDM stage in our design constrained the overall ENOB. Therefore, implementing the proposed circuit in a more advanced process node is expected to yield higher speed, lower power consumption, and a potentially improved ENOB.

6. Conclusions

This paper presents a 13-bit 10 kS/s SAR–ISDM hybrid ADC designed in a TSMC 0.18 µm process. A thorough analysis of the non-linearities in the ISDM stage is given, and several techniques were employed to improve the linearity. The chip-testing results demonstrate that the proposed ADC achieved an ENOB of 11.03 under a supply voltage of 0.6 V, sampling frequency of 10 kS/s, and input signal frequency of 101 Hz. The power consumption was 0.42 µW, and the FOMw was 20.05 fJ/conv.-step. These results indicate that the ADC offers both high precision and low power consumption.

For future work, the impacts of PVT and VCM variations on non-linearity could be further mitigated through the implementation of advanced calibration techniques or digital compensation strategies, thereby further enhancing the robustness and performance of the ADC.