Novel Series-Parallel Phase-Shifted Full-Bridge Converters with Auxiliary LC Networks to Achieve Wide Lagging-Leg ZVS Range

Abstract

Under light load conditions, the phase-shifted full-bridge (PSFB) converter often has difficulty in realizing the zero-voltage switching (ZVS) of the lagging-leg by relying on the energy of its resonant inductor; however, for the series-parallel PSFB converter applied in high-power applications, the lagging-leg still has the problem of difficult realization of ZVS. Based on this, the paper analyzes the reasons why the series-parallel PSFB converter has difficulty in achieving ZVS for the lagging-leg under light and heavy loads. Under interleaved control, the ZVS of the lagging-leg over the full load range is realized by adding an auxiliary LC branch at the midpoint of the lagging-leg of both submodules. Based on the double-bridge input-parallel-output-series (IPOS) PSFB converter, analyzing the working principle of the circuit after adding the auxiliary LC branch and extending it to the series-parallel PSFB converter. The design requirements of the LC auxiliary branch of the dual-bridge series-parallel PSFB converter are given and the effects of the LC auxiliary branch on the module operating state and device stress are analyzed. On this basis, an extension is carried out to give the working principle and design method of the auxiliary LC branch of the N-bridge series-parallel PSFB converter. Finally, a 100 kW Matlab/Simulink simulation model verifies the superior performance of the proposed LC auxiliary branch to realize the lagging-leg ZVS of the series-parallel PSFB converter under light and heavy loads and achieves a 1.09% peak efficiency improvement at rated load.

1. Introduction

Nowadays, with the increasing depletion of fossil energy and the increasing prominence of global warming, clean energy exploitation and utilization, represented by wind, light, and tides, have received widespread attention [1]. As an important link in the conversion of electric energy, the performance of DC converter, such as reliability, efficiency, and power density, plays a key role in the highly efficient utilization of clean energy [2]. Increasing the switching frequency of a switching converter is an effective way to increase the power density of the converter [3,4]. However, for hard-switching pulse width modulation (PWM) converters, an increase in switching frequency means an increase in switching losses.

Zero-voltage switching (ZVS) phase–shifted full–bridge (PSFB) converter is a commonly used topology in medium and high-power applications [5,6,7]. The main attractive features are the ZVS of the primary switching tubes, the constant switching frequency, and the simplicity of control compared to the LLC resonant converter [8,9,10]. However, the traditional PSFB converter also has some problems. When the load of the converter is light or the primary resonant inductance is small, its lagging-leg is more difficult to realize ZVS, in addition, there is the loss of the secondary duty cycle, the parasitic oscillation of the rectifier diode, etc., which limits the application of the PSFB converter in many occasions [11,12,13].

When the PSFB converter is applied to high-power and high-voltage gain applications, its primary-side switching tubes and secondary-side rectifier diodes will be subjected to large current–voltage stresses [14]. The series-parallel combination of several basic PSFB converter modules is an efficient way to extend power capacity. The series-parallel PSFB converter is a system whose power capacity can be expanded by connecting the input and output terminals in series or parallel [15]. In addition, the reliability of the converter can be increased by using redundant modules [16]. According to the way of connecting the input side and output side, series-parallel combination converters can be categorized into four types, i.e., input-parallel-output-parallel (IPOP) converter, input-parallel-output-series (IPOS) converter, input-series-output-parallel (ISOP) converter, and input-series-output-series (ISOS) converter [17]. Each combination of converters has its characteristics and areas of application. IPOP converters can expand the power capacity of a system by connecting two sub-modules in parallel on the input and output side. IPOS converters not only allow for a larger power transfer but also for a higher output voltage gain [18].

Series-parallel PSFB converters are usually driven in a synchronous interleaved manner and have the common advantages of both conventional PSFB converters and series-parallel combination converters, making them widely used in areas such as energy storage, renewable power generation, and high-voltage pulse generators [19,20,21]. Also using vertical-double-diffused metal-oxide-semiconductor field-effect transistor power devices on the primary side makes the series-parallel PSFB converter more attractive [22,23]. However, each converter submodule in a series-parallel PSFB converter still suffers from the problems of a conventional PSFB converter, which also limits its use to some extent [24]. Based on this, many scholars have proposed many solutions. An ISOP PSFB converter with auxiliary LC branches to realize a wide zero-voltage switching range has been proposed in the literature [25]. The ZVS of all switching tubes is realized by adding LC auxiliary networks at the midpoints of the leading-legs and lagging-legs between neighboring submodules. However, this method changes the driving method of the conventional PSFB converter and fails to realize the interleaving between the submodules, which increases the peak-to-peak output voltage ripple in high-power application scenarios, thus increasing the size of the filtering components. In literature [26] a fully soft-switching wide conversion range shunt full bridge structure converter is proposed. The full soft-switching of the active switching tube is realized by sharing the leading-leg under the dual control modes of primary-side phase-shifting and secondary-side phase-shifting. Moreover, since the dual full-bridge converter shares the leading-leg, it increases the current stress of the leading-leg and the dual control modes will make the system design more complicated, which reduces the reliability of the system. Article [27] presents a parallel variable inductor ZVS PSFB converter. The variable inductor is connected in parallel with the main transformer to realize the ZVS of the switching tube by utilizing the energy of the variable inductor under full load. Because the variable inductor is connected in series with the transformer, the volt-second product of the variable inductor is equal to the amplitude-second product of the transformer’s primary voltage. In high power and high voltage gain application scenarios, there is a large circulating current loss and the design of the variable inductor is complicated.

Due to the increase in switching components in series-parallel PSFB converters, switching losses account for the majority of the total converter losses in medium and high-frequency converters. The efficiency of the module is greatly reduced when the ZVS of the switching transistor is not considered. The implementation strategy of the lagging-leg ZVS for a single PSFB converter submodule makes the system very complex and greatly reduces the reliability of the system. Based on this, the paper proposes a strategy to realize ZVS in the lagging-leg of a series-parallel PSFB converter. The auxiliary inductor is energized by adding an LC auxiliary circuit at the midpoint of the lagging-leg of the adjacent submodule, which makes use of the interleaving of switching tube driving signals between submodules. When the switching tube of the lagging-leg turns off, the auxiliary inductor and the resonant inductor are connected in parallel to resonate with the junction capacitance of the switching tube of the lagging-leg to realize the charging and discharging of the junction capacitance. It solves the problem that it is difficult to realize ZVS for lagging-leg switching tubes under light load conditions. When the input voltage is high or the resonant inductor is small, the primary current of the transformer drops to zero before the drive signal of the lagging-leg arrives, resulting in the anti-parallel diode of the switching tube of the lagging-leg cutting off and the ZVS of the lagging-leg cannot be realized; however, when the switching tube of the lagging-leg is turned off, the auxiliary inductance is connected in parallel with the resonant inductor, so as long as the current of the resonant inductor does not go to zero before the drive signal arrives, the ZVS of the lagging-leg is guaranteed to be realized.

2. Working Principle of ZVS Series-Parallel PSFB Converter

The series-parallel PSFB converter is mostly used in medium and high-power applications, and its structure is shown in Figure 1. The differences in parasitic parameters between submodules for medium and high-power applications have a small impact on the performance of the converter, so the series-parallel PSFB converter submodules are often driven by interleaved synchronization as shown in Figure 2. In this driving mode, different sub-modules having the same duty cycle can not only realize the natural equalization of input current and output voltage between sub-modules, simplify the design of the control loop, and improve the reliability of the system, but also improve the input and output voltage and current ripple frequency and reduce the volume of input and output filtering components.

When the difference in parasitic parameters between series-parallel PSFB converter submodules is not considered, the input voltage of each submodule should be equal. To enable the lagging-leg to realize ZVS at light loads and higher input voltages, an LC passive auxiliary network can be connected between the midpoints of the lagging-legs of the series-parallel PSFB converter sub-modules in the interleaved driving mode.

Take the IPOS PSFB converter as an example to introduce the realization of the lagging-leg ZVS. The IPOS PSFB converter module is composed of two PSFB converter sub-modules connected in series via inputs in parallel with outputs. The main circuit of the IPOS PSFB converter after adding the LC auxiliary circuit is shown in Figure 2a. The addition of the auxiliary LC branch does not affect the working process of the IPOS PSFB converter, and the working principles of submodules M₁ and M₂ are the same as those of the conventional PSFB converter. The main waveforms of the IPOS PSFB converter are shown in Figure 2b after the addition of the auxiliary LC branch under interleaved driving.

In Figure 3a, S_1-S₄, S_5-S_8, D_R1-D_R4, and D_R5-D_R8 form the inverter H-bridge and rectifier H-bridge of the sub-modules M₁ and M₂, respectively. L_r1 and L_r2, C_b1 and C_b2, i_p1 and i_p2, and V_o1 and V_o2 are the resonance inductance (or transformer leakage inductance), the isolation capacitance, the primary-side currents, and the output voltages of the sub-modules M₁ and M₂, respectively. V_in and C_in are the input voltage and input capacitance of the IPOS PSFB converter. L_f1, L_f2, C_f1, C_f2, i_Lf1, i_Lf2, V_o1, V_o2, V_rect1, V_rect2, and R_L are the filter inductors, filter capacitors, currents flowing through the filter inductors, output voltages, the rectified output voltages, and load resistors of the submodules M₁ and M₂, respectively. L_au, C_au, v_EF, and i_au are the inductance and capacitance of the auxiliary branch, the voltage across the auxiliary branch, and the current flowing through the auxiliary branch, respectively.

As shown in Figure 2b the duty cycles of all switch tubes S₁-S₈ are 50%, the phase angle differences of the diagonal switch tubes of submodules M₁ and M₂ are δ, and the driving signals of the corresponding switch tubes of submodule M₂ lag behind the driving signals of the corresponding switch tubes of submodule M₁ by 90° or T_s/4. Utilizing full-bridge diode rectification, the ripple frequency of V_o1 and V_o2 is two times the switching frequency. In addition, the ripple of the output voltage V_o is 4f_s of the switching frequency because the submodule uses interleaved drive signals.

Due to the symmetry of the control method, the converter exists in 12 operating modes with positive and negative half-cycle symmetry during one switching cycle. The following section focuses on analyzing the operation of the ZVS IPOS PSFB converter during half a cycle of the [t₀-t₇] period.

Assumptions are made for analytical convenience as follows [28]:

• The module works in a steady state;
• Switching tubes S₁-S₈ and diodes D_R1-D_R8 are ideal devices;
• Switch tubes S₁-S₈ parasitic capacitance C₁ = C₂ = --- = C₈ = C_r;
• Transformer T_r1, T_r2, inductors L_r1, L_r2, L_f1, L_f2, L_au and capacitors C_in, C_f1, C_f2, C_au are ideal devices, and L_r1 = L_r2, L_f1 = L_f2, and C_f1 = C_f2.

a.

Mode 0 [t₀-t₁]:

At the moment t₀, the switching tubes S₁ and S₄ of the submodule M₁ are on, the primary current i_p1 increases to equal the converted value of the secondary current ni_lf1, and the diodes D_R2 and D_R3 are subjected to a counter voltage and turn off. The input power supply V_in charges the capacitor C_f1 through the submodule M₁ while transferring energy to the load. The current i_Lf1 flowing through the filter inductor L_f1 increases linearly to the value of:

$$i_{L\mathrm{f}1}(t)=i_{L\mathrm{f}1}(t_0)+\frac{n{V}_{in}-V_{o1}}{n^2{L}_{r1}+L_{\mathrm{f}}}(t-t_0)$$

(1)

The primary-side current of sub-module M₁ equal to the converted value of the filter inductor current also increases linearly.

For sub-module M_2, the primary side switching tubes S₆ and S₇ and the secondary side rectifier diodes D_R6 and D_R7 are in conduction. The primary energy is reflected to the secondary side by transformer T_r2, charging C_f2 and providing energy to the load. The current i_Lf2 flowing through the filter inductor L_f2 increases linearly with a value of:

$$i_{L\mathrm{f}2}(t)=i_{L\mathrm{f}2}(t_0)+\frac{n{V}_{in}-V_{o2}}{n^2{L}_{r2}+L_{\mathrm{f}}}(t-t_0)$$

(2)

The primary-side current of submodule M₂ is equal to -ni_Lf2 linearly decreasing.

As the switching tubes S₄ and S₆ conduct, the voltage v_EF across E and F is a lower positive and upper negative V_in, and the current i_au flowing through L_au is:

$$i_{au}(t)=i_{au}(t_0)-\frac{V_{in}}{L_{au}}(t-t_0)$$

(3)

The i_au decreases linearly and then increases inversely.

b.

Mode 1 [t₁-t₂]:

Turning off S₇ at the moment of t₁, the direction of the primary current i_p2 of the sub-module M₂ is unchanged due to the renewal of the primary resonant inductor L_r2. i_p2 is transferred from S₇ to the C₅ and C₇ branches, discharging C₅ and charging C₇. When the C₅ discharge is over, D₅ conducts and renews the current, after which switching tube S₅ can be opened to realize ZVS when D₅ or S₅ conducts the primary and secondary voltages of transformer T_r2 are clamped to zero, and the rectifier diodes of sub-module M₂ all conduct and renew the current. Since the switching state of switching tubes S₁-S₄ is unchanged, the operating state of submodule M₁ is the same as mode 0. At this time, the filter capacitor C_f1 is in the charging state C_f2 is in the discharging state.

Switch tubes S₄ and S₆ are in conduction and i_au increases inversely.

c.

Mode 2 [t₂-t₃]:

When S₆ is turned off at t₂, the direction of i_au is unchanged due to the auxiliary inductor L_au, and L_au and L_r2 resonate with C₆ and C₈ together. The i_au is transferred from S₆ to C₆ and C₈ branches, discharging C₈ and charging C₆. When C₈ is discharged, D₈ conducts to continue current, and v_EF is clamped to zero. Thereafter, switch S₈ is turned on to realize ZVS. When C₈ discharge is over, D₈ conducts to continue the current, v_EF is clamped to zero, i_au is unchanged, and thereafter, turning on the switch S₈ can realize ZVS. Due to the D₈ continuing to conduct, the input voltage is all added to the resonant inductor L_r2, and the primary current i_p2 of the sub-module M₂ is first linearly reduced and then inversely increased with a value of:

$$i_{p2}(t)=i_{p2}(t_2)+\frac{V_{in}}{L_{r1}}(t-t_2)$$

(4)

The state of submodule M₁ is the same as that of mode one. The sub-module M_2′s secondary rectifier diode continues to conduct and renew the current.

d.

Mode 3 [t₃-t₄]:

At the moment, t₃, the primary current i_p2 of the submodule M₂ is equal to the converted value of the secondary current ni_lf2, and the diodes D_R5 and D_R8 are subjected to a back-voltage and turned off. The input power V_in charges the capacitor C_f2 through the submodule M₂ and transfers energy to the load. Since the state of the inverter bridge arm switching tube of submodule M₁ remains unchanged, the operating state of submodule M₁ is the same as that of mode two. The current i_Lf2 flowing through the filter inductor L_f2 is:

$$i_{L\mathrm{f}2}(t)=i_{L\mathrm{f}2}(t_3)-\frac{n{V}_{in}-V_{o2}}{n^2{L}_{r2}+L_{\mathrm{f}}}(t-t_3)$$

(5)

The filter inductor current increases linearly, and the primary side current i_p2 of sub-module M₂, which is equal to the converted value of the filter inductor current, also increases linearly.

Switch tubes S₄ and S₈ conduct, the voltage v_EF across E and F is clamped to zero, and i_au is essentially unchanged.

e.

Mode 4 [t₄-t₅]:

Turning off S₁ at the moment of t₄, the direction of the primary current i_p1 of the submodule M₁ remains unchanged due to the renewal of the primary resonant inductor L_r1. The i_p1 is transferred from S₁ to the C₁ and C₃ branches, discharging C₃ and charging C₁. When the end of C₃ discharge, D₃ conduction renewal, and turning on the switch S₁ can realize ZVS. Due to the D₃ conduction renewal, transformer T_r1 primary and secondary side voltage is clamped to zero, D_R1-D_R4 all conduction renewal. Submodule M₂ operates in the same state as mode 3.

f.

Mode 5 [t₅-t₆]:

When S₄ is turned off at t₅, the direction of i_au is unchanged due to the continuity of the auxiliary inductor L_au, L_au, and L_r1 resonate together with C₂ and C₄, and i_au is transferred from S₄ to the C₂ and C₄ branches, discharging C₂ and charging C₄. When C₂ discharge is over, D₂ conducts to renew the current, after which switch S₂ can be turned on to realize the ZVS. Due to the D₂ renewed conduction, the input voltage is all added to the resonant inductor L_r1, and the primary current i_p1 of the sub-module M₁ first decreases linearly, and then increases inversely with a value of:

$$i_{p1}(t)=i_{p1}(t_5)-\frac{V_{in}}{L_{r1}}(t-t_5)$$

(6)

Since the switching tube state of submodule M₂ is unchanged, the operating state of M₂ is the same as that of mode 4.

Since the switching tubes S₂ and S₈ are on, the voltage v_EF across E and F is V_in which is positive up and negative down, and the current i_au flowing through L_au is:

$$i_{au}(t)=i_{au}(t_5)-\frac{V_{in}}{L_{au}}(t-t_5)$$

(7)

The i_au decreases linearly.

At the moment, t₆, the primary side current i_p1 of the submodule M₁ is equal to the converted value of the filter inductor current, ni_Lf1, and the converter enters into the next half-cycle, which works similarly to that of the first half-cycle.

The equivalent circuit of the ZVS IPOS PSFB converter operating mode is shown in Figure 3.

From the operating principle of the ZVS IPOS PSFB converter, it is clear that when the input voltage is determined, the energy of the auxiliary inductor is only related to the interleaving time between submodules and the size of the auxiliary inductor but not to the state of the load and the size of the resonant inductor. For the series-parallel PSFB converter under interleaved control, regardless of whether the input ports of the sub-modules are connected in parallel or series, the energy balance of the auxiliary LC branch in one cycle can be guaranteed by ensuring that the input voltage of each sub-module is of equal magnitude, and thus the strategy applies to all four combining forms of the series-parallel PSFB converter.

3. Series-Parallel PSFB Converter ZVS Condition and N-Bridge Extension

3.1. Series-Parallel PSFB Converter ZVS Condition

The primary resonant inductor makes the rising and falling edges of the primary current of the PSFB converter have a finite slope causing the loss of the secondary duty cycle. The expression for the output voltage V_o of a conventional PSFB converter can be written as:

$$V_o=n{V}_{in}{D}_{eff}$$

(8)

where D_eff is the effective duty cycle of the secondary side.

As illustrated in Figure 2b, the leading-leg switching tubes of each submodule are turned on or off when the primary-side current reaches its maximum value. At this time, the equivalent value of the filter inductor L_f at the primary side is involved in the resonance of the switching tube section capacitance together with the primary side resonant inductor to complete the charging and discharging of the upper and lower bridge arm capacitors. Before turning on, the leading-leg switching tube allows its anti-parallel diode natural conduction. Due to the conduction of the switching tube anti-parallel diode, the output voltage of the inverter H-bridge is clamped to zero, and the magnitude of the primary current is almost unchanged, which ensures that the switching tube anti-parallel diode is in the conduction state when the drive signal of the leading-leg arrives, and thus the ZVS of the switching tube of the leading-leg can be guaranteed. Therefore, the ZVS of the leading-leg can be realized by the resonant inductance of the circuit or the transformer leakage inductance without the need for additional auxiliary circuits.

To realize the ZVS of the switching tube of the leading-leg, there must be enough energy to draw out the charge of the shunt capacitors at both ends of the switching tube that is about to turn on, and to complete the charging of the shunt capacitors at both ends of the switching tube that is about to turn off in the same bridge arm. To realize the ZVS of the leading-leg switching tube, it is necessary to satisfy:

$$\frac{1}{2}(L_r+L_f)I_p^2\ge C_i{V}_{in}^2$$

(9)

where I_p is the peak value of the current flowing through the primary resonant inductor and its value is:

$$I_p=\frac{V_{oi}{T}_s(1-D_{eff})+4L_f{I}_o}{4L_{\mathrm{f}}}$$

(10)

As demonstrated in Figure 2b, the primary side current I_p is almost constant during the switching process of the leading-leg. Since the filter inductor is generally large, the energy stored in the original resonant inductor and the filter inductor can help the leading-leg to realize ZVS under the condition that the dead time meets the requirement, and thus, the leading-leg can realize ZVS over a wide load range.

Each sub-module of the series-parallel PSFB converter realizes the ZVS of the lagging-leg in the same way as the conventional PSFB converter. Therefore, the series-parallel PSFB converter is mainly concerned with the ZVS of the lagging-leg.

Unlike the ZVS of the leading-leg, when the lagging-leg switching tube is turned off, the primary and secondary sides of the transformer are uncoupled, and only the primary resonant inductor resonates with the junction capacitance of the lagging-leg switching tube. Therefore, to realize the ZVS of the lagging-leg, there must be enough energy to pump away the charge of the shunt capacitance at both ends of the switching tube that will be turned on and complete the charging of the shunt capacitance at both ends of the switching tube that will be turned off in the same bridge arm. However, the primary resonant inductor is generally very small, and when the load is light, the energy of the primary resonant inductor is not enough to realize the charging and discharging of the junction capacitors of the switching tubes in the lagging-leg. At the same time, when the input voltage of the series-parallel PSFB converter is high and the resonant inductance is small, the primary current of the transformer drops to zero before the driving signal of the switching tube of the lagging-leg arrives, and the anti-parallel diode of the switching tube cuts off so that the lagging-leg is unable to realize ZVS.

The auxiliary LC branch can not only realize the charging and discharging of the junction capacitance of the lagging-leg switching tube together with the resonant inductor when the lagging-leg switching tube is off but also renew the current through the anti-parallel diode after the anti-parallel diode of the lagging-leg switching tube conducts, which is a very good solution to the two problems that it is difficult for the lagging-leg to realize the ZVS in light loads and when the input voltage is high. Thus, ZVS of the lagging-leg can be realized over the full load range. According to the analysis of the operating principle of the IPOS PSFB converter with LC auxiliary branch in Section 2, the voltage and current waveforms of the auxiliary LC branch can be shown in Figure 4.

The maximum value of the auxiliary inductor current, I_aumax, can be seen in Figure 4.

$$I_{aumax}=\frac{V_{in}{T}_s}{8L_{au}}$$

(11)

I_aumax is only related to the staggering time between submodules, the input voltage, and the size of the auxiliary inductor. To realize the ZVS of the lagging-leg of a series-parallel PSFB converter, it is only necessary to ensure the following three items:

(1) The energy of the auxiliary inductor should be greater than the minimum energy required to complete charging and discharging of the junction capacitance of the switching tube i.e., L_au should be satisfied

$$L_{au}\le \frac{T_s^2}{128C_j}$$

(12)

(2) The drain-source pole parasitic capacitance of the lagging-leg switching tube needs to finish charging and discharging during the dead time, and the auxiliary circuit current cannot be reversed during the dead time, both to ensure

$$\frac{16C_j{L}_{au}}{T_s}\le t_{d,lagging}\le \frac{T_s}{8}$$

(13)

(3) To ensure that there is no DC bias current in the auxiliary circuit, an isolation capacitor C_au is connected in series with the auxiliary circuit to ensure that the resonant frequency of the auxiliary circuit is less than 1/5 of the switching frequency.

$$C_{au}\ge \frac{1}{{(\frac{2\pi }{5T_s})}^2{L}_{au}}$$

(14)

When the difference in parasitic parameters between the sub-modules of the series-parallel PSFB converter is not considered, the input voltage of each sub-module should be equal. Therefore, the series-parallel PSFB converter with the addition of the auxiliary circuit LC has the same operating principle as the main circuit and the same operating state of the auxiliary circuit as the IPOS PSFB converter. Therefore, this strategy is applicable in all four series-parallel PSFB converters under interleaved synchronous drive.

For a series-parallel PSFB converter composed of two PSFB converter submodules, due to the staggered 90° driving method between the submodules, it can be seen from Figure 4 that the current i_au flowing through the LC branch is symmetrical about the zero point of the current, and the average value of the current flowing through the LC branch in each switching cycle in the ideal case is zero. From the working process of the LC branch in Section 2, it can be seen that in one switching cycle, the flow path of current i_au does not pass through the transformer’s primary edge. Therefore, the energy stored in the LC branch is not reflected to the secondary side via the transformer but is all fed back to the input power supply. Thus, the LC branch does not transfer energy to the secondary edge nor does it exacerbate the parasitic oscillations of the secondary diode. For the primary side of the transformer, i_au only flows through the lagging-leg and flows through the same switching tube or anti-parallel diode as the primary side of the transformer, so this does not exacerbate the voltage spikes of the switching tube. In addition to this, the auxiliary inductor should be designed to minimize the current in the LC network by taking into account the dead time and the input voltage.

To further analyze the efficiency improvement of IPOS phase-shifted full-bridge converter lagging-leg realizing ZVS versus not realizing ZVS, at a rated power of 100 kW, a loss analysis is conducted under various working conditions after determining the main circuit parameters. The losses of each component in the module are shown in

Table 1. Component Loss Table at Different Input Voltages for Rated Power.

	Input Voltage (V)	205	240	280	320
Loss Type (W)
Switch tube on-state loss		427.63	359.64	311.62	342.06
Switch tube opening loss		697.00	816.00	952.00	1088.00
Switch tube turn-off loss		1312.00	1536.00	1792.00	2048.00
Transformer iron loss		276.00	299.16	328.00	351.12
Transformer copper loss		98.74	96.36	92.10	87.70
Rectifier diode on-state loss		396.48	408.00	418.40	426.00
Rectifier diode turn-off loss		19.20	23.84	32.26	38.00
Filter inductance copper loss		24.25	24.25	24.25	24.25
Filter inductance iron loss		5.00	5.00	5.00	5.00

, and the efficiency and efficiency difference curves of the lagging-leg realizing ZVS and the non-realized ZVS module at input voltages of 205 V-320 V are shown in Figure 5. Figure 5 shows that the higher the input voltage, the lower the efficiency because of the increased switching losses in the active switch and iron losses in the transformer. It can also be seen that the percentage difference in efficiency between the lagging-leg achieving zero-voltage turn-on and not achieving zero-voltage turn-on increases gradually as the input voltage increases the percentage efficiency difference is 1.09 when the input voltage is 320 V. That is to say, realizing zero voltage turn-on of the lagging-leg improves the efficiency more when the input voltage is higher.

3.2. Implementation of Lagging-Leg ZVS for N-Bridge ZVS Series-Parallel PSFB Converter

N PSFB converter submodules are usually combined in series-parallel to meet higher power demands. The concept of lagging-leg ZVS for a series-parallel PSFB converter realized by a dual-bridge LC auxiliary branch can be extended to a series-parallel PSFB converter composed of N submodules. Figure 6 shows a circuit topology consisting of three PSFB converter submodules passing through IPOS. To realize the ZVS of the lagging-leg switching tubes of each PSFB converter submodule, the topology adds two auxiliary LC branches with identical parameters at the midpoints of the lagging-legs of the neighboring submodules.

In a series-parallel PSFB converter consisting of n PSFB converter submodules, the interleaving angle of the corresponding switching tubes between two neighboring submodules should be π/n. So, in a series-parallel PSFB converter consisting of three PSFB converter submodules, the interleaving angle between two neighboring modules should be π/3.

From Figure 4, it can be seen that the auxiliary inductor current varies linearly throughout the staggered angle and is renewed when the corresponding switching tubes of the lagging-legs turn on at the same time between neighboring submodules. For a series-parallel PSFB converter consisting of n submodules, the maximum value of the auxiliary inductor current I_aumax,n is

$$I_{aumax,n}=\frac{V_{in}{T}_s}{4n{L}_{au}}$$

(15)

When the size of the auxiliary inductor is constant, it can be seen from (15) that the maximum value of the auxiliary inductor current is smaller as the number of series-parallel PSFB converter submodules increases. This is not difficult to understand because the auxiliary inductor only obtains energy from the input power supply during the interleaving time, and the interleaving angle becomes smaller as the number of series-parallel PSFB converter sub-modules increases. Therefore, to be able to realize the ZVS of the lagging-leg, the auxiliary inductance should be smaller as the number of series-parallel PSFB converter sub-modules increases. For a series-parallel PSFB converter consisting of n PSFB converter submodules, the size of the auxiliary inductance L_au should be satisfied

$$L_{au}\le \frac{T_s^2}{32n^2{C}_j}$$

(16)

From Figure 6 and the realization of the lagging-leg ZVS with the addition of the auxiliary circuit, it can be seen that for a series-parallel combined converter consisting of N PSFB converter sub-modules, the current flowing through the lagging-leg of the intermediate module is twice as much as that of the first sub-module and the Nth sub-module when N ≥ 3, which leads to a higher conduction loss.

For high-power converter applications, the number of submodules of the series-parallel converter must be determined to balance component stress, efficiency, cost, and power density. After performing this analysis and determining the number of submodules of the series-parallel combined PSFB converter, the optimal combination of series-parallel PSFB converter topologies can be selected. The double bridge topology provides the best cost and performance tradeoffs and is, therefore, more widely used.

4. Simulation Results and Discussion

To validate the series-parallel PSFB converter lagging-leg ZVS strategy, a two-bridge 100 kW ZVS IPOS PSFB converter is modeled by the Matlab/Simulink simulator as shown in Figure 7 and Figure 8, and its model parameters are shown in

Table 2. System Simulation Parameters.

Parameters	Value
Input voltage Vin	205 V–320 V
Output voltage Vo	2000 V
Transformer ratio 1:n	1:6
Resonant inductance Lr	1 μH
Junction capacitance Cj	680 pF
Filter inductance Lf	1 mH
Filter capacitor Cf	40 μF
Switching frequency fs	15 kHz
Isolation capacitor Cb	0.416 mF
Dead time td	1.2 μs
Auxiliary inductor Lau	30 μH
Auxiliary capacitor Cau	100 μF
Rated power Pn	100 kW

. In the simulation, the controller is controlled by a single voltage loop, and a Proportional Integral (PI) controller is used to balance the output voltage. The control parameters of the PI controller are K_p = 0.0001 and K_i = 0.3.

4.1. Simulation Results under Rated Load for an Input Voltage of 320 V

To analyze the reason for the difficulty in achieving ZVS for the lagging-leg at high input voltage and rated load, the steady-state analysis of the ZVS IPOS PSFB converter is implemented when the input voltage is 320 V at a rated load with 40 Ω load resistance. The driving voltage waveforms of the module are given in Figure 9, from top to bottom, the driving signals of the switch tubes S₁ and S₃ above and below the same bridge arm of the module, the driving signals of the corresponding switch tubes S₁ and S₅ between the sub-modules, and the driving signals of the diagonal switch tubes S₁ and S₄ under the rated power at the input voltage of 320 V. The output voltage and current waveforms are shown in Figure 10 with V_o = 2000 V and I_o = 50 A at steady state.

Figure 11 gives the realization of ZVS of the submodule M₁ lagging-leg switch tubes S₂ and S₄ before the addition of the auxiliary LC branch at an input voltage of 320 V and a resonant inductance of 1μH Figure 12 shows a partial enlargement of Figure 11. From Figure 12, it can be seen that the drain and source voltages V_ds-S₂ of the switching tube S₂ decrease to zero and then return to the input voltage before the arrival of the gate and source signals V_gs-S₂ and the ZVS of the lagging bridge-arm switching tube is not realized. The reason for not realizing ZVS for the lagging-leg is precisely the fact that the transformer primary current drops to zero before the drive signal for the switching tube of the lagging-leg arrives causing the switching tube’s anti-parallel diode to cut off.

Figure 13 shows the voltage v_EF, current i_au of the auxiliary branch, and the driving voltage of the lagging bridge switch tubes of submodules M₁ and M₂ after adding the auxiliary inductor, and the maximum value of i_au is 88 A when V_in = 320 V and L_au = 30 mH. The waveforms of drain-source voltage and gate-source voltage of the lagging bridge switch tubes S₂ and S_4, after adding the auxiliary inductor under the same working condition, are shown in Figure 14. It can be seen that the drain-source voltage has dropped to zero before the arrival of the drive signal of S₂, thus realizing the ZVS of the craggy switching tube afterward.

4.2. Simulation Results under Light Load for an Input Voltage of 320 V

To analyze the reason for the difficulty in achieving ZVS in lagging-leg under light load, and comparison of achieving ZVS in lagging-leg with LC auxiliary branch under light load and rated load, the same simulation is completed at an input voltage of 320 V and 5 kW load. Figure 15 shows the waveforms of the drive signals of switch tubes S₁ and S₃ above and below the same bridge arm at a load of 5 kW, the drive signals of the corresponding switch tubes S₁ and S₅ between the submodules, and the drive signals of the diagonal switch tubes S₁ and S₄ at a rated power with an input voltage of 320 V, while the other conditions remain unchanged. Under the same input and output voltages, the phase angle difference between switch tubes S₁ and S₄ in Figure 15 is significantly larger than that in Figure 9, which is because the primary current of the transformer is significantly reduced under light load, thus reducing the loss of the primary duty cycle. The output voltage and current waveforms are shown in Figure 16, with V_o = 2000 V and I_o = 2.5 A at steady state.

Figure 17 shows the realization of ZVS by the submodule M₁ lagging-leg switch tubes S₂ and S₄ before the addition of the auxiliary LC branch at an input voltage of 320 V and a resonant inductance of 1μH under light load conditions. Figure 18 shows a partial enlargement of Figure 17 from Figure 18, it can be seen that the drain and source voltages V_ds-S₂ of switch S₂ maintain the input voltage unchanged until the arrival of the gate and source signals V_gs-S₂ and the ZVS of the lagging bridge switching tubes is not realized. The reason why the lagging-leg does not realize the ZVS under the light-load condition is that the energy of the resonant inductor is not enough to realize the charging and discharging of the junction capacitance of the switching tubes of the lagging-leg.

The voltage and current waveforms of the submodules M₁ and M₂ lagging-leg switching tubes and auxiliary branches are shown in Figure 19. From Figure 13 and Figure 19 it can be seen that the voltage v_EF and current i_au of the auxiliary branch under light load are the same as those under rated load, which also verifies that v_EF and i_au are only related to the input voltage, interleaving time, and the size of the auxiliary inductance, but not the size of the load. As can be seen from Figure 20, the lagging bridge-arm switching tube also realizes ZVS after adding the auxiliary LC branch under light load conditions.

4.3. Comparative Study

Figure 21 gives the ISOP PSFB converter proposed in the literature [25] that possesses auxiliary LC networks to widen the ZVS range. The converter realizes the ZVS of all switching tubes by adding two auxiliary LC networks at the midpoints of the leading and lagging bridge arms of the neighboring submodules, and the scheme cleverly uses the interleaving of drive signals between submodules to make the energy of the auxiliary inductors vary with the duty cycle of the primary side.

Compared with the scheme presented in this paper, the drive signals of sub-modules M₁ and M₂ in this scheme are interleaved by 180 degrees, which increases the peak-to-peak input and output capacitance ripple. The series-parallel PSFB converter is mostly used in high-power scenarios, where the leading-legs can rely on the energy of the resonant inductor to realize the ZVS, and the two sets of LC auxiliary networks not only increase the circulating current loss but also reduce the power density of the module.

5. Conclusions

Aiming at the problem that the lagging-leg of a series-parallel PSFB converter is difficult to realize ZVS in high-power applications, the paper analyzes the reasons why the lagging-leg of a series-parallel PSFB converter is difficult to realize ZVS in light and heavy loads, and then proposes a strategy of adding auxiliary LC branch to realize ZVS in the full-load range with the interleaved control. This strategy achieves the ZVS of the lagging-leg independent of the states of load and input voltage by utilizing the interleaving of drive signals between submodules to energize the auxiliary LC branch. The following conclusions can be drawn from the analysis of the 100 kW simulation model under light and heavy loads:

(1) The auxiliary LC branch can be connected in parallel with the resonant inductor to realize the charging and discharging of the junction capacitance of the lagging-leg switching tube when the lagging-leg switching tube is turned off. This solves the problem that the energy of the resonant inductor is not enough to charge and discharge the junction capacitor of the lagging bridge switch under light loads.

(2) When the bridge arm switching tube is turned off afterward, the auxiliary LC branch is connected in parallel with the resonant inductor, and the ZVS of the lagging-leg switching tube can be realized during the dead time of the lagging-leg as long as the current of the auxiliary LC branch is not zero and is not reversed. It solves the case where the resonant inductor is too small at high input voltage causing the transformer primary current to drop to zero before the end of the dead time and causing the anti-parallel diode to cut off before the arrival of the drive signal of the lagging-leg.

(3) Compared with the traditional ZVS realization strategy for PSFB converter lagging bridge-arm switching tubes, for the two-bridge series-parallel PSFB converter this strategy only requires a set of passive LC auxiliary branches to realize the ZVS of the lagging bridge-arm four switching tubes, which significantly improves the reliability and power density of the system.

The implementation strategy proposed in this paper to realize the ZVS of the lagging-leg of a series-parallel PSFB converter can realize the ZVS of the lagging-leg in the full load range. However, the addition of an LC auxiliary branch at the mid-point of the lagging-leg increases the circulating current loss. Therefore, a switching device with a larger current stress should be selected for practical applications.