A Hysteresis Current Controller for the Interleaving Operation of the Paralleled Buck Converters Without Interconnecting Lines

Abstract

Paralleled buck converters have garnered significant attention for fulfilling the increasing demands of power supplies in modern applications. They have the advantages of increased current capacity and reduced current ripple. Under this architecture, applying distributed control brings the benefits of reliability and scalability. However, the interconnecting lines between the converters are required for achieving the interleaving operation, which reduces the reliability and scalability. To eliminate the interconnecting lines, this paper proposed a hysteresis current controller to achieve the symmetric interleaving operation. First, the parallel structure with a common output filter was proposed to provide the hardware basis for the proposed control method. Then, the hysteresis current controller was constructed based on the inductor voltage of each buck module to achieve the interleaving operation. The experiment of the three-module-paralleled buck converter was conducted. The experimental results show that the symmetric interleaving was achieved with a maximum phase shift error of 4.1%; the output of the parallel system can recover within 2.60 ms after the load transitions from 50% to 100%; and the parallel system can recover within 1.96 ms after one module removal. The simulation results of the six-module-paralleled buck converter show that the parallel system can recover within 1.00 ms after one module addition, which illustrates the scalability of the proposed method.

1. Introduction

The buck converter is one of the most popular topologies for voltage step-down applications [1,2]. The buck converter typically consists of a switching network (a switch and a diode, or two switches) and a filter (an inductor and a capacitor), and the output voltage can be adjusted by the pulse width modulation (PWM). Due to the simple structure, low cost, and high reliability, buck converters have been applied in many applications. For example, servers [3], microgrids [4], and electric vehicles [5] utilize a buck converter as the front-end stage to pre-regulate the voltage to a suitable level [6], and AI engines (Artificial Intelligence Engines) also require buck converters to supply a regulated voltage [7]. However, a single buck converter may struggle to meet high current demands, and thus, several buck modules in parallel are required to share the total current and reduce the total current ripple [7,8,9,10].

The modular structure of paralleled buck converters is well suited for implementing distributed control. In contrast to centralized control, the distributed control disperses the control function into local controllers located within each module. The local controllers cooperate with each other to achieve the coordination and optimization of the paralleled system, and the exit of a module will not affect the operation of the entire system. Therefore, the distributed control methods can enhance the reliability and scalability of the paralleled system [11,12]. Furthermore, the expansion of the parallel converter may bring challenges to stability. However, the stability can be analyzed with an electromagnetic transient simulation platform, e.g., MATLAB Simulink, and frequency-domain stability analysis methods, e.g., impedance-based modeling method [13,14,15]. In addition, the stability can be enhanced according to the results of a simulation or sensitivity analysis to ensure that the system can operate stably after expansion. Therefore, the parallel converters with the distributed control methods have been widely used in microgrids [16,17], traction systems [18,19], etc. However, to achieve the current sharing and total ripple reduction, communications between the modules are required for exchanging the current and phase information. Communications are often achieved by interconnecting lines, which increases the system’s complexity and reduces reliability.

To achieve current sharing without interconnecting lines, a well-established method, i.e., the voltage droop control, is usually utilized [20,21,22]. It adjusts the voltage reference of the module according to its own current, and thus, it does not require information from other modules. However, to reduce the total current ripple, the interconnecting line, which carries the phase information or the synchronous signals, is still required to achieve the interleaving operation. In references [23,24,25], the adjacent modules were connected by the interconnecting lines to transfer the phase angles of the neighboring modules or generate the clock signal, so the local module could generate its carrier to achieve the interleaving operation. Reference [26] reduced the interconnecting lines to a single line. The single signal bus carried the number of modules and sequential number at the same time, enabling the module to generate its control signal with the corresponding phase shift.

However, the interleaving line for ripple reduction still introduces the risk of a single point of failure, reducing the system’s reliability. Therefore, some research has been dedicated to eliminating the interconnecting lines. Reference [27] proposed to use the spike signals on the output voltage to extract the action moment of other modules. Then, the phase-locked loop was used to realize the interleaving operation. It can achieve the interleaving automatically; however, it is noise-sensitive. Reference [28] used the local module current to construct an oscillator circuit for control, so that the system could converge to the interleaving state. However, it required a high sampling rate. References [29,30] constructed a gradient-descent-based controller by sampling the ripple of the module current at a specific time, reducing the requirements for sampling rate. References [31,32] utilized the phase of the module current and voltage to adjust the module phase. Although the interconnecting lines were eliminated, the aforementioned methods are relatively complicated, requiring high-speed analog-to-digital conversion (ADC) and high-performance digital controllers, which distinctly increases the cost.

To achieve the current sharing and current ripple reduction without interconnecting lines, while also ensuring simpler control and lower cost, this paper proposes an analog hysteresis current control method for the paralleled buck converter. The innovations are as follows:

(1)

As shown in Figure 1, this paper proposes a modified parallel structure with the common output filter (L_t, C_o). The common filter can be implemented by the differential-mode filters, which are required in most of the parallel systems, and thus do not significantly increase the cost. With this structure, the state transition information of other modules can be integrated into the inductor voltage v_Li of each module. This configuration provides the hardware basis for the proposed control method.

(2)

An analog hysteresis current controller is constructed by utilizing the inductor voltage to generate the hysteresis band. Since the waveform of v_Li is correlated with the state transition of other modules, such a hysteresis controller can naturally achieve the interleaving operation, and no interconnecting lines are required.

(3)

The proposed hysteresis current controller can achieve the interleaving and the current control simultaneously. Additionally, the cooperation methods of the proposed current controller with the voltage droop control and the voltage outer loop are given.

This paper is organized as follows: Section 2 introduces the proposed structure of the paralleled buck converters. Next, Section 3 describes the proposed hysteresis current controller based on the shaped-inductor-voltage for the interleaving operation, and the simulation results are given. Section 4 gives the implementation methods of the proposed controller. Experimental verifications are given in Section 5. Finally, Section 6 gives the conclusions.

2. The Proposed Structure of the Paralleled Buck Converters

2.1. Structure Specification and Design Considerations

Figure 1 shows the proposed structure of the paralleled buck converters. The main design considerations are as follows:

Each module contains a control switch S_hi, a synchronous switch S_li, and an inductor L_i, and all of these buck modules are connected together at the point com. Then, the common output filter, consisting of the inductor L_t and the capacitor C_o, is connected to power the load R_l. The existence of L_t enables the state transitions of other modules to affect the inductor voltage v_Li, which is the hardware basis of the proposed controller to achieve the interleaving operation without interleaving lines. Moreover, the ripple of the total output current i_Lt flowing through L_t is small, which benefits the magnetic design of L_t.

For each module, a current sensor is used to sample i_Li for the inner hysteresis current control. A voltage sensor is used to sample the terminal voltage v_com to realize the outer voltage droop control. In addition, an independent winding is added on L_i to sample v_Li. Since v_Li contains the information of the state transition of other modules, it will be used to construct the hysteresis band for the current control, as well as to achieve the interleaving operation.

It is emphasized that both the current sharing and interleaving operations are achieved by fully utilizing the information of i_Li, v_com, and v_Li, and thus, no interconnecting lines are required.

2.2. Modeling and Analyses of the Inductor Voltage

For illustration purposes, the following analysis is conducted with the three-module-paralleled buck converter.

The equivalent circuit of the three-module-paralleled system is given in Figure 2a and v_Ai (i = 1, 2, 3) is the switching node voltage. The switching function for module i (i = 1, 2, 3) is defined as s_i. When S_hi is on and S_li is off, module i is in the on-state, and thus s_i =1. On the contrary, when S_hi is off and S_li is on, module i is in the off-state and thus s_i = 0. Therefore, v_Ai can be expressed as

$$v_{Ai}=s_i{V}_{in}.$$

(1)

Considering that the modules are identical, L₁ = L₂ = L₂ = L is satisfied. According to the superposition theorem, v_com, the voltage of the common point com, can be obtained as

$$v_{com}={\displaystyle \frac{L{V}_o+s_1{L}_t{V}_{in}+s_2{L}_t{V}_{in}+s_3{L}_t{V}_{in}}{L+3L_t}}.$$

(2)

According to Equations (1) and (2), the voltage of inductor L₁, L₂, and L₃ can be calculated as:

$$v_{L1}={\displaystyle \frac{\left(L+2L_t\right)V_{in}{s}_1-L_t{V}_{in}(s_2+s_3)-L{V}_o}{L+3L_t}},$$

(3)

$$v_{L2}={\displaystyle \frac{\left(L+2L_t\right)V_{in}{s}_2-L_t{V}_{in}(s_1+s_3)-L{V}_o}{L+3L_t}},$$

(4)

$$v_{L3}={\displaystyle \frac{\left(L+2L_t\right)V_{in}{s}_3-L_t{V}_{in}(s_1+s_2)-L{V}_o}{L+3L_t}}.$$

(5)

From Equations (3)–(5), it can be observed that v_Li is related to the input voltage V_in, the output voltage V_o, and the states (the on-state or off-state expressed by the switching function s_i) of the three modules. Figure 2b gives the voltage waveforms of v_L1, v_L2, and v_L3 when s₁, s₂, and s₃ take different values. Taking v_L1 as an example, Equation (6) gives the value of v_L1 with different s_i:

$$v_{L1}=\left\{\begin{array}{ll}{V}_{11}=\alpha [V_{in}(L+2L_t)-L{V}_o]& (s_1=1, \Sigma s_i=1)\\ V_{21}=\alpha [(L+L_t)V_{in}-L{V}_o]& (s_1=1, \Sigma s_i=2)\\ V_{31}=\alpha (L{V}_{in}-L{V}_o)& (s_1=1, \Sigma s_i=3)\\ V_{00}=-\alpha L{V}_o& (s_1=0, \Sigma s_i=0)\\ V_{10}=\alpha (-L_t{V}_{in}-L{V}_o)& (s_1=0, \Sigma s_i=1)\\ V_{20}=\alpha [-2L_t{V}_{in}-L{V}_o]& (s_1=0, \Sigma s_i=2)\end{array}\right.,$$

(6)

where α = 1/(L + 3L_t), and Σs_i = s₁ + s₂ + s₃. For the voltage value V_ij with different s_i, the subscript i represents Σs_i (the number of modules that are in the on-state), and the subscript j represents the state of the local module. For example, v_L1 = V₂₀ means that two modules in the system are in the on-state and module 1 is in the off-state. Furthermore, V_ij satisfies the relation V₁₁ > V₂₁ > V₃₁ > 0 > V₀₀ > V₁₀ > V₂₀.

From (6), several interesting features can be observed. Firstly, v_L1 is related to s_i. Therefore, when s_i changes, v_L1 changes. For example, as point A in Figure 2b, when s₁ = 0, s₂ = 0, and s₃ jump from 1 to 0, v_Li jumps synchronously from V₁₀ to V₀₀. This means that v_L1 contains the switching states of the other modules, i.e., the phase information. Similarly, the inductor voltages of the other modules exhibit the same characteristics. Therefore, it is possible to utilize v_Li to achieve the interleaving operation using appropriate methods.

3. Hysteresis Current Controller Based on Shaped-Inductor-Voltage

Based on the above structure, this paper proposes a hysteresis current controller based on the shaped-inductor-voltage, which utilizes the integrated phase information in v_Li to achieve symmetric interleaving without the interleaving line. The subsequent analysis is conducted based on the case of D < 1/3 to illustrate the proposed idea.

3.1. Construction of the Proposed Current Controller

The proposed method is based on the hysteresis current controller. It is one of the classical control methods [33]. Figure 3a shows the waveforms of the traditional hysteresis current controller, which has a fixed hysteresis band with the upper limit h_H and the lower limit h_L. The voltage v_iei is the converted current error, which satisfies v_iei = k_ivi_ei = k_iv(i_Li − I_refi) (k_iv denotes the current–voltage ratio, i_ei denotes the error between the inductor current value i_Li and the current reference I_refi). When v_iei exceeds the preset limit h_H or h_L, the control signal g_i changes to alter the operating state of module i, thereby limiting v_iei within the hysteresis band. The hysteresis current controller has the advantages of being simple, fast, and stable. However, since the operations of the three modules are independent when this method is directly utilized without communicating the phase information, the frequencies of the three modules are likely to be different, and it is challenging to achieve the interleaving operation.

Therefore, the inductor voltage v_Li, which contains the phase information, is directly used to construct the hysteresis band, as illustrated in Figure 3b. This hysteresis band produces the correction of the control signals for the modules. For example, as point A shows in Figure 3b, when g₂ changes from 1 to 0, v_hys1 simultaneously steps upward, causing v_ie1 to exceed v_hys1; hence, g₁ jumps to 1. This correction enables the three modules to operate at the same switching frequency without interconnecting lines.

However, the phase angle ϕ₁₂, ϕ₂₃, and ϕ₃₁ between these modules are not the desired value (i.e., ϕ₁₂ = ϕ₂₃ = ϕ₃₁ = 120°). This is because the voltage step resulting from the state transition of other modules causes an immediate step in the hysteresis band, which may immediately change the module state. To fix this problem, the voltage jump (as shown in point B in Figure 3c) is modified as a ramp (as shown in region C in Figure 3c). This modification delays the switching moment. (As shown in region C. After g₃ jumps to 0, v_hys1 does not follow the inductor voltage, instead, it gradually attenuates until it equals v_ie1, and subsequently, g₁ jumps to 1). Based on the designs above, a hysteresis current controller based on the shaped-inductor-voltage is proposed in this paper. The proposed hysteresis current controller can automatically converge to the symmetric interleaving operation state. The detailed analysis is given as follows.

3.2. Analysis of Interleaving Operation

The steady state waveforms of the proposed controller are given on the left of Figure 4 (see the “steady state” region). The errors of the waveform transformation process and the delay and error of the current sampling are neglected in the analysis. The upper and lower limits of the hysteresis band v_hysi can be expressed as

$$h_{\max i}=k_i{V}_{10},$$

(7)

$$h_{\min i}=k_i{V}_{01},$$

(8)

where i = 1~3, and k_i is the voltage adjustment coefficients of module i, which are constant and determined by the hardware. Since the modules are the same, k₁ = k₂ = k₃ = k, and h_min1 = h_min2 = h_min3 = h_min, h_max1 = h_max2 = h_max3 = h_max are satisfied.

According to the waveforms of the inductor current and the hysteresis band, the minimum and maximum inductor currents in the steady state satisfy the following relationships:

$$\begin{array}{cc}{I}_{10}\hfill & =(h_{\min }+{\lambda }_1{T}_{31off})/k_{iv}+I_{ref1}\hfill \\ & =h_{\max }/k_{iv}+a_{00}(T_{12off}+T_{23off}+T_{31off})+a_{10}(T_{2on}+T_{3on})+I_{ref1}\hfill \end{array},$$

(9)

$$\begin{array}{cc}{I}_{20}\hfill & =(h_{\min }+{\lambda }_2{T}_{12off})/k_{iv}+I_{ref2}\hfill \\ & =h_{\max }/k_{iv}+a_{00}(T_{23off}+T_{31off}+T_{12off})+a_{10}(T_{3on}+T_{1on})+I_{ref2}\hfill \end{array},$$

(10)

$$\begin{array}{cc}{I}_{30}\hfill & =(h_{\min }+{\lambda }_3{T}_{23off})/k_{iv}+I_{ref3}\hfill \\ & =h_{\max }/k_{iv}+a_{00}(T_{31off}+T_{12off}+T_{23off})+a_{10}(T_{1on}+T_{2on})+I_{ref3}\hfill \end{array},$$

(11)

$$I_{11}=h_{\max }/k_{iv}+I_{ref1}=I_{10}+a_{11}{T}_{1on},$$

(12)

$$I_{21}=h_{\max }/k_{iv}+I_{ref2}=I_{20}+a_{11}{T}_{2on},$$

(13)

$$I_{31}=h_{\max }/k_{iv}+I_{ref3}=I_{30}+a_{11}{T}_{3on},$$

(14)

where I_i0 and I_i1 are the minimum and maximum current of module i, respectively; I_refi is the current reference of module i; a₀₀, a₁₀, and a₁₁ are the current changing rates, and a₀₀ = V₀₀/L, a₁₀ = V₁₀/L; and a₁₁ = V₁₁/L are satisfied. λ_i is the attenuation rate of the ramp in v_hysi. λ_i and k_iv are determined by the hardware design and considering that the parameters of the three modules are the same, λ₁ = λ₂ = λ₃ = λ are satisfied. T_1on, T_2on, and T_3on are the periods when module 1, module 2, and module 3 are in the on-state, respectively. T_12off, T_23off, T_31off are the periods of t_s1~t_s2, t_s3~t_s4, t_s5~t_s6, respectively, as shown in Figure 4.

Considering a small disturbance happens during t₀₀~t₁₁ on module 1, which breaks the steady state, I_refi is assumed to be constant and equal to its steady-state value during this process. Since I_refi is generated by the voltage outer loop with a relatively slow response speed compared to the current inner loop, this assumption is reasonable. The small disturbance causes a deviation of ΔT_31off[0] from the steady-state value T_31off, and the length of this time interval $\widehat{T}$_31off[0] is

$${\widehat{T}}_{31off}[0]=T_{31off}+\Delta T_{31off}[0].$$

(15)

With the analysis in Appendix A, the expressions of ΔT_31off[k] can be derived as

$$\Delta T_{31off}[1]={\displaystyle \frac{\alpha a_{00}(a_{11}-a_{10})[(2a_{11}-a_{10})\cdot {\lambda }_{iv}-a_{00}{a}_{11}]}{a_{11}^2{({\lambda }_{iv}-a_{00})}^2}}\Delta T_{31off}[0],$$

(16)

$$\Delta T_{31off}[2]=({\alpha }^3+2{\alpha }^2)\Delta T_{31off}[1]+{\displaystyle \frac{{\alpha }^2\left(\alpha +1\right)a_{00}{\lambda }_{iv}{\left(a_{11}-a_{10}\right)}^2}{a_{11}^2\cdot {\left({\lambda }_{iv}-a_{00}\right)}^2}}\Delta T_{31off}[0],$$

(17)

$$\Delta T_{31off}[k]=({\alpha }^3+3{\alpha }^2)\Delta T_{31off}[k-1]+{\alpha }^3\Delta T_{31off}[k-2] (k\ge 2),$$

(18)

where the coefficient α is

$$\alpha =-{\displaystyle \frac{a_{10}{\lambda }_{iv}-a_{00}{a}_{11}}{a_{11}({\lambda }_{iv}-a_{00})}},$$

(19)

where λ_iv satisfies λ_iv = λ/k_iv.

The coefficients are relatively complex. Therefore, to demonstrate that the system can return to the steady state under the disturbance, the hardware parameters in

Table A1. Parameters for the simulations and experiments.

Parameter	Value
Inductor inside the module Li	132 μH
Common inductor Lt	60 μH
Common capacitor Co	250 μF
Rated input voltage Vin	48 V
Output voltage Vo	12 V
Rated load Rl	2 Ω
Voltage adjustment coefficients ki	0.018 V/V
Attenuation rate λ	3577 V/s
Current–voltage ratio kiv	1.0 V/A

are substituted into Equations (16)–(18). Figure 5 shows the variation curve of ΔT_31off[k]/ΔT_31off[0] with respect to the number of recurrences. It can be seen that ΔT_31off[k]/ΔT_31off[0] reduces rapidly when k ≥ 2, ΔT_31off[k]/ΔT_31off[0] ≈ 0 holds when the recurrence number k ≥ 17. This demonstrates that ΔT_31off[k] gradually approaches zero after several periods, i.e., $\widehat{T}$_31off[k] can converge to the corresponding steady-state value T_31off. Similarly, the deviations of other intervals can also converge to zero. Therefore, the system can recover to a steady state after the small disturbance, which indicates that the proposed controller exhibits good stability. Figure A1 in Appendix A gives more numerical results with different V_in, V_o, or λ. The curves show that ΔT_31off[k] can also gradually approach zero under these conditions. This further validates that the proposed controller can recover to the steady state.

When the modules are working under the steady state, the three modules in the system have the same period T_s (frequency), i.e., T_s = T_1on + T_2on + T_3on + T_12off + T_23off + T_31off. Therefore, according to the volt-second balance principle, these modules satisfy

$$V_{00}(T_{12off}+T_{23off}+T_{31off})+V_{10}{T}_{1on}+V_{01}(T_{2on}+T_{3on})=0$$

(20)

$$V_{00}(T_{12off}+T_{23off}+T_{31off})+V_{10}{T}_{2on}+V_{01}(T_{3on}+T_{1on})=0$$

(21)

$$V_{00}(T_{12off}+T_{23off}+T_{31off})+V_{10}{T}_{3on}+V_{01}(T_{1on}+T_{2on})=0$$

(22)

The difference between (20) and (21) yields (V₁₀ − V₀₁)(T_1on − T_2on) = 0. Since V₁₀ > 0 > V₀₁ holds, it is established that V₁₀ − V₀₁ > 0 consistently holds. Therefore, T_1on = T_2on can be derived. With the similar method, it can be derived that

$$T_{1on}=T_{2on}=T_{3on},$$

(23)

which indicates that the duty cycles of the three modules in the system are the same for the steady state.

This represents that the three modules have the same duty cycle D in the steady state. With (23), the difference between (9) and (10) yields T_12off = T_31off. With similar method, the following expression holds

$$T_{12off}=T_{23off}=T_{31off}.$$

(24)

Therefore, based on Equations (23) and (24), it can be derived that

$$T_{1on}+T_{12off}=T_{2on}+T_{23off}=T_{3on}+T_{31off}=T_s/3,$$

(25)

in other words, the phase angles between the three modules satisfy the relationship of ϕ₁₂ = ϕ₂₃ = ϕ₃₁ = 120°. The above analyses prove that with the proposed hysteresis current controller, the three modules can realize the symmetric interleaving in the steady state.

The steady-state waveforms for the cases of 1/3 ≤ D ≤ 2/3 and D ≥ 2/3 are shown in Figure 6. Although the position of the ramp in v_hysi is slightly different, it can also demonstrate that the symmetric interleaving operation can be achieved using a similar analysis method.

Although the above analysis is based on the three-module-paralleled system, the proposed method can be utilized in the system with two or more modules, and the analysis methods above and the conclusions still hold.

3.3. Simulation Verification

To validate the above analysis, the paralleled buck converters are built in MATLAB Simulink with the parameters in Table A1.

Figure 7a depicts the dynamic process with the disturbance of the current reference I_ref, with V_in = 48 V. During the simulation, I_ref1 = I_ref2 = I_ref3 = I_ref are given, and I_ref is set to change from 1.8A to 0.9A. Before the disturbance, the three modules achieve the symmetric interleaving operation with phase angles of 120°, as shown in Figure 7b. When the disturbance occurs, the phase angles are affected but the system can gradually converge to the steady state with the phase angle of 120°, as shown in Figure 7c. This verifies that the three-module-paralleled system can automatically adjust the phase after disturbance and can converge to the symmetric interleaving state. Furthermore, Figure 7d shows the key waveforms of the proposed hysteresis current controller in module 1, with I_ref = 1.8A. A hysteresis delay of 0.05 V for realizing the comparison of v_ie1 and v_hys1 is used to enhance the anti-interference capability. The waveforms well match the analysis waveforms in Figure 4. It can be observed that several voltage jumps exist on v_L1, which are introduced by the actions of other modules in the system, and these voltage jumps are adjusted to the voltage ramps on v_hys1, e.g., region A in Figure 7d.

Figure 8a,b give the simulation results of the steady state waveforms for 1/3 ≤ D ≤ 2/3 (with V_in = 24 V and I_ref = 2A) and D > 2/3 (with V_in = 16 V and I_ref = 2A), respectively. The waveforms also match those in Figure 6 and the symmetric interleaving can also be achieved in both cases.

Figure 9a gives the simulation results of a six-module-paralleled system and it shows that the system can restore stability after module addition. The zoomed views in Figure 9b,c show that both the five-module-paralleled system and the six-module-paralleled system can operate in the symmetric interleaving states, with phase angles of 72° (360°/5) and 60° (360°/5), respectively. The proposed method is effective for the system with more modules. In addition, it has hot-plug capability and the phase angles can automatically adjust.

4. Implementation of the Proposed Hysteresis Current Controller

4.1. Hardware Design of the Proposed Hysteresis Current Controller

The proposed hysteresis current controller is implemented by analog methods.

According to the analysis above, the proposed hysteresis current controller has integrated the phase information into the waveform of v_Li to eliminate the interconnecting lines. However, the actions of the switches result in high-frequency noise on v_Li, and the noise increases with the increase in the operating voltage and current. Therefore, when implementing the proposed hysteresis current controller, it is necessary to use some methods, such as isolated sampling and filtering, to cope with the noise and to guarantee the stability of control.

Figure 10 shows the circuit diagram of the controller in module i. An independent winding of W turns is added to the inductor to sample v_Li and the isolated sampling method ensures strong noise immunity. The sampled signal v_seci is proportional to v_Li and is used to construct the hysteresis band v_hysi. Furthermore, the low-pass filter with a bandwidth of 1.06 MHz is employed to filter out the high-frequency noise while not affecting the voltage jump information (i.e., phase information) in v_seci. To generate the ramp, the positive part and negative part of the waveforms of v_seci are separately shaped.

For the positive part shaping, a peak voltage detection (PVD) circuit is utilized to detect and maintain the maximum value. The discharging resistor R_dis is paralleled across the capacitor C_pk of the PVD circuit to form the required ramp. When v_seci falls, C_pk discharges through R_dis, converting the voltage jump into the slowly discharging voltage. Moreover, during the period when v_seci is less than zero, the output of the PVD circuit is clamped to 0 by the negative voltage shielding (NVS) circuit, avoiding its influence on the shaping of the negative part. Thereout, the shaped voltage v_posi for the positive part is obtained. The values of C_pk and R_dis need to be chosen carefully. C_pk should not be too large so that the PVD circuit can track the peak value quickly, while R_dis needs to be carefully chosen to ensure that the ramp always exists before the next state transition of this module. Furthermore, the low-pass filter is added to each stage of the operational amplifier to avoid noise interference.

For the negative part shaping, v_seci is firstly inverted by the phase inverter, and then v_negi can be obtained using the same method of processing v_posi. Subsequently, v_posi and v_negi are combined by the subtractor to obtain v_hysi. Both v_hysi and the current error i_ei of module i are fed into the hysteresis comparator to generate the control signal g_i for module i. The hysteresis comparator can suppress noise and enhance the stability of the comparison.

From the implementation process of the proposed hysteresis current controller, it can be seen that to construct v_hysi with v_Li, the analog basis method is the most convenient and cost-efficient way (in the digital method, the high-speed ADC and digital controller are required to realize hysteresis operation, leading to an increase in implementation costs). Furthermore, due to the simple structure of the proposed hysteresis control, only the voltage adjustment coefficients k_i (voltage divider resistors) and attenuation rate λ (C_pk and R_dis) need to be tuned.

4.2. Cooperation with the Voltage Outer Loop and the Voltage Droop Control

Furthermore, the proposed current hysteresis controller can achieve both the interleaving and the inner loop current control. The required current reference I_refi comes from the voltage droop control for current sharing and the voltage outer loop, which can be implemented with common methods.

To realize the voltage outer loop, the output voltage V_o is rebuilt from the terminal voltage v_comi of each module. v_comi of module i can be expressed with

$$v_{comi}=v_{Lt}+v_o,$$

(26)

where v_Lt is the transient voltage across the common inductor L_t, and v_o is the transient output voltage. Filtering the signal v_comi with a simple RC filter, the low-frequency components of v_comi, namely $\stackrel{\mathrm{-}}{v}$_comi, can be obtained (the time constant of the RC filter should be much smaller than that of the outer voltage loop). Mathematically, $\stackrel{\mathrm{-}}{v}$_comi is

$${\overline{v}}_{comi}={\overline{v}}_{Lt}+{\overline{v}}_o\approx V_o,$$

(27)

In (27), the average inductor voltage $\stackrel{\mathrm{-}}{v}$_Lt converges to zero due to the volt-second balance principle; therefore, $\stackrel{\mathrm{-}}{v}$_comi is dominated by the filtered average voltage $\stackrel{\mathrm{-}}{v}$_o, i.e., V_o. Therefore, $\stackrel{\mathrm{-}}{v}$_comi can be used to estimate V_o as the feedback in the outer voltage loop. The expression of the voltage outer loop based on the PI (Proportional-Integral) controller can be expressed as

$$I_{refi}=K_p(V_{refi\_dr}-{\overline{v}}_{comi})+K_i{\displaystyle \int (V_{refi\_dr}-{\overline{v}}_{comi})},$$

(28)

where K_p and K_i are the proportional and integral coefficients, respectively. Moreover, V_{refi_dr} is the voltage reference with a droop feature. The output of the controller is treated as the current reference I_refi of the inner hysteresis controller.

For voltage droop purpose, V_{refi_dr} is obtained by introducing the average of the sampled current value $\overline{I}$_Li as feedback

$$V_{refi\_dr}=V_{ref}-k_{dr}{\overline{I}}_{Li},$$

(29)

where k_dr represents the droop coefficient and V_ref represents the voltage reference value. With (29), the goal of the voltage droop is to achieve the balance of $\overline{I}$_Li. Since $\overline{I}$_Li equals the output current I_oi, the output currents can also be naturally shared.

5. Experimental Verification and Discussion

To experimentally validate the proposed hysteresis current controller, a three-module system prototype was built with the parameters in Table A1, as shown in Figure 11. It can be seen that there are only power connections among the modules, and no interconnection lines exist for signal transmission.

Figure 12a,b show the dynamic processes of the load transitions while maintaining V_o at 12 V. It can be seen that the paralleled system can achieve the regulation of V_o. After the load addition in Figure 12a, the steady-state value of V_o decreased from the original value of 11.99 V to 11.85 V due to the voltage droop control, and after the load removal in Figure 12b, V_o recovered from 11.85 V to 11.99 V. Meanwhile, the inductor currents of the three modules, i_L1, i_L2, and i_L3, are always overlapped, which indicates that the current sharing can be achieved even in the dynamic processes. The current sharing error is within 4.0%.

The interleaving operation can be further observed in Figure 12c,d. Figure 12c shows the zoomed view of the steady state with the full load, and the phase angles ϕ₁₂, ϕ₂₃, and ϕ₃₁ were 118.0°, 123.5°, and 118.5°, respectively. Figure 12d shows the zoomed view of the steady state with the half load, and the phase angles ϕ₁₂, ϕ₂₃, and ϕ₃₁ were 124.9°, 117.8°, and 117.3°, respectively. The phase angles of both states were close to the desired value of the symmetric interleaving 120° (360°/3), with a maximum relative error of 4.1%. This demonstrates that the proposed method can automatically achieve the symmetric interleaving operation.

From the experimental results above, it can be seen that for the proposed method, the phase shift error and the current sharing error exist. The phase shift error results from the inconsistencies of the hardware parameters, including the delay of the comparator, and the accuracy of the resistors. These inconsistencies are inherent problems of using the analog circuits for generating the control signals. For the methods with interconnecting lines, the information on the lines is always generated by the digital controllers. Therefore, the phase shift error and the current sharing error result from the accuracy of the phase lock loop (PLL) and the ADC. For example, [26] utilizes one interconnecting line to carry a synthetic signal generated by the operating modules. With the synthetic signal, each module can decode the total number of operating modules and its sequential number, thereby achieving the interleaving and current sharing. The phase shift error results from the PLL, e.g., the phase shift error of the method in [26] is about 5.4%. Furthermore, the error of the proposed method can be further decreased by selecting the resistors with higher precision and analog devices with more consistent characteristics or integrating the circuits by using integrated circuit technology to improve the consistency.

Figure 13 gives the waveforms of two extreme situations, i.e., the module removal and addition. Figure 13a gives the waveforms of the dynamic process when removing module 3 from the three-module-paralleled system. After the removal of module 3, V_o stabilized at 11.77 V after 1.96 ms. Furthermore, i_L1 and i_L2 increased simultaneously and maintained the current sharing throughout the dynamic process. Figure 13b gives the zoomed view of the module removal. It can be observed that when module 3 was removed, the phase angles of the remaining modules automatically adjusted and gradually approached the values under the symmetric interleaving state. The zoomed view of the steady state is given in Figure 13c and it shows that the two remaining modules could also achieve the symmetric interleaving operation with the phase angles of 177.9° and 182.1°, which are close to 180° (360°/2) with a relative error of 1.2%.

Figure 13d gives the dynamic waveforms of the module addition. The addition of module 3 to a two-module-paralleled system resulted in the fluctuations of V_o; nevertheless, V_o could stabilize at 11.84 V with a settling time of 2.41 ms. As i_L3 increased, i_L1 and i_L2 decreased, and the current sharing among the three modules was achieved after about 30 ms. The transient of module addition is shown in Figure 13e, and it shows that when module 3 was added, the phase angles adjusted automatically. Figure 13f shows the zoomed view of the steady state, where the two-module-paralleled system could also achieve the symmetric interleaving operation with the maximum relative error of 1.2%.

The above experimental results demonstrate that the proposed hysteresis current controller has the hot-plug capability, which enhances the modularity, scalability and redundancy of the system.

Most of the hot-plug methods are achieved based on digital controllers. Therefore, these methods require detection of the circuit state to determine whether the module is added or removed. Then, the controller can adjust the phase shift cycle by cycle based on the detection results, and the system recovers to a stable state after multiple periods. On the contrary, the proposed method uses the analog hysteresis current controller to achieve both the current sharing and the interleaving. Consequently, once the module is added or removed, the waveform of v_Li is immediately changed, resulting in the synchronous changes in the hysteresis band v_hysi. Furthermore, the inductor current can quickly respond to the change in v_hysi. Therefore, the dynamic processes can be faster.

To compare the hot-plug performance, the simulation of the proposed method under similar conditions of the method in [31] (It is realized with digital controllers without the interleaving lines) was conducted. The parameters are given in

Table A2. Parameters for the simulations of Figure 14.

Parameter	Value
Inductor inside the module Li	180 μH
Common inductor Lt	60 μH
Common capacitor Co	50 μH
Rated input voltage Vin	24 V
Output voltage Vo	8 V
Rated load Rl	1 Ω
Voltage adjustment coefficients ki	0.1 V/V
Attenuation rate λ	20,000 V/s
Current–voltage ratio kiv	1.0 V/A

and the results are given in Figure 14. It can be seen that after the module addition, V_o recovered to the stable value after 731 μs. Additionally, the symmetric interleaving and current sharing were achieved after 348 μs and 3 ms, respectively. In contrast, for the method in [31], the dynamic process lasted for 13 ms. In addition, for the module removal process, the current sharing is always achieved. V_o recovered to the stable value after 447 μs and the symmetric interleaving was achieved after 316 μs. These times are much shorter than those of the method in [31] (13 ms). Therefore, the dynamic processes of both the module addition and removal are much faster than the method in [31].

6. Conclusions

This paper proposes a hysteresis current controller for the paralleled buck converters to achieve the interleaving operation without the need for interconnecting lines. Firstly, the paralleled structure is slightly modified to integrate the phase information into the inductor voltage in the module. Then, the hysteresis current controller based on the shaped-inductor-voltage is designed and with the controller, the symmetric interleaving is automatically achieved. The effectiveness of the proposed control method is validated through simulations and experiments. The results confirm the following:

(1)

The proposed hysteresis control can achieve symmetric interleaving of the modules, with the maximum phase angle error of 4.1%;

(2)

The current sharing can be achieved by combining the proposed controller with the voltage drop control, and the error of current sharing is within 4.0%;

(3)

The hot-plug capability is verified. The modules can achieve the current sharing after adding the new module for 30 ms and can keep the current sharing after removing one module. At the same time, the phase angles can automatically adjust to the symmetrical interleaving state.

(4)

The output voltage can recover within 2.60 ms after the load transitions from 50% to 100% and recover within 3.53 ms after the load transitions from 100% to 50%. In addition, the output voltage can recover within 1.96 ms after one module removal and recover within 2.41 ms after one module addition.

The proposed method utilizes an additional winding to sample the inductor voltage for constructing the hysteresis band, thereby eliminating the need for isolated voltage sensors. Furthermore, the construction of the hysteresis band and the generation of the control signals are implemented by analog circuits, thereby eliminating the need for high-speed ADC and a high-performance digital controller. These characteristics demonstrate that the proposed method has the merits of low cost and simplicity. Additionally, the results of the load transitions and hot-plug demonstrate the robustness. Therefore, the proposed controller can reliably achieve the desired control objectives without the need for interconnecting lines, making it highly potential for those applications that require reliability, modularity, and scalability.

The proposed method is hysteresis-control-based, which suffers from frequency variation with voltage variation. Hence, one of the future research opportunities will be to reduce the frequency variation range of the proposed control to facilitate the filter design. In addition, future research will extend this method to other paralleled DC–DC converters. Moreover, the proposed idea is currently verified by the circuit with discrete components, however, such a circuit is suitable for being made into integrated chips so as to further reduce costs and improve reliability and consistency.