TCAD Simulation of an E-Mode Heterojunction Bipolar p-FET with I_max > 240 mA/mm

Abstract

This work demonstrates an enhancement mode heterojunction bipolar p-FET (HEB-PFET) structure with a AlGaN/GaN heterojunction bipolar transistor (HBT) integrated on the drain side. Such device design notably contributes to the ultra-high output current density, which is conventionally limited by the low hole mobility and concentration in the p-FETs. The HEB-PFET exhibits an output current density of 241 mA/mm, which is 134 times larger compared to the conventional p-FET (C-PFET) and 2.4 times of the homojunction bipolar p-FET (HOB-PFET). This can be attributed to a better current gain of HBT than homojunction bipolar transistor (BJT). An optimized HEB-PFET of 6 nm p-GaN layer beneath the gate is proposed, where I_ON/I_OFF is >10¹¹, and V_th is −0.44 V. Additionally, thermal stabilities are studied with temperature changes from 300 K to 425 K. Moreover, a semi-empirical compact model is presented to visually explain the working principle of the HEB-PFET.

1. Introduction

Gallium nitride (GaN), as an emerging wide bandgap semiconductor material, is regarded as a key material to promote the development of the next generation of high-efficiency and high-frequency electronic devices because of its outstanding electron mobility and high breakdown electric field strength [1]. With the maturity of GaN n-channel high-electron mobility transistor (HEMT) technology, considerable performance improvements have been brought to the fields of power electronics, radio frequency applications, and high-speed digital circuits. GaN-based complementary metal oxide semiconductor (CMOS) technology combines the wide-band gap characteristics of GaN with the low static power consumption advantages of CMOS, showing significant potential in promoting the development of integrated circuits (ICs). The GaN-based power and associated peripheral devices in use today are solely reliant on n-channel, meaning that integrated logic circuits cannot leverage the most power-saving complementary logic solutions that are prevalent in Si logic ICs [2]. Therefore, the fabrication of E-mode GaN p-channel field-effect-transistors (p-FETs) has become crucial to fully exploit the performance of GaN CMOS technology, which not only improves circuit switching speed and reduces static power consumption [2,3,4] but also simplifies circuit design for safer and more reliable operation.

However, the severe mismatch in current density driving capability between p-FETs and n-HEMTs is the primary obstacle to achieving high-performance GaN-based CMOS logic circuits. The average hole mobility of GaN p-FETs at room temperature is about 16 cm²/V·s [5,6], which is much smaller than the electron mobility (>1000 cm²/V·s) due to the large hole effective mass. Additionally, p-GaN layer is often achieved by doping magnesium (Mg), where Mg has an activation rate of only 2–3% at room temperature [7], making it challenging to realize the high concentration of holes. Thus, it is a knotty task to obtain GaN based p-FETs with high output drain current density (I_D). To address these issues, some researchers have confirmed that optimization of heterojunctions can effectively improve the output characteristics of GaN p-channel devices, including (1) AlN/GaN [8,9] (2) InGaN/GaN [5,10] (3) GaN/AlInGaN [11,12]. However, the problem is that they cannot be integrated with the mainstream commercial n-HEMTs. Therefore, from the perspective of GaN ICs integration, the GaN/AlGaN heterojunction structure is preferred for the design of GaN p-FETs. Considering the safety and circuit design simplification, enhancement mode p-FETs are preferred. Several studies have been reported to achieve enhancement device, in which devices with recessed gate are widely used [13,14]. The recessed gate is formed by etching the p-type layer beneath the gate to deplete the 2DHG channel under the gate, ensuring that the device is depleted at the off-state. Other methods to achieve enhancement mode include oxygen (hydrogen) plasma treatment [15], n-GaN [16] or n-AlGaN gate cap [17], and hybrid barrier layer [5].

GaN/AlGaN heterojunction-based P-FETs are more attractive because this structure can monolithically integrate with the predominant commercial p-GaN gate-enhanced GaN HEMTs. However, the output current density is around 20 mA/mm in the enhancement devices, which is too small to integrate with GaN based HEMTs [7,13,14,17,18,19]. In order to improve the performance of enhancement mode GaN/AlGaN p-FET, Yang et al. [18] reported enhancement-mode p-channel heterojunction field–effect transistors without gate recess on a standard p-GaN/AlGaN/GaN high electron mobility transistor platform, obtaining a drain current density of 0.2 mA/mm and a threshold voltage of −0.6 V. And Raj et al. [19] proposed GaN/AlGaN superlattice-based normally-off hole channel FinFET devices, characterized by a current density of 13 mA/mm and a threshold voltage of −0.2 V. More recently, Tang et al. [20] have introduced an innovative approach to increase the output current density by adding a NPN bipolar stack of n-/p-/n-GaN on the drain side of the p-FET and enhanced the conduction capability by converting electrons into the main carriers, and obtaining a threshold voltage of −2 V through the recessed gate, with an output current density of 120 mA/mm. In this work, a GaN-based p-FET is proposed on the conventional p-GaN HEMT platform, and a GaN/AlGaN heterojunction is used to form two-dimensional hole gas (2DHG). Additionally, a heterojunction bipolar structure is proposed on the drain side of the device. The electric characteristics of the proposed HEB-PFET have been studied and compared with HOB-PFET and C-PFET. The simulation results show that the HEB-PFET exhibits the largest output drain current density, this can be ascribed to a larger current density gain of HBT. Both devices show a good gate control ability, where the leakage current density is less than 10⁻⁸ mA/mm and the I_ON/I_OFF ratio reaches 10¹¹. In addition, the p-GaN layer beneath the gate is recessed to obtain enhancement mode, and the thermal stability of the proposed device is also studied. Moreover, to improve understanding and predictability of the proposed HEB-PFET, a semi-empirical compact model of the output current density I_D of the device is given.

2. Device Structure and Simulation Models

Figure 1a,b exhibit a schematic of the proposed HEB-PFET and a commercial p-GaN HEMT platform, respectively. The commercial p-GaN HEMT platform consists from top to bottom of a 70 nm p-GaN layer doped with a Mg concentration of 2 × 10¹⁹ cm⁻³, a 6 nm p-GaN layer underneath the gate (t), a 15 nm Al_0.2Ga_0.8N barrier layer doped with Si concentration of 5 × 10¹⁶ cm⁻³, a 420 nm unintentionally doped GaN (UID-GaN) layer, and 4.2 μm GaN buffer layer on a substrate. A recessed gate is introduced into a commercial p-GaN HEMT platform to form the C-PFET, as shown in Figure 1c. The HEB-PFET is obtained by integrating the AlGaN/GaN Heterojunction bipolar transistor stack on the drain side of the C-PFET. The stack structure is as follows: an 80 nm AlGaN layer (Si: 5 × 10¹⁸ cm⁻³), a 70 nm p-GaN layer (Mg: 2 × 10¹⁹ cm⁻³), a 100 nm n⁻-GaN layer (Si: 5 × 10¹⁷ cm⁻³) and a 120 nm n-GaN layer (Si: 5 × 10¹⁸ cm⁻³). In addition, a 100 nm unintentionally doped GaN layer is applied between the stack and the platform to reduce the impacts of Mg memory effect [20]. The gate dielectric is Al₂O₃ with a thickness of 20 nm, which is used to suppress the gate leakage current [5], and the recessed gate is applied to obtain an E-mode operation [21]. The gate-source (L_GS), gate-drain (L_GD) spacing, gate length (L_G) and gate width (W_G) are 3 μm, 3 μm, 3 μm, 1 mm, respectively.

The device characteristics in this work were simulated by Silvaco TCAD (2022, Santa Clara, CA, USA) modeling that considered the coupled carrier Poisson continuity equation [22]. The temperature was set to 300 K by default. According to previous reports [23], Shockley-Read-Hall and Auger recombination were employed to simulate trap dynamics. The hole transport was calculated by the Albrecht mobility model [24] at low field and the nitride specific field dependent mobility was used at high field. Accordingly, the maximum hole mobility was limited to 16 cm²/Vs, which is consistent with the hole mobility reported in GaN p-FETs [6]. Polarization models were taken into account due to the strong spontaneous and piezoelectric polarization effects in GaN material, and all calculations were based on the Fermi-Dirac statistics. The gate contact was set as Schottky contact with the metal work function of 4.8 eV. A contact resistance of 10⁻⁴ Ωcm² was set for source contacts to p-GaN [25], while drain and collector contact resistance set to 10⁻⁵ Ωcm² [26]. In addition, a fixed charge density at the oxide/GaN interface of 4.65 × 10¹² cm⁻² was introduced in our simulation. I_D − V_GS characteristics were compared with the reported result [5] to validate the applicability of our models as shown in Figure 1d. The numerical algorithm employed was the Newton iteration method with a set iteration count of 10, and the tolerance parameters were the default values.

3. Results and Discussion

The following sections are organized into four parts. Firstly, the performances of the GaN homojunction bipolar transistor and AlGaN/GaN heterojunction bipolar transistor are presented. Secondly, a comparison and detailed explanation of the electrical characteristics of the C-PFET, HOB-PFET, and HEB-PFET are provided. Thirdly, an optimized HEB-PFET is proposed by modulating p-GaN layer thicknesses underneath the gate with consideration of threshold voltage and output current density. Fourthly, the electrical properties of the HEB-PFET at different temperatures are proposed. Lastly, a semi-empirical compact model is introduced to offer an insightful understanding of the HEB-PFET output characteristics.

3.1. I–V Characteristics of GaN BJT and AlGaN/GaN HBT

The bipolar junction transistor is an essential semiconductor device characterized by its primary function of current amplification. Composed of two back-to-back PN junctions, the BJT has three main parts: the emitter, the base, and the collector. The heterojunction bipolar transistor, which is a modified form of the BJT, is formed by utilizing different semiconductor materials to create a heterojunction between the emitter and the base. In this section, we focus on the effects of the current gain by employing GaN or AlGaN as the emitter. The stack structures of the GaN BJT and AlGaN/GaN HBT are designed on the drain side of the p-FETs as shown in the circled region in Figure 1a, in order to form the HOB-PFET and the HEB-PFET, respectively. An emitter size of 0.5 × 40 μm² is possessed by the devices in Figure 2.

Figure 3a shows the Gummel plot of the GaN BJT. The base-collector voltage (V_BC) was maintained at a constant 0 V throughout the simulation. The amplification factor (β) is determined by dividing the collector current density ($I_C$) by the base current density ($I_B$) at various base-emitter voltages (V_BE) [27]. The device achieves a current density gain β = 76 at V_BE = 10 V with $I_B$ = 4.8 mA/mm and $I_C$ = 367.7 mA/mm. Figure 3b shows the common-emitter I–V characteristics of the GaN BJT. The collector voltage V_CE sweeps from 0 to 12 V, and the base current density I_B sweeps from 0.25 to 2.5 mA/mm with 0.25 mA/mm per step. The maximum collector saturation current density is 167.5 mA/mm at V_CE = 12 V.

Figure 3c,d are Gummel curves and output curves of AlGaN/GaN HBT. In Figure 3c, the base current density and collector current density intersects at a voltage of 3.2 V. The low crossover voltage indicates a low base resistance [28]. When the base-emitter voltage is 10 V, with a base current density of 4.04 mA/mm and a collector current density of 770.2 mA/mm, the current density gain reaches 191, which is more than 2.5 times larger than the GaN BJT. In addition, the maximum collector saturation current density is as high as 460 mA/mm at V_CE = 12 V.

The better current amplification effect shown by AlGaN/GaN HBT can be explained by the energy band diagrams and current composition as shown in Figure 4. The current gain for a BJT amplifier is defined as follow [29]:

$$\beta ={\displaystyle \frac{I_C}{I_B}}={\displaystyle \frac{I_{E,n}-I_{B,b}-I_{B,re}}{I_{B,p}+I_{B,b}+I_{B,re}}}$$

(1)

The electron diffusion current from the emitter to the base is denoted by $I_{E,n}$, while the hole diffusion current from the base to the emitter is represented by $I_{B,p}$. The term $I_{B,re}$ refers to the complex current within the space charge region of the emitter junction, and $I_{B,b}$ signifies the complex current within the base. $I_{B,b}$ and $I_{B,re}$ together constitute the current base region of $I_B$. Compared with GaN BJT, the valence band offset ∆E_V of the BE junction in AlGaN/GaN HBT is larger due to the band discontinuity between AlGaN/GaN, which further inhibits the reverse injection current of holes from the base region to the emission region $I_{B,p}$ [29], thus improving the injection efficiency. This efficient injection mechanism means that more electrons are able to participate in the amplification process, thereby increasing the gain of the transistor. In addition, the interface of the AlGaN/GaN heterostructure generates a high-density two-dimensional electron gas (2DEG) with higher electron mobility due to the polarization effect, which also contributes to the improvement of current gain.

3.2. I–V Characteristics of the C-PFET, HOB-PFET and HEB-PFET

As shown in the circle region in Figure 1a, the GaN BJT or GaN/AlGaN HBT is integrated at the drain side of the conventional p-FET. The contact at the bottom n-GaN layer is shorted with source, defined as Ω side as shown in Figure 1, which is served as an electron source for current amplification [20]. When the device is turned on, the small hole current density in the p-channel is amplified through the BJT to achieve a high current density.

The transfer characteristics in linear and semi-logarithmic coordinates of the C-PFET, HOB-PFET and HEB-PFET are plotted in Figure 5a,b. It can be observed from Figure 5b that the threshold voltages (V_th) of the three structures are −0.83 V, −0.43 V and −0.44 V, respectively, at the current density of 10⁻² mA/mm. All the devices reach enhancement mode thanks to the recessed p-GaN gate layer. In addition, the off-state leakage current density of the proposed HEB-PFET is lower than 10⁻⁸ mA/mm at V_GS = 0 V, offering an ultra-low static power consumption required for CMOS logic circuits [3]. The HEB-PFET has the smallest subthreshold swing (SS) is 271 mV/dec, indicating a faster transition between the on-state and off-state, which is a key factor in achieving high-performance, low-power integrated circuits, where the subthreshold swing of HOB-PFET is 280 mV/dec and C-PFET is 427 mV/dec. The switching conduction ratio (I_on/I_off) is as high as 10¹¹. As shown in Figure 5b, the off-state current of HEB-PFET and HOB-PFET fluctuated while that of C-PFET did not happen, this can be attributed to the leakage path in npn stack on the drain side. Little electrons exit in the leakage path of the npn stack. Figure 6a–c show the e⁻ current density distribution of the C-PFET, HOB-PFET, and HEB-PFET at off-state (@V_GS = 1 V, V_DS = −10 V), respectively. As can be noticed from Figure 6, compared with C-PFET, a large amount of e- current density can be obviously observed in the npn stack of HOB-PFET and HEB-PFET, resulting in fluctuate off-state leakage current.

Figure 7a–c present output characteristics of the C-PFET, HOB-PFET and HEB-PFET, respectively. Both HOB-PFET and HEB-PFET demonstrate better current conduction capabilities compared with C-PFET. The saturation drain current density of 241 mA/mm is obtained from I_D − V_D curves of HEB-PFET, while 100 mA/mm and 1.8 mA/mm are achieved for HOB-PFET and C-PFET (@V_GS = −10 V, V_DS = −10 V), respectively. Therefore, the proposed HEB-PFET exhibits the largest output drain current density of 134 times larger than C-PFET, and 2.4 times larger than HOB-PFET.

There is a detail in the output curves of p-FET with integrated BJT at a small V_DS. Compared with the C-PFET, the current density order of HOB-PFET and HEB-PFET is very small within the V_DS range of −4–0 V. This distinction can be explained by the V_BE0 voltage, identified at the intersection of the I_C and I_B curves in Figure 3a,c. When V_DS < V_BE0, BJT is in the cut-off region and blocks the current. Conversely, BJT operates in the amplification region and enhances the current of the p-FET when V_DS > V_BE0. The inset plot in Figure 7b,c is the output curves of the HEB-PFET in a semi-logarithmic coordinate system across the V_DS range from −4 to 0 V, corroborates the above explanation.

Obviously, the HEB-PFET performs the best output characteristics, followed by the HOB-PFET and the C-PFET is the worst. This is due to the fact that the former two integrate npn-type BJT under the drain side, transforming electrons into the primary carriers. Moreover, the HEB-PFET exhibits a higher output current density of 2.4 times larger than HOB-PFET, owing to the larger current density gain of the AlGaN/GaN HBT, which is in consistent with the results in Figure 3. Meanwhile, the gate leakage current density remains at a low level, and the I_on/I_off ratio does not degrade significantly.

3.3. Optimization of the HEB-PFET

The transfer and output characteristics with the varied t of 4, 5, 6, 7, 8, 9, 10 nm are depicted in Figure 8a,b, respectively. With the reduction in t from 10 to 4 nm, a leftward shift in the transfer curves is observed, resulting in the threshold voltage being transformed from 3.79 V to −2.3 V, and during this process, the output current density drops from 486 mA/mm to 199 mA/mm. In Figure 8c, the threshold gate voltage and drain current density are plotted against different values of t. As the t reduces, the device transitions from depletion mode (D-mode) to E-mode, resulting in a decrease in output current density. The results presented in Figure 8 clearly indicate that the shallow trench sacrifices output current density in exchange for an increased transistor safety threshold. Band diagrams with different values of t are simulated to study the effects of t on V_th shift, as shown in Figure 9. Valence band diagrams in the channel region are under the fermi level at t of 6, 5, and 4 nm, indicating that the hole concentrations in the channel are depleted, resulting in enhancement mode performance. In addition, the downward shift in the valence band with decrement of t, leading to the depletion of holes beneath the gate, thereby shifting the threshold voltage to the left. We carefully balanced the threshold gate voltage and drain current density, ultimately selecting a residual thickness of p-GaN layer of 6 nm beneath the gate with a V_th of −0.44 V, to ensure the device could be turned off efficiently. Simultaneously, a larger drain current density of 241 mA/mm was maintained (@V_GS = −10 V, V_DS = −10 V).

3.4. Temperature-Dependent Characteristics on the HEB-PFET

The characteristics of the HEB-PFET under different temperature conditions were simulated to understand the thermal stability of the device. Figure 10a presents the temperature-dependent transfer characteristics of the HEB-PFET. Notably, as the temperature increases from 300 K to 425 K, there is a positive shift in the threshold voltage of the HEB-PFET, changing from −0.44 V to −0.21 V. With the temperature transition from 300 K to 425 K, the subthreshold swing changed from 271 mV/dec to 277 mV/dec with little change. As can be noticed from Figure 10b, output current density increases from 30 mA/mm to 49 mA/mm (@V_GS = −10 V, V_DS = −6 V) with temperature increases from 300 K to 425 K, which is consistent with the phenomenon observed in reference [18]. This increase is likely a result of the enhanced thermal emission of holes [13], which becomes more pronounced at elevated temperatures. Thus, the proposed device exhibits good thermal stability.

3.5. A Semi-Empirical Compact Model for I_D of HEB-PFET

In order to further analyze the performance of the HEB-PFET, a semi-empirical compact model is proposed to describe the I_D (@|V_DS| > V_BE0), which combines the current model of the conventional p-FET [30] and the model of the HBT current gain β [29]. The I_D of the proposed HEB-PFET is i_d$·$β, where id describes the current of the conventional p-FET and β is the current gain of the AlGaN/GaN HBT. The i_d is defined as follows [30]:

In linear region (V_DS > V_GS − V_TH)

$$-{\mathrm{i}}_{\mathrm{d}}={\mu }_{\mathrm{p}}{\mathrm{C}}_{\mathrm{ox}}{\displaystyle \frac{W_{\mathrm{G}}}{L_{\mathrm{G}}}}\left[\right({\mathrm{V}}_{\mathrm{GS}}-{\mathrm{V}}_{\mathrm{TH}}){\mathrm{V}}_{\mathrm{DS}}-{\displaystyle \frac{1}{2}}{{\mathrm{V}}^2}_{\mathrm{DS}}]$$

(2)

In saturated region (V_DS ≤ V_GS − V_TH)

$$-{\mathrm{i}}_{\mathrm{d}}={\displaystyle \frac{1}{2}}{\mu }_{\mathrm{p}}{\mathrm{C}}_{\mathrm{ox}}{\displaystyle \frac{W_{\mathrm{G}}}{L_{\mathrm{G}}}}{({\mathrm{V}}_{\mathrm{GS}}-{\mathrm{V}}_{\mathrm{TH}})}^2$$

(3)

In Formulas (2) and (3), μ_p is the hole mobility, W_G and L_G are the width and length of the gate, C_ox = (ε_ox/t_ox) is the capacitances across the Al₂O₃ layers. V_TH is the threshold voltage of the conventional p-FET, any further drain-induced threshold shift is accounted for by shifting V_TH = V_T0 − δV_DS from its low-bias value V_T0 [8].

In addition, β is given below:

$$\beta ={\displaystyle \frac{{\mathrm{N}}_{\mathrm{E}}{\mathrm{t}}_{\mathrm{E}}}{{\mathrm{N}}_{\mathrm{B}}{\mathrm{t}}_{\mathrm{B}}}}·{\displaystyle \frac{{\mathrm{D}}_{\mathrm{nB}}}{{\mathrm{D}}_{\mathrm{pE}}}}·\mathrm{a}·{\displaystyle \frac{1+\mathrm{n}\exp \left(\frac{{\mathrm{V}}_{\mathrm{DS}}-{\mathrm{V}}_0}{\mathrm{k}}\right)}{1+\exp \left(\frac{{\mathrm{V}}_{\mathrm{DS}}-{\mathrm{V}}_0}{\mathrm{k}}\right)}}$$

(4)

The thickness and concentration of the p-GaN and Al_0.2Ga_0.8N layer under the drain are denoted as t_B, t_E, N_B and N_E, respectively. D_pE and D_nB are the diffusion coefficients of holes and electrons in the Al_0.2Ga_0.8N layer under the drain and p-GaN. V₀ is considered to be the voltage threshold that marks the beginning of transistor amplification. The a, n, and k are all constants related to V_GS.

The basic part of the model, i_d is a formula widely used to describe the current behavior of conventional p-FETs in different operating regions (linear region and saturated region) [30]. Then, the second part of the model, β describes the current gain effect due to the integrated AlGaN/GaN HBT at the drain side. The parameters a, n and k are introduced to characterize the electrical behavior of the HBT, which are dependent on the variation of V_GS, reflecting the amplification effects of the triode at different gate source voltages.

Figure 11 presents the fitting diagram between the predicted values of the model and the simulated values. The model, which combines the current model of the conventional p-FET and the model of the HBT current gain β, intuitively explains the working principle of HEB-PFET. It not only provides a powerful tool for predicting and optimizing the electrical characteristics of the HEB-PFET, but also offers new perspectives and ideas for the design of GaN p-FET devices.

4. Conclusions

In summary, a novel e-mode HEB-PFET structure is demonstrated to advance the state-of-the-art for GaN p-FETs in current level. The simulation results indicate that the integration of a AlGaN/GaN HBT can amplify current density by a factor of 134 and 2.4 compared with C-PFET and HOB-PFET, respectively. The optimized HEB-PFET with 6 nm p-GaN layer underneath the gate exhibits 241 mA/mm drain current density, with V_th of −0.44 V and I_on/I_off of >10¹¹. Additionally, the proposed HEB-PFET shows a good thermal stability when the temperature changes from 300 K to 425 K, where the V_th shows a 0.23 V increase, the subthreshold voltage shows only a 6 mV/dec increment, and the output current density shows a 19 mA/mm increase. A semi-empirical compact model is proposed to predict the current characteristics of the devices. Therefore, the HEB-PFET is a very attractive device that can be integrated with commercial p-GaN gate HEMT to form GaN based CMOS. Future research will concentrate on fabricating the proposed device, with a focus on the growth of GaN/AlGaN heterostructure with high concentration of holes, minimizing etching damage, and optimization of ohmic contact of source side.