Design, Fabrication, and Characterization of a PTAT Sensor Using CMOS Technology

Abstract

This paper presents the design of an integrated temperature sensor. The sensor was manufactured using the 3 µm CMOS technology. The proportional to absolute temperature sensor output signal was produced by two MOS transistors with biasing and buffering circuits. The sensor output voltage was linearly proportional to the absolute temperature in a wide range of temperature values. The measurement results coincide very well with the results of the process corner analysis. Certain non-linearities occurring at high temperature values are investigated in this paper in more detail. Additionally, the influence of neighboring circuits present in the manufactured integrated circuit on the sensor temperature response is studied.

1. Introduction

At present, the rapid development of microelectronic technology is being observed. Microprocessors and electronic systems contain more and more transistors on a single chip, e.g., the latest Apple M2 Max consists of 67 billion transistors [1]. Consequently, Moore’s law, stating that the number of transistors on a single chip doubles every two years, is still valid [2,3]. However, the ever-growing density of dissipated power and operating frequencies exceeding 3 GHz increase integrated circuit (IC) temperatures. Thus, at present, many circuits require continuous temperature monitoring by internal integrated sensors. Such sensors, owing to their small size, can be used to measure the temperature inside a chip close to heat sources in various ICs, including application-specific integrated circuits (ASICs) [4]. Moreover, the operating temperature range of these sensors is very wide, typically from −50 °C to +180 °C.

Integrated temperature sensors can be achieved in many different ways, e.g., as p-n diodes [5], oscillators [6], bipolar transistors [7], or proportional to absolute temperature (PTAT) sensors [8,9,10,11,12,13]. According to the amount of dissipated, one could distinguish also low-power temperature sensors [14,15,16]. Temperature sensors can be used for various purposes, including IC overheat protection [17] as well as in Internet of Things (IoT) [18] and embedded [19,20] or space applications [16].

Definitely, the smallest temperature sensor is a simple p-n junction operating under low forward bias so as to avoid self-heating effects. Then, the voltage across the junction drops with the temperature, but this dependence might be non-linear. Quite the opposite, PTAT sensors, consisting usually of two appropriately connected transistors together with a biasing circuit and a buffering output stage, yield output signals that are linearly dependent on the temperature, which simplifies greatly the readout circuitry. Therefore, the authors decided to verify the operation of this kind of sensor in practice.

Although the idea of the PTAT sensor is known, its implementation in the chosen CMOS technology is a novelty. The achieved results show that the sensor works linearly in a wide range of temperature values. Detailed analyses show that non-linearities appear in the high temperature range, and this phenomenon is discussed further in this paper.

Another goal of this work is to test the possibility of manufacturing small series of analog circuits in the technology offered by a research institute in Poland providing various services related to IC design, multi-project wafer (MPW) prototyping, testing, and manufacturing of both ASICs and micro-electro-mechanical systems (MEMSs) [21]. At present, this technological line is undergoing modernization focused on enhancing the technology line with new MEMS manufacturing capabilities.

Although the characteristic dimension of this complementary metal–oxide–semiconductor (CMOS) process is large (3 µm), such a technology still might be useful for some specific niche applications and small- or middle-sized clients who want to order, at affordable prices, small batches of ICs for commercial or research purposes. Moreover, as a partly experimental process, it allows for the modifications of technological steps and process parameters, so as to suit some specific requirements of customers developing custom prototype solutions and allowing them to protect proprietary information.

This is also a case in this paper, in which the authors aim at testing the stability and capabilities of this technology as a mean for the rapid design and manufacturing of small ASIC series for research projects with the possibility of future commercialization in cooperation with companies. In particular, the test ASIC investigated in this paper is designed in order to become accustomed with the offered technology, and it contains, among others, an array of memory cells dedicated to the detection of single-event upsets (SEUs), which require the modification of standard technological steps [22].

Taking into account that this ASIC requires the continuous monitoring of its temperature, a CMOS PTAT sensor is also included in it. This circuit, as presented in this paper, is characterized and thoroughly tested. The following section covers briefly the PTAT sensor’s principles of operation. Then, the detailed sensor design is provided. Finally, the simulation and measurement results are compared. In particular, the sensor linearity is assessed and the influence of neighboring circuits is studied.

2. Principle of Operation

Various practical realizations of PTAT sensors, in which the resulting output voltage is proportional to the absolute temperature, are provided in the literature [8,9,10,11,12,13]. The original designs are based on bipolar transistors or p-n diodes of different sizes. One can also find solutions based only on the MOS transistors, which are achieved in CMOS technologies [23,24,25,26,27]. In such sensors, the PTAT voltage source consists of two n-type metal–oxide–semiconductor (NMOS) transistors, as presented in Figure 1. When two separate current sources are used, as in Figure 1a, both transistors operate in the weak inversion region and, then, one can derive the following equation [8]:

$$V_{ptat}=\frac{kT}{q}\ln \left(1+\frac{I_1+I_2}{I_1}\frac{\raisebox{1ex}{$W_1$}\!\left/ \!\raisebox{-1ex}{$L_1$}\right.}{\raisebox{1ex}{$W_2$}\!\left/ \!\raisebox{-1ex}{$L_2$}\right.}\right)$$

(1)

where V_ptat—output voltage; T—absolute temperature; k—the Boltzmann constant; q—elementary charge; W₁, W₂, L₁, and L₂—the respective widths and lengths of transistor M1 and M2 channels; and I₁ and I₂—source currents.

The output sensor voltage V_ptat in this equation is linearly dependent on the absolute temperature. The linear coefficient value depends on the MOS transistor aspect ratio W/L and the value of the source currents I₁ and I₂. The main advantages of this kind of sensor are its low-power dissipation and the small layout area.

When only one current source is used, as in Figure 1b, the output voltage is equal to [9,28]:

$$V_{ptat}=\frac{T}{T_R} \sqrt{\frac{2I_R}{S n_R {\mu }_R C_{ox}}}$$

(2)

where T—absolute temperature, T_R—reference temperature (300 K), I_R—drain current at the reference temperature, S—W/L ratio (lower transistor M4), n_R—subthreshold slope factor at the reference temperature, µ_R—effective electron mobility at the reference temperature, C_OX—NMOS gate oxide capacitance.

3. Sensor Design

The PTAT sensor, as mentioned before, was designed as a part of a larger test ASIC manufactured using the 5 V 3 µm CMOS technology available in Poland. The ASIC was mounted in a ceramic DIL-40 package (Lukasiewicz Institute, Warsaw, Poland). The ASIC layout and its microscopic photograph taken with its package lid open are shown in Figure 2. The exact dimensions of the silicon die were 2080 μm × 2160 μm. The location of PTAT sensor, which is the main interest in this paper, is indicated in the figure with yellow boxes.

The electrical schematic of the PTAT sensor and its layout are presented in Figure 3. As it can be seen, it contains several blocks, including the diode-connected MOS providing sensor bias, two current mirrors, the actual PTAT voltage source, and the output stage. Taking into account the unavailability of bipolar transistors in the particular technology considered in this paper, only MOS transistors were used in the design. The entire PTAT sensor layout had the dimensions of 440 μm × 275 μm and it occupied an area of 0.121 mm², which is just 2.7% of the entire chip area.

The ASIC that contains the PTAT sensor is composed of several functional blocks having separate power supply and ground lines. Thus, the influence of other components on the PTAT sensor can be eliminated simply by not powering them. The PTAT sensor is placed close to one of the ASIC corners (Figure 2). Such a location additionally minimizes the influence of other heat sources in the ASIC when they are powered. On the other hand, the PTAT is placed close to the electro-thermal filter (ETF). Both the resistor heater and the thermopile in this device can be used as heat sources with controlled power levels. Thus, it is possible to record the reaction of the PTAT sensor due to the dissipation of known amounts of energy in the proximity of the PTAT sensor.

Moreover, the electro-static discharge (ESD) protection devices of the ETF heater and thermopile are placed next to the PTAT sensor. Owing to such a location, the ESD devices also can be used as heat sources for the PTAT when the ETF is driven with currents that are high enough to switch on the ESD devices. This mode of operation was tested several times and the paper includes results obtained with activated ESD devices. Such an activation is safe and fully reversible when the ETF components are current-driven. The current–voltage characteristics of the ESD devices are highly non-linear and the current control mode enables a much better control of power dissipation in these devices.

Assuming a power dissipation limit of less than 0.5 mW for the nominal supply voltage of 5 V, it yields a maximal current equal to 100 µA. This assumption resulted in the PTAT electrical schematic presented in Figure 3. The main part of the sensor consists of two NMOS transistors M5 and M60, where the latter transistor has the aspect ratio W/L equal to 20 μm/120 μm. The M7 transistor biases the M1 and M3 transistors with the current of 8.5 μA. Together with the M2 and M4 transistors, they form a cascode current mirror replicating the current flowing through its left part. Owing to the cascode’s high resistance, independent of the circuit temperature or technology, the cascode ensures a high output sensor linearity [29,30]. The second current mirror formed by the M8 and M9 transistors was used in this paper for reversing the current that flowed through the M5 and M60 transistors. Because of the use of micrometer-sized technology, various channel length modulation and drain-induced barrier-lowering effects, discussed in [31], could be neglected in this paper. The output stage rendered the entire sensor less sensitive to the external readout circuitry.

4. Simulation and Measurement

Before the ASIC manufacturing, the PTAT sensor operation was simulated in the Cadence environment [32]. The results of corner analysis, presented in Figure 4, show that, in spite of the process parameter spread, the output voltage linearity remains virtually the same in a wide range of temperature values, from −25 °C to +125 °C. Namely, the PTAT sensor output voltage level shift between the maximal corner and the minimal corner is about 260 mV, but the sensor output voltage changes due to the temperature variation within the considered range are 217 mV and 221 mV for the respective corners.

The actual dependence of the PTAT sensor voltage on the temperature was measured in the climate chamber Binder MKF 115 presented in Figure 5a. This chamber allows temperature measurements from −40 °C, to +180 °C with the pre-set air humidity value between 10% and 98% [33]. The measurements were taken for several ASIC samples in the temperature range from −40 °C to +150 °C.

First, the ASICs were placed in the chamber, cooled to −40 °C, and then maintained at this temperature for 20 min. Next, the temperature was ramped linearly up to +150 °C taking measurements during the heating process. Owing to the slow rate of the temperature increase of less than 1 °C/min, it was possible to ensure a low temperature difference between the environment and the measured ASICs. Moreover, in order to further minimize this difference, the measurements were taken with the package lid removed and the die exposed directly to the environment, as shown in Figure 5b.

Each measurement session lasted nearly 6 h in order to acquire an output signal of high resolution. The actual measurements of the PTAT output voltage were taken with the resolution of 0.1 °C, but in this section, for the sake of picture clarity, the charts present the results at 5 °C intervals. Figure 6a comprises the measurement results for eight PTAT specimens named according to the pattern AXX (solid lines with markers). The letters and numbers denote particular ASIC specimens, each of them containing a single PTAT sensor. All these ASICs were supposed to be identical and behave in the same manner.

The measurement results were compared with the post-layout simulation results performed for the minimum, typical, and maximum corners (dotted lines). Post-layout simulations were carried out using parameters extracted based on the knowledge of IC layout and its geometry. The parameter extraction procedure provided information on parasitic resistances and capacitances identified in the IC geometry. The resulting netlist comprised all these parasitic devices and rendered possible more accurate analyses of circuit operation in both the direct current (DC) and alternating current (AC) domains.

As it can be observed in Figure 6a, the measured results are within the limits set by the post-layout simulation corners and primarily lie between the typical and maximum corners. The PTAT sensor output voltage linearity can be more precisely assessed by analyzing Figure 6b and comparing the derivatives of this voltage with respect to the temperature for all measured specimens (solid lines with markers) with the ones calculated based on the post-layout simulation (grey circles). The output voltage derivatives emphasize the non-linear effects, what makes the analysis more effective. As it can be seen, the sensor output voltage does not depend linearly on the temperature throughout the entire temperature measurement range, since the simulated sensitivity gradually increases, especially for temperature values exceeding 100 °C. The derivatives calculated based on the measurements, though very noisy due to the limited precision of meters, match quite well the simulated values.

5. Result Analysis and Discussion

Firstly, the linearity of the sensor was assessed by adding trendlines and calculating the determination coefficient R² values for each curve in Figure 6a. The linear fitting results are also summarized in

Table 1. Linear fitting results of the PTAT output voltage temperature dependences presented in Figure 6a.

Chip Specimen	The Determination Coefficient—R²	Fitting Equations of the PTAT Output Voltage Thermal Dependence
Post-layout simulation	0.9996	y = 1.4547 × T + 568.5157
A01	0.9998	y = 1.3259 × T + 578.5363
A02	0.9993	y = 1.4236 × T + 631.8302
A03	0.9996	y = 1.3384 × T + 576.1250
A04	0.9998	y = 1.3382 × T + 588.1372
A10	0.9981	y = 1.4549 × T + 663.3609
A0C High current	0.9997	y = 1.3342 × T + 584.0633
A0D	0.9983	y = 1.4697 × T + 680.1295
A0E	0.9998	y = 1.4247 × T + 653.8753
A0C Low current	0.9998	y = 1.3444 × T + 577.1225

. As it can be seen, the determination coefficient values calculated for the measured and simulated values agree very well. Although the fitting results seem satisfactory, some non-linearity can be observed, especially at higher temperature values.

According to Equation (2), a linear thermal dependence of the PTAT sensor output voltage on the temperature should be expected, i.e., the derivative values in Figure 6b should be constant. On the other hand, both the post-layout simulation and the measurements show that these values increase with the temperature. Hence, this issue was investigated in more detail in the remainder of this paper.

For this reason, first- and third-order polynomial fittings were carried out for the data concerned in Figure 6b. The latter fitting was expected to better represent the measured values. The results of this fitting are presented in Figure 7 and

Table 2. Fitting results of the PTAT output voltage temperature dependence derivative in Figure 7.

Chip Specimen	The Determination Coefficient—R²	Fitting Equations of the PTAT Output Voltage Thermal Dependence Derivative
Post-layout simulation	0.9985 0.9969	y = 0.0011 × T + 1.3949 y = 2.32 × 10−8 × T3 − 3.41 × 10−6 × T2 + 1.18 × 10−3 × T + 1.40
A01	0.0384 0.1313	y = 0.0006 × T + 1.2830 y = 1.57 × 10−7 × T3 − 2.48 × 10−5 × T2 + 1.28 × 10−3 × T + 1.30
A02	0.1507 0.4995	y = 0.0007 × T + 1.3657 y = 2.48 × 10−7 × T3 − 2.66 × 10−5 × T2 + 7.98 × 10−4 × T + 1.38
A03	0.2140 0.3103	y = 0.0013 × T + 1.2602 y = 2.26 × 10−7 × T3 − 4.17 × 10−5 × T2 + 2.62 × 10−3 × T + 1.29
A04	0.0746 0.2320	y = 0.0007 × T + 1.2934 y = 1.49 × 10−7 × T3 − 2.28 × 10−5 × T2 + 1.24 × 10−3 × T + 1.31
A10	0.1051 0.7181	y = 0.0009 × T + 1.3654 y = 5.13 × 10−7 × T3 − 5.81 × 10−5 × T2 + 1.25 × 10−3 × T + 1.40
A0C High current	0.0264 0.0686	y = 0.0008 × T + 1.2904 y = 1.41 × 10−7 × T3 − 2.16 × 10−5 × T2 + 1.17 × 10−3 × T + 1.31
A0D	0.1637 0.6757	y = 0.0011 × T + 1.3786 y = 2.70 × 10−7 × T3 − 2.20 × 10−5 × T2 + 6.17 × 10−4 × T + 1.40
A0E	0.0094 0.1175	y = 0.0003 × T + 1.4021 y = 6.07 × 10−8 × T3 + 1.75 × 10−7 × T2–2.94 × 10−4 × T + 1.40
A0C Low current	0.0221 0.1268	y = 0.0004 × T + 1.3073 y = 1.09 × 10−7 × T3 − 1.52 × 10−5 × T2 + 8.53 × 10−4 × T + 1.32

. The trendlines, as it can be seen, for any type of fitting can be divided into two distinct sets having different line slopes, flatter and steeper than the simulated trendline. Furthermore, the differences among the various ASIC specimens become even more pronounced at high temperature values. This might result from the fact that the tested chips belonged to different manufacturing batches.

Non-linear effects are visible both in the results of the MAX corner simulation and the measurements. Additionally, this phenomenon was reproduced in the simulations, assuming that the PMOS transistors widths were greater than their nominal values (see the green line in Figure 8). Then, the drain current of transistor M9, visible in Figure 3, decreases at high temperature values and this device leaves the saturation region of its operation. On the other hand, the drain current of transistor M60 remains unchanged. This current difference is compensated by the current provided from the output stage of the PTAT sensor, which changes the output voltage. This occurs at temperature values exceeding 100 °C. Therefore, the non-linearities observed at high temperature values for some ASICs could be attributed to the technological process, rather than to the errors in the sensor design.

Additionally, the PTAT sensor behavior was analyzed using, instead of the climate chamber, the neighboring ETF and its ESD protection circuitry, highlighted by yellow boxes in Figure 9, which served as the heat sources. The ETF itself consists of a diffusion resistor heater and a temperature-sensing thermopile. For the sinusoidal excitation, the phase shift introduced by this device depends linearly on the temperature; thus, it can be used also as a temperature sensor [34]. The influence of the ETF on the PTAT sensor operation can be observed already in Figure 6, which presents two different measurements of the A0C specimen taken for low and high bias currents of the ETF heater and thermopile, denoted as LC and HC, respectively. The low current values were the same both for the heater and the thermopile and equal to 31.6 µA. The high current values were determined by the maximum voltage allowed at the temperature of 150 °C. These values amounted to 3.1 mA for the heater and 4.4 mA for the thermopile.

More detailed analyses of Figure 6a show that the low and high current thermal responses for the A0C specimen look nearly identical, but they are just shifted by about 5 °C from each other. This can be better observed in Figure 10a, which shows the measured temperature responses for the cases considered in this paper in the range of temperature from 0 °C to +50 °C. Additionally, the low current response shifted by 5 °C is also presented here. As it can be seen, after shifting, both PTAT sensor responses are almost identical.

These analyses provided the incentive to conduct more thorough investigations of the PTAT output voltage dependence on the ETF heater current. Indeed, the measurements carried out for the A04 specimen, whose ASIC results are presented in Figure 10b, showed that the PTAT output voltage increased with the heater current and, for the value of 10 mA, the voltage change exceeded 7 mV.

Analyzing the operation of the ETF, as shown in Figure 11a, the output voltage generated by the thermopile increases with the heater current, but at the current value of slightly above 4 mA, the ETF voltage response saturates and finally sets at the value of about 5.8 V. This phenomenon can be explained by the activation of the ESD protection circuitry built in the heater input pad and consisting of two oppositely connected diodes sinking the excessive input current whenever an overvoltage event occurs.

The dependence of the PTAT output voltage on the ETF heater current was measured altogether for three different ASICs, A03, A04, and A0C, at least twice for each specimen. Then, using the linear fit equations presented in Table 2, the temperature measurement errors due to the observed PTAT sensor output voltage shift were calculated. The results of these calculations are presented in Figure 11b. Although the repeated measurement sessions in the case of each particular ASIC produced nearly identical results, there were clear differences between the different ASICs. Considering the temperature measurement error values, for the heater current of 10 mA, they amounted to 6 °C.

An additional check was performed also for whether the thermopile current influenced the PTAT output voltage. During these tests, both the ETF thermopile and the heating resistor were used for heating, or either of these devices. The obtained results were always referenced to the case when the ETF was not active. The heating resistor and thermopile current values during tests were equal to 3.1 mA and 4.4 mA, respectively; thus, they were identical to the earlier determined high bias current values for the A0C ASIC.

Then, considering that their resistances were equal to 1350 Ω and 950 Ω, the respective power values were 13.0 mW for the heater and 18.4 mW for the thermopile, yielding a dissipated power ratio of around 1.42. At the same time, the calculated temperature measurement error ratio was equal to 1.38; hence, the currents of both ETF devices have a comparable influence on the PTAT sensor measurement errors.

Similar experiments were also carried out with the A04 ASIC specimen. The results of all tests are summarized in

Table 3. PTAT output voltage variation and temperature measurement errors due to the ETF current.

High ETF Current Values	ΔV (PTAT) (V)		ΔT (°C)
	A04	A0C	A04	A0C
None	0	0	0	0
Heater	2.251	2.855	1.718	2.179
Thermopile	3.715	3.951	2.836	3.016
Heater + thermopile	5.885	6.222	4.492	4.749

. The PTAT sensor voltage shift and the resulting temperature measurement errors, as it can be seen, are comparable for both tested ASIC specimens, although the A0C one seems to be slightly more affected by the ETF current heating.

Therefore, the PTAT sensor investigated in this paper was compared with selected previous publications presenting similar sensors manufactured using CMOS technologies. The data presented in

Table 4. Various PTAT sensors’ comparison.

	This Work	Rossi et al. [10]	De Vita et al. [31]	Leung et al. [35]	Tso-Sheng Tsai et al. [23]
CMOS technology (µm)	3.0	0.8	0.35	0.35	0.18
Sensor layout (mm2)	0.121	NA	0.045	0.240	0.00126
Temperature range (°C)	−50 ÷ 150	−30 ÷ 100	0 ÷ 80	0 ÷ 100	−60 ÷ 140
R2	0.999	NA	NA	NA	0.993

show that, in spite of the apparently obsolete technology used for the design of the sensor, its layout area is fairly small and, what is even more important, its output characteristics are linear in a wide range of temperature values.

6. Conclusions

This paper presented a PTAT sensor designed and manufactured entirely using CMOS technology. The sensor operation was tested in the wide range of temperature values. The measurements carried out for several specimens of manufactured circuits confirmed the proper sensor operation. Its characteristics fell well within the limits defined by the post-layout corner simulations. Moreover, the output signal of the PTAT sensor turned out to be nearly linear over a wide temperature range. Thus, this technology can be considered repeatable and suitable for the production of small batches of analogue ICs.

However, the measurements showed that the apparent spread of the PTAT output voltage may require initial calibration in the case when the PTAT sensors are supposed to directly provide information on the temperature. Nevertheless, considering the measured temperature dependence of the PTAT output voltage, such a calibration should be rather a straightforward procedure. However, it should be noted that there are differences between various specimens of the measured PTAT, which seem to group them into a few batches. Thus, taking into account the process parameter spread, all PTAT sensors must be individually calibrated, especially for temperatures values exceeding 100 °C, when non-linear effects are observed.

The PTAT voltage source in the investigated sensor was generated by the M5 transistor operating in the saturation region and the M60 transistor operating in the linear region. The main advantage of this solution is a more stable operation and better immunity to the process parameter spread than in the solution when both transistors operate in the subthreshold region. The transistors in the output stage could be rescaled, influencing in this way the output voltage offset.

Furthermore, the experiments demonstrated that, in integrated circuits, which combine several analogue subcircuits, special precautions have to be undertaken, so that the components do not interfere with each other. In particular, it was shown that the PTAT sensor output response can be affected by the currents used for the powering of the ETF heating resistor and biasing its sensing thermopile. Future work should be focused on the redesign of the PTAT sensor in order to reduce its size and minimize the effect of non-linear behavior in higher temperatures, which was identified in this work.