A Configurable Resolution Time-to-Digital Converter with Low PVT Sensitivity for LiDAR Applications

Abstract

This paper presents an all-digital and configurable resolution time-to-digital converter (TDC) with low process–voltage–temperature (PVT) sensitivity for light detection and ranging (LiDAR) applications. The proposed TDC offers configurable resolution, allowing it to provide an appropriate conversion resolution according to the system’s requirements, thereby optimizing overall system performance. In addition, because the proposed TDC has high immunity to process–voltage–temperature (PVT) variations, it provides more stable time-converting results. The proposed design uses 0.18 μm CMOS technology, and the measurement results demonstrate a resolution ranging from 36 ps to 1193 ps, with a conversion range from 0.1 ns to 36 ns and an average error of 20.59 ps. Furthermore, the proposed TDC is implemented in an all-digital manner, making it highly suitable for system integration.

1. Introduction

Distance measurement is a crucial task in both everyday life and scientific research. The results obtained from distance measurements can be used for various purposes, such as navigation, mapping, and object identification. Time-correlated single-photon counting (TCSPC) systems are extensively used for distance measurement and ranging applications [1,2,3]. One of the most notable applications of TCSPC systems is in light detection and ranging (LiDAR) systems. LiDAR is an optical remote sensing technique that uses pulsed laser light to measure the distance to a target. LiDAR is commonly used in time-to-flight (ToF) applications, including advanced driver assistance systems (ADASs), space exploration, crop production monitoring, natural environment monitoring, and smart factories [4,5,6,7,8].

Figure 1 shows the functional block diagram of ToF sensors, which consist of a pulsed laser driver, transmitter optics, receiver optics, a single-photon avalanche diode (SPAD) array, and time-to-digital converters (TDCs). The pulsed laser driver generates a trigger signal to activate the pulsed laser. The laser light is transmitted to the object through the transmitter optics, and the trigger signal is sent to the TDC simultaneously. After emitting laser light to the object, it reflects and returns to the receiver optics. By measuring the travel time of the laser light, the distance between the object and the transmitter can be calculated. The TDC is a critical component of LiDAR systems, as it directly impacts the overall performance of the system, including distance detection range, resolution, and precision. In LiDAR design, the detection distance range is a crucial specification, and the maximum and minimum detection distances are determined by the longest and shortest detection times of the TDC, respectively. The TDC’s time resolution plays a crucial role in determining the distance detection resolution of the LiDAR system. A higher TDC time resolution leads to an improved distance detection resolution. Additionally, the LiDAR system aims to enhance measurement stability with high detection precision. If the operating environment easily affects the conversion results of the TDC, the LiDAR system will not provide high measurement stability.

Several structures have been proposed for implementing a TDC in LiDAR applications [9,10,11,12]. The flash TDC is a simple and straightforward method that uses a delay chain and flip-flops to measure input time intervals. However, its quantization resolution is limited by the propagation delay of the delay circuit, making it difficult to achieve high time resolution [13]. The Vernier TDC achieves higher resolution due to the delay difference between the two delay circuits of the delay chains. However, a longer delay line length is required for a larger detectable time interval, resulting in higher hardware costs when using the Vernier TDC to provide a wider detectable range [13]. Although the ring oscillator Vernier and cyclic Vernier TDC use the Vernier delay chain and counter to achieve both fine resolution and a wide range, these two structures present some design challenges such as high complexity, high power consumption, and high switching noise.

Designing a single TDC that meets the diverse specifications required by LiDAR applications is a significant challenge. Many of these specifications require trade-offs from a circuit design perspective. To address these issues, this paper proposes a TDC architecture with configurable resolution. The maximum detectable time of this architecture varies depending on the selected resolution: higher resolutions have a shorter maximum detectable time, while lower resolutions have a longer maximum detectable time. Consequently, the system can select the most suitable TDC resolution based on its specific application requirements, thus avoiding unnecessary power consumption and hardware costs. Furthermore, both flash TDCs and Vernier TDCs rely on the delay of delay elements to determine their resolution. Unfortunately, these delay elements are susceptible to variations in process, voltage, and temperature (PVT), leading to fluctuations in the TDC’s resolution across different operating environments. This significantly degrades the TDC’s stability and consequently impacts LiDAR accuracy. The proposed TDC employs all-digital delay-locked loops (ADDLLs) to stabilize the delay of delay elements, thereby reducing their sensitivity to process variations, voltage fluctuations, and temperature shifts. Consequently, this approach enhances the overall stability of the TDC. As a result, the proposed TDC design not only significantly reduces the sensitivity of resolution to PVT variations but also provides a suitable resolution and conversion range according to the requirements of the system’s application, making it highly suitable for LiDAR applications.

This paper is structured as follows: Section 2 describes the proposed TDC architecture. Section 3 provides additional information on ADDLL operation, locking algorithms, and key module circuit design. Section 4 presents the experimental results obtained from implementing the designed TDC. Finally, Section 5 draws the conclusions.

2. TDC Architecture Overview

To achieve both high resolution and a wide conversion range simultaneously, the proposed TDC employs a two-stage conversion architecture, as illustrated in Figure 2. The proposed two-stage TDC consists of two conversion stages (Time Conversion Stage I and II), four ADDLLs (ADDLL I~IV), two signal selectors (Signal Selector I and II), and two pulse generators (Pulse Generator I and II). The pulse generators convert the input signal to a periodic signal to facilitate subsequent conversion stages. Time Conversion Stage I and Stage II are identical in circuit structure but differ in conversion resolution and range due to input digital control code settings. The first conversion stage (Time Conversion Stage I) has a lower resolution and a wider conversion range, while the second conversion stage (Time Conversion Stage II) has a higher resolution and a narrower conversion range. The conversion resolution and range of each conversion stage are determined by the delay of its internal delay elements, which in turn is determined by the digital delay control code generated by the ADDLL. Consequently, the primary function of the ADDLL is to generate the digital delay control code that governs the conversion resolution of the conversion stages. The signal selector serves as an interface circuit between the first and second conversion stages, with its primary function being to feed the residual time interval, quantified by the first conversion stage from the input signal time difference, into the second conversion stage for further quantization.

Figure 3 illustrates the operating sequence of the two-stage TDC. The operating procedure comprises two states: initialization and conversion. In the initial state, there are two main tasks to be performed: First, four ADDLLs (ADDLL I~V) generate the digital delay control codes (Delay Control Code I~IV) required for the delay elements within the conversion stages. The ADDLLs achieve locking based on the configured input clock signal period of the ADDLL (Ref_CLK I~IV). When ADDLL locking is complete, the corresponding digital delay control codes are output to the conversion stages. Second, the signal selectors convert the two input signals (Start, Stop) into corresponding periodic signals (Pulse_Start, Pulse_Stop). Once the TDC has completed initialization, it can proceed to the conversion stages. Since both conversion stages use a Vernier-type TDC architecture, each stage requires two different delays for its delay elements. Therefore, a total of four ADDLLs are required to set the required delays. The first conversion stage quantifies the time difference between the two input signals initially. Typically, reducing the quantization error requires a significant increase in the conversion resolution. However, to maintain the same conversion range, more delay elements and associated circuitry must be used, increasing the overall power consumption and hardware cost. To address these limitations, the proposed two-stage TDC employs a relay-based approach to quantization that effectively reduces the overall quantization error at a lower hardware cost. Upon completion of quantization in the first stage, the remaining unquantized portion is passed to the second stage for higher-resolution quantization. The signal selector chooses one of the delayed element outputs from the first conversion stage as the input signal for the second conversion stage based on the output of the first conversion stage. The time difference between the outputs of the two signal selectors (Start_Sel, Stop_Sel) represents the portion that has not been quantified yet. When both the first and second conversion stages output conversion digital codes (Code_Out I, II), it indicates that the TDC has completed the conversion process.

Figure 4 is used as an example to further illustrate the operation concept of the two-stage TDC. T_M is the time interval to be measured and is the time difference between the positive edge of the input signal Start and the positive edge of the input signal Stop. Pulse generators I and II generate Pulse_Start and Pulse_Stop, respectively, and the time difference between the first rising edge of Pulse_Start and Pulse_Stop is the same as T_M. In the Vernier-type TDC architecture of Time Conversion Stage I, there are delay elements with a larger delay denoted as T₁ and delay elements with a smaller delay denoted as T₂. The conversion resolution of Time Conversion Stage I is T₁ − T₂. If the length of T_M falls between 7 and 8 times T₁ − T₂, the signal selector chooses Start_D1[7] and Stop_D1[7] as outputs to Time Conversion Stage II, as illustrated in Figure 4. Basically, the circuit architecture and operational principles of the first and second conversion stages are the same. The difference lies in the conversion resolution of Time Conversion Stage II, denoted as T₃ − T₄, which is smaller than that of the first conversion stage, denoted as T₁ − T₂. The overall resolution of the TDC is contingent upon the discrepancy between T₃ and T₄.

3. Circuit Design

The four ADPLLs are constructed using the same circuit design. The differentiation is based on the varying input clock frequencies of the four ADPLLs, which enable them to generate the distinct digital control codes required by the corresponding time conversion stages. The ADDLL consists of a period-to-digital converter (PDC), a phase detector (PD), an ADDLL controller, and a digitally controlled delay line (DCDL). The ADDLL controller consists of a DCDL code converter, a delay control code generator, and an initial code generator, as shown in Figure 5. The overall ADDLL locking process is illustrated in Figure 6. Firstly, the PDC quantifies the period of the input clock signal (T_CLK) using the delay elements of the DCDL to generate the initial digital control code (Initial Code). This rapid acquisition of a control code close to the target value significantly reduces the time required for locking. Since the output code (P_Code) format of the PDC differs from the signal format required by the ADDLL controller, it is necessary to use an initial code generator for conversion. Once the initial control code is generated, the delay control code generator further refines the digital control code based on the output of the PD (UP, DN). By aligning the positive edges of the Ref_CLK and FB_CLK, the ADDLL is locked, meaning that the delay of the DCDL equals T_M [14]. Since the output code (Initial Code) format of the delay control code generator differs from the signal format required by the DCDL, it is necessary to use a DCDL code generator to convert the output code to Delay Control Code.

The DCDL consists of 10 identical delay elements (DEs), as illustrated in Figure 7. When the ADDLL is locked, the overall delay of the DCDL is equal to T_CLK. Therefore, the delay of each DE is one-tenth of T_CLK. As demonstrated in Figure 7, the ADDLL locking process effectively mitigates the impact of PVT variations on the delay of the delay elements. By maintaining a consistent input clock signal period, the ADDLL ensures that the DE delay remains stable and predictable.

The proposed delay element comprises four digital-controlled delay circuits (DCDCs), designated as the first, second, third, and fourth DCDCs, as illustrated in Figure 8. The digital control codes that regulate the DCDC delays within the DE are generated by the ADPLL controller. The first DCDC offers the highest delay resolution, followed by the second, third, and fourth DCDCs. Conversely, the fourth DCDC exhibits the widest controllable range, followed by the third, second, and first DCDCs. The first DCDC dynamically determines the delay introduced between its input and output by controlling the path length traversed by the input signal based on the first-stage control code (C1). The first DCDC architecture allows for straightforward expansion of the controllable range by increasing the number of buffers and multiplexers. However, this approach has limitations in terms of enhancing delay resolution due to the inherent logic gate delays of these components. To address this issue, subsequent DCDCs are employed to augment the overall delay resolution of the delay element [15]. The second DCDC employs a digital control code (C2) to regulate delay hysteresis and generate distinct delays. The second DCDC utilizes a concept akin to cross-coupled inverters to facilitate the adjustment of delay magnitude. The third and fourth DCDCs control the gate capacitance of the two-input NAND gate to generate varying delays. The gate capacitance is altered in a slight manner by the digital control codes (C3, C4), enabling the third and fourth DCDCs to achieve exceedingly high timing resolutions. The third- and fourth-stage DCDCs employ two-input NAND gates with different sizes (L and S) to achieve varying delay resolutions.

Table 1. The delay resolution and controllable range of each DCDC.

	1st DCDC	2nd DCDC	3rd DCDC	4th DCDC
Range (ps)	1595.2	578.5	223.4	26.3
Resolution (ps)	227.8	82.6	14.8	3.76

summarizes the post-layout simulation results for the delay resolution and controllable range of each DCDC stage. According to Table 1, it is confirmed that the controllable range of each DCDC is greater than the delay resolution of the previous stage, ensuring that there will be no delay change greater than the minimum resolution during specific control code transitions.

Time Conversion Stages I and II employ the Vernier TDC architecture, as illustrated in Figure 9. As the time conversion stages generate a thermometer code as their output, a code converter is necessary to transform the format into a binary one before being used in the output control code. The output control code comprises two components: output control Code_Out I and Code_Out_II. Code_Out I and Code_Out_II have lengths of 5 bits and 2 bits, respectively. Consequently, the output control code has a total length of 7 bits. The overall range and conversion resolution of the TDC are contingent upon the conversion range of Time Conversion Stage I and the conversion resolution of Time Conversion Stage II, respectively. It is thus imperative that Time Conversion Stages I and II be designed in accordance with the system’s specifications for the TDC. The time conversion stages employ a Vernier delay line architecture, resulting in a maximum conversion resolution that is determined by the delay difference between two delay elements with differing delay values within the subsystem. The conversion range is defined as the product of the number of delay elements and the maximum conversion resolution. Furthermore, the delay values of the delay elements within the proposed time conversion stages are dependent on the period of the external reference clock (Ref_CLK I~IV), allowing for adjustments to be made to meet system requirements. The conversion resolutions of Time Conversion Stages I and II are T₁ − T₂ and T₃ − T₄, respectively. Therefore, the relationship between the TDC output and the time difference between start and stop is as follows:

T_M = Code_Out I × (T₁ − T₂) + Code_Out II × (T₃ − T₄)

(1)

The delay elements within these stages share the same design as the delay elements in the ADDLL. Consequently, the delay of the delay elements remains unaffected by PVT variations. This ensures that the conversion resolution remains consistent across varying PVT conditions.

4. Experimental Results

The proposed two-stage TDC was fabricated using a 0.18 μm 1P6M CMOS process, with a core area of 890 × 890 μm² and a power consumption of 26.8 mW. Figure 10 presents a microphotograph of the proposed TDC design, indicating the fabrication of the chip. The figure highlights the placement and relative area occupied by each design module on the actual chip. For instance, the ADLLLs are situated at the four corners of the chip, while the remaining circuitry resides in the central region. Figure 11 illustrates the post-layout simulation results for the phase error of the ADDLL under typical (TT, 1.8 V, 25 °C), best (FF, 1.98 V, −40 °C), and worst (SS, 1.62 V, 125 °C) conditions, with the input clock period varying from 13.5 ns to 20 ns. According to the simulation results, the maximum phase error is 1.09%, occurring under the worst condition when the input clock period is 15 ns. The output signals for the test chip are measured using a digital oscilloscope at 1.8 V/25 °C. Upon achieving lock in the ADPLL, the generated delay control code is transmitted to the time conversion stages, where it sets the delay of the delay elements within the time conversion stages to one-tenth of the input clock period. T₁ and T₂ are the delay of the delay elements in Time Conversion Stage I, and T₃ and T₄ are the delay of the delay elements in Time Conversion Stage II. The overall resolution of the TDC is contingent upon the discrepancy between T₃ and T₄. Figure 12a shows the delay of two delay elements in Time Conversion Stage II when the input clock periods for ADDLL III and ADDLL IV are 24 ns and 24.4 ns, respectively. Since T₃ and T₄ are 2.442 ns and 2.406 ns, respectively, the resolution of the TDC is 36 ps. Figure 12b shows the delay of two delay elements in Time Conversion Stage II when the input clock periods for ADDLL III and ADDLL IV are 20.5 ns and 8.8 ns, respectively. Since T₃ and T₄ are 2.066 ns and 0.873 ns, respectively, the resolution of the TDC is 1193 ps. The resolution of the TDC can be adjusted by providing different clock periods to the input ADDLLs. This flexibility enables the TDC to achieve a wide range of resolutions, with the highest resolution achievable being 36 ps. Figure 13a and Figure 13b, respectively, show the measurement results for different input signal time intervals at resolutions of 36 ps and 1193 ps, with average errors of 20.59 ps. Figure 13a depicts the ideal conversion curve (blue line) of the input time interval. The discrepancy between the TDC conversion result (orange line) and the input time interval conversion result represents the TDC’s conversion error. To minimize the conversion error, it is possible to enhance the TDC’s maximum conversion resolution.

Table 2. Performance comparisons.

Performance Indices	Proposed	[11]	[6]	[4]
Process	0.18 μm CMOS	0.18 μm CMOS	0.18 μm CMOS	0.18 μm CMOS
Resolution (ps)	36~1190	40	48.8	208
Range (μs)	0.1~36	N/A	50	N/A
Number of Bits	7	11	12	12
Configurable Resolution	Yes	No	No	No
Power Consumption (mW)	28.4	2.19	0.3	N/A
Area	0.79 mm2	1350 μm2	4200 μm2	N/A
PVT Sensitivity	Low	Low	High	High

lists the performance comparisons with state-of-the-art TDCs for LiDAR system applications. Compared to other designs, the proposed TDC not only offers an adjustable resolution but also exhibits lower sensitivity to PVT variations, making it highly suitable for LiDAR applications.

5. Conclusions

The proposed TDC is designed with an adjustable resolution, allowing for the customization of the conversion resolution to align with the specific requirements of LiDAR systems. This capability eliminates the need for excessive design and cost, thereby expanding the applicability of this TDC. Additionally, the TDC’s conversion resolution remains unaffected by PVT variations, thereby enhancing the conversion’s stability and accuracy. Furthermore, the proposed design can be implemented using an all-digital approach, making it highly suitable for system integration.