Self-Balanced Switched-Capacitor Common-Grounding Boost Multilevel Inverter

Abstract

Transformerless inverters have been extensively deployed in photovoltaic (PV) applications, owing to features such as high efficiency, high power quality, and low cost. However, the leakage current in such inverters due to the absence of galvanic isolation has resulted in several topological modifications. This paper introduces a single-input switched-capacitor (SC)-based multilevel inverter (MLI) that is capable of eliminating the leakage current due to its common-ground structure. Also, the proposed inverter has the capability of single-stage voltage boosting, which is essential in PV systems. The series–parallel switching facilitates the self-balancing of SCs, which, in turn, assists in voltage boosting. Moreover, the proposed MLI synthesizes a seven-level output using only eight switches. Following an in-depth analysis of the circuit operation, modulation scheme, and power losses, a detailed comparison among recently developed seven-level MLIs is carried out, which verifies the design's superiority. Extensive simulation and experimental results are presented to validate the prominent features of the seven-level MLI under dynamic operating conditions.

1. Introduction

With the rapid industrialization and increased demand of renewable-based power generation, multilevel inverters (MLIs) are emerging [1,2]. In several applications, like photovoltaic (PV) power conversion systems, electric vehicles, and high-frequency power conversion systems, MLIs play a key role due to their attractive features, such as operation under a wide range of switching frequency, sinusoidal-like ac output, reduced dv/dt stress, etc. [3,4]. The well-known MLI topologies are flying capacitor (FC) MLI, neutral-point clamped (NPC) MLI, and cascaded H-bridge (CHB) MLI [5,6,7]. In addition to the complexity of voltage balancing, the requirements of a large number of capacitors and clamping diodes are major issues with the increases in voltage levels in FC and NPC MLIs, respectively [8,9]. On the other hand, CHB MLIs require several isolated dc sources and a large number of switches. Therefore, in view of PV applications, the widely debated issues are (a) the design of compact MLIs using a reduced number of components, (b) reducing the voltage stress, (c) attaining high-voltage boosting ac output from low-input dc, and (d) suppressing the high-frequency common-mode voltage (CMV).

To meet these objectives, switched-capacitor (SC)-based structures have been researched in the recent literature [4,10]. SCMLIs with a self-voltage balancing feature reduce the control complexity and assist in voltage boosting, utilizing a reduced number of dc sources and switches. To reduce the requirement of multiple sources, a recent study [11] proposed a single-input MLI consisting of series-connected capacitors. Although this circuit reduced the number of components for generating a seven-level output, voltage boosting was absent, and additional voltage balancing control was required to maintain the required voltage across the capacitors. To enable self-voltage balancing, the authors of [12] introduced a single-input CHB MLI structure that utilizes additional switches. These switches provide a path for the capacitors to be charged in parallel and discharged in series with the input to produce the required voltage levels. The series–parallel charge balancing principle was clearly discussed in [13], taking into account a new single-input SCMLI. This structure consisted of a level generation unit connected as the front-end circuit and a back-end H-bridge for synthesizing the negative-half output. A further optimized circuit in [14] reduced the number of switches by replacing a few switches with diodes. Conversely, series-connected diodes restrained the reactive power transfer capability. With a suitable arrangement of switches and diodes, a modular SCMLI structure was proposed in [15], comprising several SC units and a single input. Further, multi-input cascaded structures were derived that could operate in symmetrical and asymmetrical modes. The driver circuit requirement increased with the increase in the number of switches, which, in turn, made the design complex. This issue was resolved in [16] by introducing a new self-balanced SCMLI consisting of two H-bridge units. A new SCMLI topology proposed in [17] addressed the issues related to the inrush current during the capacitor charging. A recently proposed SCMLI in [18] featured single-phase and three-phase extendibility. The requirement of a full bridge at the back-end of the structures discussed above necessitates a higher rating of the switches; thus, the total standing voltage (TSV) is high.

In an attempt to reduce the voltage stress, further optimized SCMLIs have been proposed recently without using a full bridge. The circuits proposed in [10,19] minimized the overall stress. However, the former had a low voltage gain, and the latter required a greater number of switches. A new SCMLI in [20] greatly reduced the voltage stress, but at the cost of a large number of switches. The structures proposed in [21,22] also reduced the voltage stress by avoiding the H-bridge, but the circuit required a considerably greater number of capacitors.

Although the above-discussed boosting structures are suitable for single-stage transformerless PV applications, the leakage current due to the high-frequency CMV has adverse issues in such systems. Owing to the absence of galvanic isolation and the switching of a transformerless PV inverter, as shown in Figure 1, a time-varying voltage was introduced across the capacitance (C_pv). This, in turn, resulted in the flow of the ground leakage current depending on the values of capacitance and high-frequency CMV, which cause personal safety issues [23]. Several elegant solutions, such as those in the ac/dc decoupling technique [24], the pulse-width modulation scheme [25], active-neutral point clamped (ANPC) configurations [26,27,28,29,30,31,32], and common-ground (CG) configurations [33,34,35,36,37,38], have thus been proposed to mitigate this issue. The leakage current has been completely nullified (<5 mA), owing to the CG connection in [33,34,35,36,37,38], which satisfies the VDE 0126-01-01 grid code standard (<300 mA).

The designs of ANPC MLI and CGMLI are among the straightforward solutions addressing the issues of leakage current. The ANPC configuration maintains the CMV constant by connecting the ac-side neutral point to the mid-point of the decoupled dc-link, thereby reducing the leakage current. However, the voltage gain of these topologies is low. Therefore, SC-based CGMLIs are the ultimate choice to completely eliminate the leakage current by clamping the CMV to zero while retaining all other benefits. Figure 2 shows a few recently developed CGMLI configurations. The structures shown in Figure 2a,b require additional control for capacitor voltage balancing. Although the topology presented in Figure 2c has a self-balancing feature, it does not have a boosting ability while synthesizing a five-level output. The recently proposed CGMLIs shown in Figure 2d–f have the inherent voltage balancing and a boosting ability. However, the required number of switches is higher for synthesizing five-level and seven-level output. Despite several research efforts, concerns such as the component count, voltage stress, control complexity, boosting ability, inherent voltage balancing, etc. motivates the development of a new circuit configuration. A seven-level CGMLI based on the SC concept is proposed in this work as an elegant solution with the following key features:

• Single input source and only eight switches are required to synthesize triple-boost seven-level output.
• Self-voltage balancing of capacitors simplifies the control.
• Highly suitable in PV applications due to the common-grounding feature with zero CMV.
• Suitable operation under different loading conditions.

The remainder of the paper includes a detailed analysis and implementation of the proposed MLI. Section 2 includes the working principle and modulation scheme for the proposed MLI. Section 3 estimates the power losses in the proposed circuit, and Section 4 incorporates a thorough comparative analysis with prior-art MLIs. The detailed simulation and experimental results are shown in Section 5. Finally, Section 6 summarizes the work.

2. Principle of Operation of Proposed Seven-Level CGMLI

Figure 3a,b depict the recently developed circuits and their features. The first circuit is a CG-type MLI consisting of a level generation (LG) unit and a polarity generation (PG) unit. The LG unit creates two-step output with one capacitor, and the capacitor in the PG unit assists in synthesizing the required levels at the load. The circuit in Figure 3b utilizes a minimum number of switches in the LG unit to produce three-step output but without the CG feature. Hybridizing the concepts of these topologies, Figure 3c shows the configuration of the proposed seven-level CGMLI. The circuit is powered from a single input source (V_in), and the negative terminal of the source is directly connected to the ac-side neutral point. It consists of eight switches (S₁–S₈), three capacitors (C₁–C₃), and two diodes (D₁ and D₂). Except for switches S₂ and S₃, all other switches have built in anti-parallel diodes. The input side of the circuit consisting of two capacitors and four switches forms a novel SC circuit. Both the capacitors are charged to an equal magnitude of V_in by a simple series–parallel connection with the dc source. This module, along with the input voltage, can boost the voltage to three times the input. Additionally, the module consisting of capacitor C₃, which acts as virtual dc bus, assists in the synthesis of the negative half-cycle of the output voltages. Capacitor C₃ is charged to 3V_in by the input-side SC module, and therefore, the proposed circuit produces a seven-level output (0, ±V_in, ±2V_in, and ±3V_in). The switch pairs (S₁, S₂) and (S₃, S₄) are never operated simultaneously to prevent the short-circuiting of the source. The switch pair (S₅, S₆) operates simultaneously in the positive half-cycle. The switch pairs (S₅, S₈) and (S₆, S₇) always operate in a complementary fashion.

To realize the circuit analysis, the seven operational modes (Mode A to Mode G) of the proposed MLI are shown in Figure 4. The capacitor voltages are assumed constant at V_c1 = V_c2 = V_in and V_c3 = 3V_in, to easily realize the operation. In Mode A, capacitors C₁ and C₂ discharge in series with the source, and capacitor C₃ is charged in parallel due to the conduction of S₁, S₅, and S₆. Thus, the output voltage is the sum of input voltage V_in and capacitor voltages V_c1 and V_c2, i.e., +3V_in. In Mode B, discharging capacitor C₂ in series with the source voltage produces +2V_in in the output. At the same time, capacitor C₁ is charged in series with the source due to the conduction of S₂ and S₃. At the same time, C₃ is disconnected from the circuit, i.e., C₃ is in the idle state. Capacitor C₂ is charged to the input voltage magnitude in Mode C when switch S₄ is conducting, and the input voltage is only responsible for generating +V_in at the output. Diode D₁ is forward-biased during this mode, whereas capacitors C₁ and C₃ are disconnected. When switches (S₁, S₅, and S₇) or (S₄, S₆, and S₈) are in the conducting state during Mode D, the output voltage is clamped to zero. In the first case, the capacitors are in the same state as in Mode A, and in the second case, the charging operation is the same as in Mode C. It is clear from the positive half-cycle operation that the output voltage is boosted to three times the input. During the negative half-cycle operation (Modes E to G), capacitor C₃ continuously contributes to the synthesis of the output voltage levels: −V_in (V_c3-V_c2-V_c1), −2V_in (V_c3-V_c2), and −3V_in (V_c3), respectively. Both capacitors C₁ and C₂ are charged during Mode E, whereas only capacitor C₂ is charged in the other two modes of the negative half-cycle.

Table 1. Operational states of the proposed CGMLI.

Modes	Conducting Switches	Switching Control Signals	C1	C2	C3	Output Voltage
A	S1, S5, S6	er > e1	↓	↓	↑	3Vin
B	S2, S3, S5, S6	e1 ≥ er > e2	↑	↓	-	2Vin
C	S4, S5, S6	e2 ≥ er > e3	-	↑	-	Vin
D	S1, S5, S7	e3 ≥ er > e4	↓	↓	↑	0
	S4, S6, S8		-	↑	-
E	S2, S3, S5, S7	e4 ≥ er > e5	↑	↑	↓	−Vin
F	S4, S5, S7	e5 ≥ er > e6	-	↑	↓	−2Vin
G	S4, S7, S8	e6 ≥ er	-	↑	↓	−3Vin
↑ = Charging, ↓ = Discharging

summarizes the switching modes of the proposed CGMLI.

A.

Multi-carrier PWM control of the proposed CGMLI

Carrier-based pulse-width-modulation (PWM) schemes are more popular for controlling MLIs [11,12,13]. Six carrier signals (e_c) and one sinusoidal signal (e_r), as shown in Figure 5, are used to generate the switching pulses for the switches. The level-shifted carriers are in the same phase with the same amplitude and frequency (f_c). The sinusoidal reference signal with a frequency of f_n is compared with the carrier signal in the same time axis. To synthesize the required seven-level output, the modulation process is divided into six regions according to the switching control signals (e_c and e_r), based on which the modes of operation are decided. In region 1, e_r is compared with e₃, which synthesizes two different modes, C and D, and the output voltage is either V_in or 0. In region 2, e_r is compared with e₂, and thus, two different modes, B and C, appear alternately, which produces 2V_in or V_in at the output. In region 3, e_r is compared with e₁, which synthesizes Modes A and B, resulting in the output voltage between 3V_in and 2V_in. Similarly, the negative half-cycle in Modes E–G is synthesized by comparing e_r with e₄–e₆.

By comparing the reference and carrier signals, three command signals, C_a, C_b, and C_c, are obtained, as shown in Figure 5. Based on the operating modes in different regions and the command signals, switching signals (S₁–S₈) are generated by applying the logic combination. The switching pulses, and therefore, the output voltage, can be varied by controlling the modulation index (0 < M_i < 1).

B.

Self-balanced Capacitor Design

From Figure 4 and Table 1, it is clear that the capacitors are charged in parallel and discharged in series. Furthermore, the charging–discharging durations are shorter than the total output voltage duration, and the low-parasitic-resistance path guarantees the voltage balancing of each capacitor regardless of the loading. It is worth noting that the voltage balancing of capacitors is achieved without using auxiliary voltage balancing control or sensors.

Practically, the voltage ripple across the capacitors is a key criterion to suitably determine the capacitance. Considering the maximum allowable voltage ripple of 10% and the maximum discharging period, the capacitance is calculated. The maximum discharging periods of C₁, C₂, and C₃ are from t₂ to t₃, from t₁ to t₄, and from t₅ to t₁₀, respectively. Based on this, the amount of charge in the capacitors can be expressed as follows:

$$∆Q_{C1}={\int }_{t_2}^{t_3}{I}_{omax}\sin \left(\omega t-\phi \right)dt$$

(1)

$$∆Q_{C2}={\int }_{t_1}^{t_4}{I}_{omax}\sin \left(\omega t-\phi \right)dt$$

(2)

$$∆Q_{C3}={\int }_{t_5}^{t_{10}}{I}_{omax}\sin \left(\omega t-\phi \right)dt$$

(3)

where I_omax is the peak value of the load current, and φ is the phase angle. Accordingly, the minimum value of capacitance required with the allowable voltage ripple should satisfy (4).

$$C_n\ge \frac{∆Q_{Cn}}{0.1V_{in}};n=1,2,3.$$

(4)

3. Power Loss Evaluation for the Proposed CGMLI

The total losses in switched-capacitor-based MLIs can be categorized as (a) switching loss due to the switching transition, (b) conduction loss caused by parasitic parameters, or (c) capacitor voltage ripple loss. Considering the resistive loading at which the maximum loss occurs in any converter, these losses were analyzed for the proposed MLI.

A.

Switching loss analysis

Due to turn-on and turn-off delays in switching semiconductor devices, switching losses are generated. These losses can be calculated based on the linear capacitance variation [41]. Considering an IGBT as the switching device, both the collector–emitter voltage and the collector current change gradually during the turn-on and turn-off process. Instantaneous changes in the voltage and current are not possible due to the built-in capacitor. Thus, switching losses occur due to significant voltage and current levels during the switching transition process.

From the operational analysis shown in Figure 4, it is clear that all the switches, except for S₆ and S₇, operate at a higher frequency. These switches withstand a voltage stress of 10V_in. On the other hand, switches S₆ and S₇ operate at a fundamental frequency and withstand a voltage stress of 3V_in each. Therefore, the switching loss is given by

$$P_{sw}=f_{sw}{E}_{sw}=f_{sw}{C}_{sw}{V}_{sw}^2$$

(5)

where f_sw = f_n for S₆ and S₇, and f_sw = f_c for all the other switches. E_sw is the energy loss during the switching transition, and V_sw is the voltage across the switches. C_sw is the parasitic capacitor that is charged and discharged during the off-state and on-state of the switches, respectively.

B.

Conduction loss analysis

The main causes of conduction loss are the parasitic parameters of the conducting devices in the discharging loop. The parasitic parameters include the forward voltage drop of diodes (V_Deq), the equivalent parasitic resistance (R_eq) of the switch (with anti-parallel diodes), and the equivalent series resistance of the capacitors (ESR_c). Considering this, Figure 6 shows an equivalent discharging current loop where R_L is the load resistance.

Assuming that the forward voltage drop of all the diodes, including the anti-parallel diodes of the switches, is the same (i.e., V_D, with an internal resistance of R_D) and the on-state resistance of the switches is the same (i.e., R_S), the equivalent circuit parameters are listed in

Table 2. Equivalent discharging loop parameters.

Equivalent Parameters	Equivalent Voltage (Veq)	Forward Voltage Drop of Diodes (VDeq)	Equivalent Parasitic Resistance (Req)
k = 0	0	VD	RS + RD
k = 1	Vin	VD	2RS + RD
k = 2	2Vin	0	3RS + ESRc
k = 3	3Vin	0	3RS + 2ESRc

.

Considering a resistive loading condition, the overall conduction loss for the time instant (t) is expressed as

$$P_{cn}=\frac{2}{\pi }{\sum }_{k=1}^3\left\{{\left(\frac{V_{eq}-V_{Deq}}{R_{eq}+R_L}\right)}^2\times R_{eq}\times \left(t_{k+1}-t_k\right)\right\}$$

(6)

C.

Capacitor voltage ripple loss analysis

During the charging of the capacitors in parallel, ripple/charging losses occur due to the difference between the desired voltage and the actual voltage across the capacitors. The energy loss due to the capacitor voltage ripple (∆V_c) in one charging period for any capacitor (C) can be calculated as

$$E_{rip}=0.5C{∆V_c}^2$$

(7)

The total ripple loss of the proposed CGMLI, taking 10% of the maximum allowable voltage ripple, can be expressed as

$$P_{rip}=f_n{E}_{rip}$$

(8)

$$P_{rip}={0.5f}_n\left[\left(C_1+C_2\right){\left(0.1V_{in}\right)}^2+C_3{\left(0.3V_{in}\right)}^2\right]$$

(9)

Considering the losses in (5), (6), and (9), the theoretical efficiency of the proposed MLI can be obtained as

$$\eta =\frac{\mathrm{o}\mathrm{u}\mathrm{t}\mathrm{p}\mathrm{u}\mathrm{t} \mathrm{p}\mathrm{o}\mathrm{w}\mathrm{e}\mathrm{r}}{\mathrm{o}\mathrm{u}\mathrm{t}\mathrm{p}\mathrm{u}\mathrm{t} \mathrm{p}\mathrm{o}\mathrm{w}\mathrm{e}\mathrm{r}+P_{sw}+P_{cn}+P_{rip}}$$

(10)

4. Comparative Evaluation

To verify the different features of the proposed CGMLI, a fair comparison was carried out considering seven-level (N_l) SC-based topologies with and without the CG architecture. All the topologies considered for the comparison in

Table 3. Comparison of the single-phase single-input 7-level SCMLI topologies.

Parameters	Nsw	Ndrv	Ndd	Ncap	Nms	MSVpu	TSVpu	Gain	CF (x = 0.5)	CF (x = 1.5)	ileak	Reactive Power Transfer	Efficiency
[11]	7	7	2	3	3	1	5.6	1	3.61	4.56	high	Yes	92.3% @ 800 W
[26]	10	8	0	2	5	1.33	7.33	1.5	3.98	4.81	low (NPC)	Yes	97.4% @ 1.3 kW
[28]	10	8	0	2	6	0.67	6	1.5	4.03	4.67	low (NPC)	Yes	96.5% @ 270 W
[30]	10	9	0	1	5	0.67	6	1.5	3.89	4.52	low (NPC)	Yes	96% @ 900 W
[32]	9	8	0	4	4	1	5.33	1.5	3.87	4.48	low (NPC)	Yes	97% @ 600 W
[27]	9	8	0	1	5	0.67	5.33	1.5	3.57	4.14	low (NPC)	Yes	-
[29]	9	8	0	1	5	0.67	5.33	1.5	3.57	4.14	low (NPC)	Yes	96.7% @ 150 W
[31]	8	7	2	2	4	0.67	4.67	1.5	3.54	4.05	low (NPC)	Yes	97.8% @ 130 W
[19]	10	8	0	1	6	0.67	5.33	1.5	3.86	4.43	high	Yes	-
[14]	7	7	4	2	4	1	5	3	3.57	3.86	high	No	-
[20]	14	14	0	2	6	0.33	4.67	3	5.26	5.50	high	Yes	91.7% @ 180 W
[12]	14	14	0	2	6	0.67	5.33	3	5.29	5.57	high	Yes	91% @ 1 kW
[10]	12	11	0	2	8	0.67	5.33	3	4.86	5.14	high	Yes	95.5% @ 900 W
[13]	10	10	0	2	4	1	6	3	3.88	4.21	high	Yes	85.9% @ 5 W
[17]	10	10	0	3	6	1	6	3	4.31	4.64	high	Yes	95.4% @ 500 W
[22]	10	10	3	2	5	1	6	3	4.45	4.79	high	Yes	97% @ 500 W
[18]	9	9	1	2	4	1	5.67	3	3.73	4.05	high	Yes	96.5% @ 100 W
[15]	8	8	2	2	4	1	5.33	3	3.58	3.88	high	Yes	-
[16]	8	8	2	2	4	1	5.33	3	3.58	3.88	high	Yes	97.1% @ 190 W
[21]	8	8	4	4	4	0.67	4	3	4.11	4.33	high	Yes	94% @ 250 W
[25]	11	11	1	3	5	1	8.67	3	4.66	5.12	low	Yes	91.1% @ 200 W
[37]	11	10	0	3	6	1	6	3	4.45	4.79	zero (CG)	Yes	97.2% @ 600 W
[38]	10	8	2	3	4	1	8.33	3	4.08	4.52	zero (CG)	Yes	96.3% @ 1 kW
Proposed	8	8	2	3	3	1	5.33	3	3.58	3.88	zero (CG)	Yes	95.1% @ 740 W

require a single input to generate a seven-level output. In terms of the number of switches, the topologies proposed in [11,14] require a minimum number of components. However, while the former does not have a boosting ability, the latter is not suitable for low-power-factor loads due to its series diodes. In comparison, the proposed MLI utilizes an optimum number of switches (N_sw), diodes (N_dd), and driver circuits (N_drv) while retaining the said benefits. Also, the minimal switches in the load current path (N_ms) signify low conduction loss. Moreover, achieving high voltage boosting using a lower number of capacitors (N_cap) is a key requirement. Most of the seven-level topologies with a three-fold boosting ability require two/three capacitors similar to the proposed CGMLI, whereas a few MLIs that require one capacitor have a low voltage gain.

From the voltage stress point of view, the topology proposed in [21] has the minimum TSV. However, due to the absence of the common-grounding feature, this structure cannot address the leakage current issue. The structures proposed in [20,31] had a considerably lower TSV than the proposed CGMLI. However, the voltage gain in [31] was limited to 1.5, whereas a lower TSV and maximum standing voltage (MSV) were achieved in [20] at the cost of a significantly higher number of switches. Furthermore, the NPC MLI and CGMLI are among the straightforward solutions addressing the issues of leakage current (i_leak). The cost factor (CF) was calculated for a fair comparison. The CF is defined as below:

$$CF=\frac{\left(N_{sw}+N_{drv}+N_{dd}+N_{cap}+N_{ms}+x[{\mathrm{M}\mathrm{S}\mathrm{V}}_{\mathrm{p}\mathrm{u}}+{\mathrm{T}\mathrm{S}\mathrm{V}}_{\mathrm{p}\mathrm{u}}]\right)}{N_l}$$

(11)

From the CF analysis, it is clear that the proposed CGMLI is superior compared to the most recently developed SCMLIs. A weight factor of x = 0.5 was assigned to give less weight to the voltage stress and x = 1.5 was assigned to give high weight to the voltage stress. In both cases, and considering the various comparison parameters, the proposed MLI is the only structure that renders the benefit of high voltage boosting and utilizes a reduced number of components, allowing for backflow of the current and eliminating the leakage current completely. Therefore, the superiority of the proposed MLI is justified in single-stage single-phase PV systems.

The most recently developed seven-level topologies were further compared in terms of their power loss (Pl), efficiency (η), and cost. The efficiencies of different topologies were evaluated by a detailed circuit simulation. The total power loss included the losses discussed in Section 3. For a low output power range, the topology in [21] had higher efficiency. However, the capacitor ripple losses and the total power loss increased due to a greater number of capacitors at high output power. Compared to most prior-art seven-level topologies, Figure 7 indicates that the proposed structure has the advantages of higher efficiency and low power loss due to its lower number of components and significantly low TSV.

Table 4. Cost evaluation comparison of prior-art 7-level topologies.

Components	Part Number	Rated Voltage	Unit Cost (USD)	[21]	[25]	[37]	[17]	Proposed
MOSFET Switch	IRFP250	Vin	4.14	4	2	6	6	3
	IXFH30N40	2Vin	8.60	4	3	2	--	2
	IXFH30N60	3Vin	11.42	--	6	3	4	3
Gate driver	TLP250	--	1.77	8	11	10	10	8
Diode	DPG30I400	Vin	3.89	4	--	--	1	--
	DPG30I400	2Vin	3.89	--	1	--	--	1
	DHG30I600	3Vin	5.17	--	--	--	--	1
Capacitor	UCY2C221MHD	Vin	2.56	4	3	3	3	2
	LLS2V471MELC	3Vin	6.29	--	--	--	--	1
Total cost ($)				90.92	133.64	101.68	99.79	98.51

Cost evaluation (unit cost from www.digikey.in as of 3 May 2024).

indicates the costs of the prior-art seven-level MLIs, evaluated considering a 1 kW prototype with an input voltage of 100 V, triple-voltage gain output, and 30 A current rating of the devices. The monetary cost of the proposed MLI is low compared to the structures proposed in [17,25,37]. The device rating is quite low compared to the topology in [21], resulting in a lower cost. However, none of the topologies have a common-grounding feature, unlike the proposed CGMLI, which is essential in PV systems for eliminating issues of leakage current.

5. Simulation and Experimental Verification

To validate the operability of the proposed seven-level CGMLI, simulations were conducted using the MATLAB/Simulink 2018a environment, and the experimental results were obtained using a laboratory-scale prototype.

Table 5. Simulation and experimental test parameters.

Parameters	Values
Input dc source (Vin)	100 V
Capacitors	0.22 mF (C1 and C2), 0.47 mF (C3)
Input inductor (Lin)	50 µH
Frequency (fn and fc)	50 Hz and 5 kHz
R-load	(50–100) Ω
RL-load	50 Ω–100 mH

summarizes the specifications of the test system.

A.

Simulation analysis of open-loop operation

To verify the operation of the proposed seven-level CGMLI, simulation results were obtained under different dynamic conditions. The switching pulses were obtained using the modulation scheme shown in Figure 5. Figure 8a shows the output voltage (V_o) and load current (I_o) with a change in the M_i from 0.6 to 0.95. At t₁, the output of the proposed MLI changed from five levels to seven levels, i.e., the peak amplitude of the output voltage varied from 200 V to 300 V. Thus, the MLI was able to synthesize different output voltage levels by varying the control signal. The results of sudden variation in the loading are also shown in Figure 8b. At t₂, the load was halved (100 Ω to 50 Ω), and at t₃, the load changed from resistive to inductive. In both these scenarios, the load current changed smoothly, while the output voltage remained stable. The loading power factor changed from unity to nearly 0.85 with the change in load. The peak amplitude of the output voltage was maintained throughout at 300 V, which is three times the input voltage, and the capacitor voltages were inherently balanced as desired. The capacitor voltage ripple also increased with the decrease in the loading. To further analyze the self-balancing ability, Figure 8c shows the results under a drop in the input voltage from 100 V to 80 V at t₄. Figure 8d verifies that the voltage stress across all switches were in line with those with Figure 3c.

B.

Simulation analysis of closed-loop operation

To verify the closed-loop operation of the proposed seven-level CGMLI-based grid-tied system, simulation results were obtained under different dynamic conditions. For the single-stage grid-tied system, a few key objectives, such as the maximum power point tracking (MPPT) under fluctuating irradiation, current injection into the grid, active–reactive power (P and Q) control, and multilevel output generation, were ensured using the control schematics shown in Figure 9. Operation of the PV MLI at MPPT was ensured using the incremental conductance MPPT algorithm. The control structure takes into account the conversion of the grid voltage (V_g) and grid current (I_g) into a two-phase dq component (V_d, V_q, I_d, I_q), which enables control of the reactive power exchange. Using a decoupled power control strategy, reference currents were obtained, and then a modulating reference signal (V_inv^*) was obtained using the current control loop. The multi-carrier PWM control logic depicted in Figure 5 was further used to generate the switching pulses. The PV array was designed using 6 × 2 panels with a maximum voltage of 17.32 V and a maximum current of 7.13 A. The grid voltage was considered to be 250 V (peak) with a 50 Hz frequency, integrated via a 3.5 mH filter inductance. Figure 10a validates the operation with a change in irradiation from 1000 W/m² to 300 W/m². The grid operated at unity power factor while maintaining a clean sinusoidal grid current. The dc-link voltage was stably maintained at nearly 100 V, and the capacitor voltages were maintained throughout. Thus, the CGMLI produced the required seven-level output (V_o). It is also clear that the leakage current (I_lkg) was negligible (a few mA) due to the CG connection of the proposed circuit. Figure 10b validates the operation of the grid-tied system with changes in the power factor. The CG MLI operated smoothly, confirming the reactive power exchange capability with changes from a lagging to leading power factor. With a small input choke (50 µH), Figure 10c shows the capacitor currents and the input current. The inrush current was significantly reduced, confirming the suitability of the circuit operation in PV applications.

C.

Experimental verification

To verify the correct functioning of the proposed seven-level CGMLI, experimental tests were conducted using a laboratory-scale setup, as shown in Figure 11. The system parameters are shown in Table 5. Eight IGBTs (S₁–S₈) were used, comprising IKP30N65F5, with anti-parallel diodes, and IGP30N65F5, without anti-parallel diodes. The test bench also includes IDP30E65D1 (D₁ and D₂) diodes, UCY2C221MHD (C₁ and C₂), LLS2V471MELC (C₃) capacitors, a programmable dc source, a TLP250 optocoupler-based driver circuit, and a DSP 28335 controller. The controller was programmed to generate switching pulses using the multi-carrier PWM control scheme. These pulses were amplified using the driver circuit to provide the required gate voltage and current for switching. The results were captured on a DLM3024 and DL850 oscilloscope, and a power analyzer was used to evaluate the efficiency and other performance parameters.

Initially, tests were conducted with dynamics, with the M_i varying from 0.95 to 0.6 at t₁ and from 0.6 to 0.95 at t₂. Figure 12 shows that the proposed circuit was able to successfully synthesize different output voltage levels. The capacitor voltage ripple changed correspondingly with the changes in the M_i. Figure 13 verifies the dynamic operational ability under sudden changes in loading and the input voltage variation. At t₃ and t₄, the load changed from no-load to an RL-load and from an R-load to an RL-load, respectively. The output voltage remained undistorted and stable under the sudden load variation, while the load current pattern changed. The load current pattern was identical to the output voltage under the R-load and the sinusoidal under the RL-load, as shown in Figure 13b,c, respectively. The amplitude of the output voltage was 300 V, which verifies the triple-voltage gain of the proposed MLI. Figure 13c further validates the inherent voltage balancing and boosting ability as the capacitor voltages were naturally decreased to the desired voltage after a change in the input voltage from 100 V to 80 V at t₅.

The voltage stress across all the switches is depicted in Figure 14a, verifying that despite requiring three switches with a peak load voltage rating, the total TSV was limited to 16V_in while maintaining the maximum voltage gain. Furthermore, in the SC-type ANPC/CG-based circuit, high current spikes occurred during the capacitor charging process, a longstanding issue in all reported SC MLIs. As a straightforward solution to this issue, integrating a quasi-resonant cell on the input side is more feasible [37]. A similar test was conducted with a small choke. Without an input choke and considering the parasitic resistance only, the capacitor current and the input current were significantly higher (almost 20 times the load current), as shown in Figure 14b. With a small input choke (50 µH), the capacitor current and the input current were effectively reduced, as shown in Figure 14c. The results closely match with the simulation results in Figure 10c, and the efficiency of the MLI was unaffected by the input choke. Figure 14d depicts the performance analysis of the seven-level prototype under two different loads, i.e., high-power-factor load (50 Ω–20 mH) and low-power-factor load (50 Ω–100 mH). The efficiencies of the proposed topology were 95.16% and 94.73% for output ratings of 740 W and 860 W, respectively. With a decrease in the power factor (λ), a decrease in the active power (P) and an increase in the reactive power (Q) is evident from the results. The results also display the voltage and the current total harmonic distortion (THD) of the seven-level output voltage and current.

Furthermore, tests were carried out to justify the closed-loop operation with the grid voltage 220 V (peak), 50 Hz frequency, and 100 V programmable power supply. At unity power factor, the grid operated with a clean sinusoidal current, and the capacitor voltages were maintained at the desired voltage, as shown in Figure 15a. A three-fold boosted seven-level inverter voltage is also confirmed by the results. Figure 15b,c depict the operation of the grid-tied system with lagging and leading power factors, respectively. The results confirm that the CG MLI with the suggested control scheme can exchange the reactive power while injecting a sinusoidal grid current. Figure 15d validates the common-grounding attribute, nullifying the leakage current (a few mA) in practice, and satisfying the VDE 0126-01-01 grid code standard (<300 mA). The results confirm that the proposed structure has the advantage of high-voltage boosting using a reduced number of components, dynamic operational ability under different power factors, and a common-grounding feature, making it suitable for PV applications.

6. Conclusions

This work has introduced a single-input seven-level boost-type CGMLI with a common-grounding architecture aimed at eliminating leakage current. By charging the SCs in parallel and discharging them in series, the steady-state voltages across the SCs are maintained at V_in and 3V_in, facilitating triple-voltage boosting. As a result, the proposed MLI does not require any auxiliary voltage balancing circuit, thereby reducing control complexity. Furthermore, the AC output was synthesized without using a conventional full-bridge, which significantly reduces voltage stress. With these distinctive features, the proposed CGMLI is highly suitable for single-stage PV systems. The operational principles, multi-carrier PWM scheme, charging–discharging process, and power loss analysis have been discussed in detail. A thorough comparative analysis revealed that the proposed CGMLI optimizes the number of components while retaining other advantages, such as high-voltage gain and the elimination of leakage current. Both simulation and experimental analyses have confirmed the feasibility of the proposed seven-level MLI under dynamic operating conditions, including changes in the modulation index, loading, input voltage, and sudden variations on the grid side.