Leveraging Seed Generation for Efficient Hardware Acceleration of Lossless Compression of Remotely Sensed Hyperspectral Images
Abstract
:1. Introduction
- We describe the hardware acceleration of a lossless compression algorithm designed specifically for hyperspectral images. Optimized for FPGA platforms and enhanced by leveraging seed generation techniques, this adaptation demonstrates practical applicability and effectiveness in real-time processing.
- We present the implementation of the lossless algorithm targeting an FPGA with modest capabilities, such as Cyclone V. This implementation demonstrates substantial performance improvements, achieving a throughput of 1598.67 Mega Samples per second (MSps), while maintaining a power requirement below 1 Watt. This highlights the durability of the designed algorithm and the optimized hardware acceleration in achieving both computational speed and efficiency.
2. Related Work
3. Materials and Methods
3.1. Lossless Compression
3.1.1. Preprocessing
3.1.2. Computation of the Integral Part
3.1.3. Calculation of the Binary Logarithm
3.1.4. Computing the Fractional Part
3.1.5. Postprocessing
3.2. Hardware Implementation
3.2.1. Bitwise XOR Logic
3.2.2. Shift Amount Calculator
Algorithm 1: Binary search to determine shift_amount based on the value of XORed |
Input: XORed Output: shift_amount 1. Determine n based on the value of XORed using nested comparisons: if XORed > 15 if XORed > 63 if XORed > 127 n ← 8 //XORed is greater than 127 else n ← 7 //XORed is between 64 and 127 else if XORed > 31 n ← 6 //XORed is between 32 and 63 else n ← 5 //XORed is between 16 and 31 else if XORed > 3 if XORed > 7 n ← 4 //XORed is between 8 and 15 else n ← 3 //XORed is between 4 and 7 else if XORed > 1 n ← 2 //XORed is between 2 and 3 else n ← 1 //XORed is 1 or less 2. Compute shift_amount as half of n by right-shifting n by 1: shift_amount ← n ≫ 1 3. Return shift_amount |
Algorithm 2: Modified binary search to determine shift_amount based on the value of XORed |
Input: XORed Output: shift_amount 1. Determine shift_amount based on the value of XORed using nested comparisons: if XORed > 31 if XORed > 127 shift_amount ← 4 //XORed is greater than 127 else shift_amount ← 3 //XORed is between 32 and 127 else if XORed > 7 shift_amount ← 2 //XORed is between 8 and 31 else if XORed > 1 shift_amount ← 1 //XORed is between 2 and 7 else shift_amount ← 0 //XORed is 1 or less 2. Return shift_amount |
3.2.3. Seed Generation Logic
3.2.4. Fraction Calculation Logic
3.2.5. Uniform Encoding Block
3.2.6. Direct Rice Encoder
3.2.7. Zero Detection Logic
3.2.8. Adaptive Run-Length Encoder
3.2.9. The Glue Logic
3.2.10. Top-Level Entity
4. Results and Discussion
4.1. Clock Frequency
4.2. Power Requirement
4.3. Throughput
4.4. Resource Utilization and Scalability
4.5. Comparison with State-of-the-Art Implementations
5. Conclusions
6. Future Work
Author Contributions
Funding
Data Availability Statement
Acknowledgments
Conflicts of Interest
References
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Compression Method | CR | Throughput (MSps) | Power (Watts) | Efficiency (MSps/W) | Reference, Year |
---|---|---|---|---|---|
CCSDS 123.0-B-1 | - | - | - | - | [13], 2021 |
CCSDS 123.0-B-2 | - | 21.47 | - | - | [16], 2023 |
CCSDS 123.0-B-3 | - | 9.38 | 0.149 | 63 | [16], 2023 |
CCSDS 123.0-B-2 | - | 249.6 | 1.21 | 206.3 | [17], 2022 |
CCSDS-123.0-B-2 | - | 305 | 1.525 | 200 | [18], 2022 |
CCSDS-MHC | 3.28 | - | - | - | [19], 2022 |
Integral Part (Seed) | Fractional Part | ||
---|---|---|---|
1 | 1 | 0000 | 0 (unary) |
2 | 1 | 0001 | 0 |
3 | 1 | 0001 | 1 |
4 | 2 | 0000 | 10 (unary) |
5 | 2 | 0010 | 00 |
6 | 2 | 0010 | 01 |
7 | 2 | 0010 | 10 |
8 | 2 | 0010 | 11 |
9 | 3 | 0011 | 00 |
… | … | … | … |
16 | 4 | 0000 | 110 (unary) |
17 | 4 | 0100 | 000 |
18 | 4 | 0100 | 001 |
19 | 4 | 0100 | 010 |
20 | 4 | 0100 | 011 |
21 | 4 | 0100 | 100 |
22 | 4 | 0100 | 101 |
23 | 4 | 0100 | 110 |
24 | 4 | 0100 | 111 |
25 | 5 | 0101 | 0000 |
… | … | … | … |
Pivot 1 | ||
---|---|---|
1 | 1 | 0 |
2 | 3 | 1 |
3 | 7 | 1 |
4 | 15 | 2 |
5 | 31 | 2 |
6 | 63 | 3 |
7 | 127 | 3 |
8 | 255 | 4 |
FPGA Characteristics | Name/Value |
---|---|
Manufacturer | Intel |
Series | Cyclone® V GT |
Number of LABs/CLBs | 113560 |
Number of Registers | 4786 |
Number of DSP Blocks | 342 |
Total RAM Bits | 14251008 |
Number of Pins | 616 |
Number of GPIO Pins | 560 |
Voltage—Supply | 1.07 V~1.13 V |
Operating Temperature | 0 °C~85 °C |
Compression Method | CR | Throughput (MSps) | Power (Watts) | Efficiency (MSps/W) | Reference |
---|---|---|---|---|---|
DPCM | 4.8 | 280 | 650 | 0.4 | [31] |
CCSDS123 | 2.2–4.5 | 183.4 | 60 | 3.1 | [32] |
CCSDS 123 | - | 401–116 | 60–15 | 6.7–7.7 | [33] |
CCSDS123 | 3.2–4 | 165.65 | 2.6 | 63.7 | [34] |
CCSDS 123 | 1.5–5.5 | 129 | 4.9 | 26.3 | [35] |
CCSDS123 | - | 69.8 | 4.56 | 15.3 | [36] |
CCSDS123 | - | 93.2 | 4.56 | 20.4 | [36] |
CCSDS123 | - | 45 | 5.7 | 7.9 | [37] |
CCSDS123 | - | 146.9 | 6.28 | 23.4 | [37] |
CCSDS123 | - | 308.13 | 10.9 | 28.3 | [37] |
CCSDS123 | - | 66 | 5.7 | 11.6 | [37] |
CCSDS123 | - | 203.3 | 6.28 | 32.3 | [37] |
CCSDS123 | - | 402.5 | 10.9 | 36.9 | [37] |
CCSDS 123 | - | 147 | 0.295 | 498.3 | [38] |
CCSDS 123 | - | 750 | 0.515 | 1456 | [39] |
CCSDS123 | 3.4 | 3.5 | 0.169 | 20.7 | [40] |
CCSDS123 | 3.4 | 11.3 | 2.345 | 4.8 | [40] |
CCSDS123 | 3.4 | 11.2 | 2.345 | 4.8 | [40] |
CCSDS 123 | 2.3 | 3.5 | 0.169 | 20.7 | [40] |
CCSDS 123 | 2.3 | 11.3 | 2.345 | 4.8 | [40] |
CCSDS 123 | 2.3 | 11.2 | 2.345 | 4.8 | [40] |
Prediction-based | - | 179.7 | 3.04 | 59.1 | [41] |
Prediction-based | - | 116 | 0.95 | 122.1 | [41] |
Prediction-based | - | 219.4 | 5.3 | 41.4 | [41] |
Prediction-based | - | 62.2 | 65 | 0.96 | [41] |
Prediction-based | - | 62.6 | 29 | 2.2 | [41] |
CCSDS 123 | - | 179.7 | 3.04 | 59.1 | [41] |
CCSDS 123 | - | 116 | 0.95 | 122.1 | [41] |
CCSDS 123 | - | 219.4 | 5.3 | 41.3 | [41] |
CCSDS 123 | - | 62.2 | 65 | 0.96 | [41] |
CCSDS 123 | - | 62.6 | 29 | 2.2 | [41] |
VS—3DGAP—ExtRice (CCSDS based) | 2.8 | 210 | 0.573 | 366.5 | [42] |
Prediction-based | 2.5 | 23.3 | 0.55 | 42.4 | [43] |
CCSDS 123 | 2.5 | 23.3 | 0.55 | 42.4 | [43] |
CCSDS 123.0-B-3 | - | 9.38 | 0.149 | 63 | [16] |
CCSDS 123.0-B-2 | - | 249.6 | 1.21 | 206.3 | [17] |
CCSDS-123.0-B-2 | - | 305 | 1.525 | 200 | [18] |
Proposed | 2.6 | 1598.67 | 0.874 | 1829.1 | - |
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Altamimi, A.; Ben Youssef, B. Leveraging Seed Generation for Efficient Hardware Acceleration of Lossless Compression of Remotely Sensed Hyperspectral Images. Electronics 2024, 13, 2164. https://doi.org/10.3390/electronics13112164
Altamimi A, Ben Youssef B. Leveraging Seed Generation for Efficient Hardware Acceleration of Lossless Compression of Remotely Sensed Hyperspectral Images. Electronics. 2024; 13(11):2164. https://doi.org/10.3390/electronics13112164
Chicago/Turabian StyleAltamimi, Amal, and Belgacem Ben Youssef. 2024. "Leveraging Seed Generation for Efficient Hardware Acceleration of Lossless Compression of Remotely Sensed Hyperspectral Images" Electronics 13, no. 11: 2164. https://doi.org/10.3390/electronics13112164
APA StyleAltamimi, A., & Ben Youssef, B. (2024). Leveraging Seed Generation for Efficient Hardware Acceleration of Lossless Compression of Remotely Sensed Hyperspectral Images. Electronics, 13(11), 2164. https://doi.org/10.3390/electronics13112164