# Polymorphic Hybrid CMOS-MTJ Logic Gates for Hardware Security Applications

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Background

#### 2.1. Magnetic Tunnel Junction: Construction and Switching

#### 2.2. Logic-in-Memory Architecture

## 3. Proposed Work: Spintronics PGs for Hardware Security Applications

#### 3.1. Operation of Spintronics PGs

#### 3.2. Preventing Manufacturing-Time Tampering

#### 3.3. IC Watermarking

#### 3.4. IC Fingerprinting

## 4. Results and Discussion

#### 4.1. Simulation Results

#### 4.2. Effect of Process Variation

#### 4.3. Design Considerations, Discussion, and Challenges

## 5. Conclusions

## Author Contributions

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Data Availability Statement

## Conflicts of Interest

## References

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**Figure 1.**(

**a**) Two-terminal p-MTJ construction and switching. (

**b**) Three-terminal p-MTJ structure. (

**c**) Von-Neumann and logic-in-memory architecture. (

**d**) Hybrid CMOS-MTJ structure.

**Figure 2.**Hybrid CMOS-MTJ-structure-based circuits utilizing a four-transistor writing circuit for performing (

**a**) XOR/XNOR operation and (

**b**) AND/OR operation. (

**c**) Truth table with corresponding resistance value of left and right branch of PCSA. NMOS logic structures from [46] were utilized.

**Figure 3.**Preventing manufacturing-time tampering using spintronics PG. (

**a**) An example circuit (Clk and Ctrl signal are connected to every block). (

**b**) Equivalent gate-level diagram with Ctrl = 0. (

**c**) Equivalent gate-level diagram with Ctrl = 1.

**Figure 4.**IC watermarking using spintronics PG. (

**a**) An example circuit (Clk is connected to both blocks). (

**b**) Equivalent circuit giving regular output sequence at Ctrl = 0. (

**c**) Equivalent circuit giving watermark output sequence at Ctrl = 1.

**Figure 5.**IC fingerprinting using spintronics PGs. (

**a**) An example circuit with an SDC-condition-based fingerprinting. (

**b**) Truth table of the internal signals and output for AND and OR operation.

**Figure 7.**Variation of delay with width of tail NMOS transistor of PCSA for SOT-based (

**a**) XOR operation. (

**b**) NAND operation.

**Figure 8.**Waveform showing the operation of spintronics PG based watermarking and fingerprinting example circuits.

**Figure 9.**Monte Carlo simulation waveforms at (

**a**–

**c**) FF, TT, and SS corners in circuit performing AND/OR operation and (

**d**–

**f**) FF, TT, and SS corners in circuit performing XOR/XNOR operation.

Parameter | STT-MTJ Values | SOT-MTJ Values |
---|---|---|

MTJ Dimension | 40 nm × 40 nm | 40 nm × 40 nm |

MTJ Shape | Circular | Circular |

Oxide barrier thickness | 0.85 nm | 0.85 nm |

Free layer thickness | 0.7 nm | 0.7 nm |

Heavy metal dimensions | – | 60 nm × 40 nm × 3 nm |

Resistance area product | 10 $\mathsf{\Omega}$ um${}^{2}$ | 10 $\mathsf{\Omega}$ um${}^{2}$ |

Tunnel Magnetoresistance | 200% | 200% |

Temperature | 300 K | 300 K |

Technology parameters | default [36] | default [37] |

Logic Operation | STT-MTJ-Based | SOT-MTJ-Based | ||
---|---|---|---|---|

Fall Time | Delay | Fall Time | Delay | |

AND | 117.71 ps | 132.48 ps | 167.74 ps | 96.20 ps |

OR | 99.16 ps | 25.40 ps | 154.95 ps | 70.60 ps |

NAND | 115.48 ps | 25.30 ps | 154.33 ps | 70.20 ps |

NOR | 146.40 ps | 161.60 ps | 170.15 ps | 98.00 ps |

XOR | 106.88 ps | 27.60 ps | 171.40 ps | 99.30 ps |

XNOR | 106.53 ps | 27.50 ps | 164.53 ps | 93.40 ps |

**Table 3.**Performance of spintronics PGs at various process corners with 3% variation in specific MTJ parameters.

Process Corner | Temperature (°C) | Supply Voltage (Vdd) | AND/OR Operation | XOR/XNOR Operation |
---|---|---|---|---|

Fast–best (FF) | −25 °C | 1.1 V | Pass | Pass |

Typical (TT) | 25 °C | 1.0 V | Pass | Pass |

Slow–worst (SS) | 75 °C | 0.9 V | Fail | Fail |

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**MDPI and ACS Style**

Kumar, R.; Divyanshu, D.; Khan, D.; Amara, S.; Massoud, Y.
Polymorphic Hybrid CMOS-MTJ Logic Gates for Hardware Security Applications. *Electronics* **2023**, *12*, 902.
https://doi.org/10.3390/electronics12040902

**AMA Style**

Kumar R, Divyanshu D, Khan D, Amara S, Massoud Y.
Polymorphic Hybrid CMOS-MTJ Logic Gates for Hardware Security Applications. *Electronics*. 2023; 12(4):902.
https://doi.org/10.3390/electronics12040902

**Chicago/Turabian Style**

Kumar, Rajat, Divyanshu Divyanshu, Danial Khan, Selma Amara, and Yehia Massoud.
2023. "Polymorphic Hybrid CMOS-MTJ Logic Gates for Hardware Security Applications" *Electronics* 12, no. 4: 902.
https://doi.org/10.3390/electronics12040902