Reliability Analysis of a Multilevel Inverter Applied to Stratospheric Drones Using Fault Tree Analysis

Abstract

Stratospheric drones operating in extreme environments are very important for predicting reliability and are high-efficiency, high-performance, and lightweight power units. Multilevel inverters are suitable for application as power conversion units for stratospheric drones. A guideline is needed to evaluate whether it is suitable for practical application from a reliability perspective among various multilevel topologies. Existing reliability prediction models cannot reflect the operating characteristics of multilevel inverters. In this paper, we analyze the driving characteristics of each topology from the perspective of half-bride, which is the basic configuration of multilevel inverters, and we propose a fault tree analysis (FTA) design with three operating modes. The proposed method has the advantage of being able to easily analyze the failure rate by expanding to single-phase and three-phase and to analyze the failure rate according to changes in modulation index (MI) and power factor (PF). The failure rates of the proposed method and the part count method are analyzed using MIL-HDBK-217F. We also analyze the impact of different various operating characteristics on the failure rate. From a reliability perspective, we provide a variety of guidelines for selecting a multilevel topology that fits the operation conditions.

1. Introduction

The stratospheric drone has recently been studied for weather observation, communication relay role, surveillance, and reconnaissance at an altitude of 18 to 20 km. The stratospheric drones use solar energy and energy storage to maintain altitude for long stays. To maintain the target altitude for a long period in the stratosphere, high efficiency and high performance of the power unit are required, and it is very important to improve and predict reliability for mission performance in extreme environments [1,2,3].

The pulse width modulation (PWM) method, which is widely applied to motor drives and power conversion, has the advantage of simultaneously controlling the magnitude and frequency of the output voltage and is relatively easy to implement. Owing to the switching operation, the output waveform of the inverter includes various harmonic components in addition to the fundamental harmonic components. Harmonics can cause various disturbances to other peripherals due to electromagnetic inductance, motor noise and torque pulsation, and current leakage due to common mode voltage. Therefore, harmonics cause the reliability and efficiency of the entire system to deteriorate. Therefore, it is necessary to minimize the harmonic component caused by PWM switching [4,5].

A common method is to configure a filter at the inverter output, but the larger the filter, the worse the control response characteristics and the larger the overall size and weight. For stratospheric drones that need to be reliable and lightweight, it may be effective to apply multilevel inverters to suppress harmonic components [6,7]. Therefore, it is important to select reliable circuit topologies for long-term flight and mission performance in the stratosphere.

To improve reliability, a risk analysis of the operating environment of major parts such as semiconductor switching elements and capacitors is important. Among the indicators of reliability, the failure rate is defined as the number of failures per unit of time for an individual part. Mean time between failure (MTBF), an indicator of average life, is a reciprocal expression of the failure rate [8,9]. The most common method for predicting lifespan is accelerated life testing. This is not based on the failure rate of the part unit, but rather a method of predicting the lifespan of the actual operating environment by testing the completed system in a harsh environment. However, it requires a large number of samples for accurate lifetime prediction and is not suitable for the topology selection stage [10,11,12]. Other reliability prediction models include Markov models, binomial distributions, and part count models.

The Markov model is useful for quantifying the failure rate for systems with frequent failures, but it is impossible to evaluate when the failure rate of the devices varies depending on the time of use. In addition, there is the problem that the size of the state space increases exponentially with the number of parts [13,14,15,16]. The binomial distribution model is a reliability analysis method based on probability distribution and evaluates reliability by probabilistically analyzing system failures using the DeMoivre equation [17,18]. The part count model is a method of prediction by assuming that the subsystem has a serial structure and that the failure rate of individual parts is constant. A simple prediction method is useful in the initial design stage, but the condition that the failure rate of the unit part is constant can make a big difference from the actual failure rate [19,20,21]. These reliability models can interpret the reliability of the inverter itself but cannot consider the operating characteristics. To find the optimal circuit topology, a more accurate lifetime prediction and failure risk analysis that reflects the driving and operating conditions in detail is needed. To compensate for this problem, we would like to apply a fault tree technique that can analyze failures by reflecting the type of components, connection status, and operating characteristics of the multi-level inverter. The fault tree analysis may reflect the operation characteristics of the analysis target by logically using the relationship between the causes of system failure to create a fault tree and calculating the probability of system failure. Therefore, logical and probabilistic quantitative results can be derived [22,23,24,25,26,27,28].

In this paper, we analyze the behavioral characteristics of three types of multilevel half-bridge topologies and propose three modes of fault-tree for each topology. Based on MIL-STD-217F, we present and calculate the criteria for selecting part failure rates for major parts. The failure rates of the proposed FTA and part count fault analysis (PCA) using the part count method are compared for each topology. We analyze the impact of changes in temperature, MI, and PF on failure rates and provide a variety of guidelines to select the appropriate topology for stratospheric drones from a reliability perspective.

2. Fault Tree Design Based on the Operating Characteristics of Multilevel Inverter

The main failure factors of multilevel inverters are voltage unbalance and short circuits on the DC link, overvoltage on the AC output side, overcurrent, voltage imbalance, etc. Semiconductor switching devices that repeat ON/OFF at high switching frequencies and capacitors that repeat charging and discharging accordingly are major parts and weak reliability devices. In addition, failures may occur due to electronic components such as a control board and a communication board. In this paper, we analyze the operation characteristics based on the half-bridge, which is a basic module in the inverter, and we design a fault tree that logically shows the relationship with the failure causes. Through this, the failure probability is analyzed for each circuit topology of the multilevel inverter, and the lifetime is predicted.

2.1. Analyze the Mode of Operation for Each Topology

It analyzes the operation of three topologies commonly used in multilevel inverters: Diode Clamped Circuit (DCC), Flying Capacitor Circuit (FCC), and T-Type Neutral Clamped circuit (TNPC). To reflect the failure conditions according to the operating conditions in the fault tree design, it is classified into four types according to the polarity of the output voltage and current and analyzed.

2.1.1. Analysis of DCC Topology Operation

DCC requires a clamping diode to obtain the m-level phase voltage and initially has the advantage that the entire DC link voltage can be charged using a single power source. In addition, switching operation and control techniques are simpler than other multilevel inverters. However, as the number of levels increases, the number of serial connections of diodes increases, making it difficult to keep the voltage of each capacitor uniform and making it difficult to modularize each bridge. The number of switching required to make the m-level is (m−1), the number of capacitors of the direct current link is (m−1), and the number of clamping diodes is (m−1) × (m−2) [29,30,31,32]. Figure 1 shows the operation mode of the DCC. It is classified according to the direction of the output voltage $v_o$ and the output current $i_o$ and analyzes the switching pattern and current flow when forming a 1-level voltage and in zero-level freewheeling mode.

Figure 1 shows the current flow and switching state by dividing the operation into eight types depending on the output voltage, output current polarity, and level formation to analyze the operation of the DCC topology. The switching operation and power flow according to the eight operating states from Figure 1a–h are summarized in

Table 1. Analysis of DCC operating modes.

Current	Voltage	Level	On Switch	Power Flow	Note
Polarity	Polarity	Formation	Operation
Positive	Positive	1 level	S1, S2	C1 discharge	Figure 1a
		Zero level	S2, D5	Freewheeling	Figure 1b
	Negative	−1 level	D3, D4	C2 charge	Figure 1c
		Zero level	D5, S2	Freewheeling	Figure 1d
Negative	Positive	−1 level	S3, S4	C2 discharge	Figure 1e
		Zero level	S3, D6	Freewheeling	Figure 1f
	Negative	1 level	D1, D2	C1 charge	Figure 1g
		Zero level	S3, D6	Freewheeling	Figure 1h

.

When the level is formed, if the output voltage and current polarity are the same, power flows from the DC link to the output terminal and the capacitor goes into discharge mode. Conversely, if the output voltage and current polarity are different, power flows from the output terminal to the DC link, and the capacitor goes into charging mode. At zero level, current flows due to the clamping action of the diode connected to the neutral point, and the output terminal and capacitor are separated.

2.1.2. Analysis of FCC Topology Operation

The FCC is similar in structure to the DCC but uses a capacitor instead of a clamping diode to create the zero-level, allowing for a more modular structure. In addition, by using a capacitor, the internal voltage level can obtain a margin, enabling a stable power supply. However, as the number of levels increases, the control becomes more complicated, switching losses increase, and a large number of capacitors are required. The number of switching required to make the m-level is 2 (m−1), the number of capacitors of the direct current link is (m−1), and the number of flying capacitors is (m−1) (m−2)/2 [33,34,35]. Figure 2 shows the operation mode of the FCC topology, which is analyzed by dividing it into voltage and the current directions, zero-level, and 1-level.

Figure 2 shows the current flow and switching state by dividing the operation into eight depending on the output voltage, output current polarity, and level formation to analyze the operation of the FCC topology. The switching operation and power flow according to the eight operating states from Figure 2a–h are summarized in

Table 2. Analysis of FCC operating modes.

Current	Voltage	Level	On Switch	Power Flow	Note
Polarity	Polarity	Formation	Operation
Positive	Positive	1 level	S1, S2	C1 discharge	Figure 2a
		Zero level	S1, D3	$V_j$ charge	Figure 2b
	Negative	−1 level	D3, D4	C2 charge	Figure 2c
		Zero level	D4, S2	$V_j$ discharge	Figure 2d
Negative	Positive	−1 level	S3, S4	C2 discharge	Figure 2e
		Zero level	D2, S4	$V_j$ charge	Figure 2f
	Negative	1 level	D1, D2	C1 charge	Figure 2g
		Zero level	D1, S3	$V_j$ discharge	Figure 2h

. When the level is formed, the charge/discharge state of the dc link capacitor and the power flow are the same as in DCC, and the flying capacitor is separated from the output stage. When at zero level, zero level is created by the flying capacitor. If the polarity of the output voltage and current are the same, it is discharged, and in the opposite case, it is charged.

2.1.3. Analysis of TNPC Topology Operation

The TNPC is a variant of DCC and consists of four switching elements per leg, which can reduce two diodes. Compared to DCC or FCC, it has the advantage of having fewer series switching devices for one-level output, and even compared to a two-level topology, the voltage applied to the switching devices is halved, which reduces switching losses. However, when implementing more than 5-levels, it is difficult to increase it in a modular form compared to other multi-level inverters, and switching patterns and control are difficult [36,37,38,39,40].

Figure 3 shows the current flow and switching state by dividing the operation into eight types depending on the output voltage, output current polarity, and level formation to analyze the operation of the FCC topology. The switching operation and power flow according to the eight operating states from Figure 3a–h are summarized in

Table 3. Analysis of TNPC operating modes.

Current	Voltage	Level	On Switch	Power Flow	Note
Polarity	Polarity	Formation	Operation
Positive	Positive	1 level	S1	C1 discharge	Figure 3a
		Zero level	S1, D3	freewheeling	Figure 3b
	Negative	−1 level	D4	C2 charge	Figure 3c
		Zero level	S2, D3	freewheeling	Figure 3d
Negative	Positive	−1 level	S4	C2 discharge	Figure 3e
		Zero level	D2, S4	freewheeling	Figure 3f
	Negative	1 level	D1	C1 charge	Figure 3g
		Zero level	D2, S3	freewheeling	Figure 3h

. When the level is formed, the capacitor charging/discharging operation and power flow according to the polarity of the output voltage and current are the same as the DCC. When the level is zero, the output terminal and the capacitor are separated by the operation of S2 and S3 and the clamping operation of D2 and D3 at the neutral point.

2.2. Design a Fault Tree for Each Topology

In this chapter, we design a fault tree that considers the risks that reflect the operating characteristics of the half-bridge for each topology. FTA is a fault tree design method that logically analyzes the relationship between the causes of power converter failures and obtains the probability of a failure of the system. This allows you to derive probabilistic and quantitative results to respond to risks in your system.

Looking at the operation status of each topology analyzed in Section 2.1, the output voltage is repeated at +1 level and zero-level based on one cycle of the output voltage, and the DC link capacitor is charged or discharged depending on the arm current direction. In the other half cycle, the power voltage is repeated at −1 level and zero-level, and the charging and discharging of the DC link capacitor is determined according to the direction of the current. It can be found that the operations of the switching device, diode, and capacitor are complementary operations according to the polarity of the output voltage. Therefore, the design of the fault tree is divided into three categories: “1 level capacitor charging failure”, “1 level capacitor discharging failure”, and “zero level failure”, and each lower level event is designed. For each mode, the failure analysis focuses on the parts connected to the closed circuit where the current is conducted and does not account for conditions where two or more parts fail simultaneously.

2.2.1. DCC Fault Tree Design

Figure 4 shows the fault tree considering the operating characteristics when in 1-level capacitor charging mode. Each sub-step is defined based on 1-level voltage formation and capacitor charging. The [Level formation fault] is designed as an OR-gate combination of [Diode switching failure] and [IGBT S3 switching failure]. The [Diode switching failure] event is independent of the IGBT S1 and S2 control failures, the current path is opened in the event of a D1 or D2 failure and no output voltage level is formed. The [IGBT S3 switching failure] event means that the output voltage will be at 0 level when IGBT S3 fails to switch off. Causes related to IGBT switching-off failure are caused by IGBT self-failure, switching signal failure in the controller, and short circuits between the IGBT collector–emitter. The [Capacitor charging function fault] event is caused by the loss of the capacitor charging function, drift, or damage to the enclosure.

Figure 5 shows the fault tree considering the operation characteristics when in 1-level capacitor discharging mode. Each sub-step is defined based on 1-level voltage formation and capacitor discharge. The [Level formation failure] event is designed as an OR-gate combination of the [IGBT S1 switching ON failure] event and the [IGBT S2 switching ON failure] event, and when IGBT S1 or S2 ON fails, the current path is open and the output voltage level is not formed. Causes related to IGBT switching ON failure are caused by IGBT self-failure, switching signal error in the controller, short circuit between gate-emitter, and open between collector-emitter. The [Capacitor discharging function fault] is designed as an OR-gate combination of the [Capacitor discharging failure] event and the [IGBT S3 switching ON failure] event. The [Capacitor discharge failure] event may cause level formation to fail due to capacitor failure. The [IGBT S3 switching ON failure] event can cause C1 to be short-circuited through S1, S2, S3, and D6 when IGBT S3 is turned OFF, resulting in device failure and level failure.

Figure 6 shows the fault tree considering the operation characteristics when in zero-level mode. Each sub-step is defined based on level voltage formation and capacitor function failure. The [Level formation failure] is designed as an OR-gate combination of [D5 failure] event, [IGBT S2 switching ON failure] event, and [IGBT S1 switching OFF failure] event. In case of D5 failure or IGBT S2 ON failure, the current path is opened to make the zero level. In case of IGBT S1 OFF failure, current is delivered to the output stage through C1 to form 1 level. The [capacitor function failure] event can cause C2 to be short-circuited through D5, S2, S3, and S4 when IGBT S4 OFF fails, resulting in device failure and level failure.

2.2.2. FCC Fault Tree Design

Figure 7 shows a fault tree considering the operation characteristics when in 1-level capacitor charging mode. Each sub-step is defined based on 1-level voltage formation and flying capacitor and capacitor charging. The [Level formation fault] event is independent of the IGBT S1 and S2 control failure, and the output voltage level is not formed because the current path is open when D1 or D2 fails. The [capacitor $V_j$ function failure] event is designed as an OR-gate combination of IGBT S3 and S4 switching OFF failure. When IGBT S3 OFF fails, $V_j$ is short-circuited through S2 and S3, causing device failure and level failure. When IGBT S4 OFF fails, $V_{d}c$ voltage is applied to $V_j$, causing $V_j$ failure and level failure. The [CAPACITOR DISCHARGE FAILURE] event may cause the level formation to fail due to capacitor failure.

Figure 8 shows the fault tree considering the operation characteristics when in 1-level capacitor discharging mode. Each sub-step is defined based on 1-level voltage formation and flying capacitor and capacitor discharging. The [Level formation fault] event occurs when IGBT S1 or S2 ON fails, the current path is open and the output voltage level is not formed. The [capacitor $V_j$ function failure] event is designed as an OR-gate combination of IGBT S3 and S4 switching OFF failure and has the same failure cause as the flying capacitor event in Figure 7. The [Capacitor discharge failure] event is a capacitor failure that can cause level formation to fail.

Figure 9 shows the fault tree considering the operation characteristics when in zero-level mode. Each sub-step is defined based on 1-level voltage formation, flying capacitor, and capacitor discharge. The [Level formation fault] event is designed as an OR-gate combination of the [D3 failure] event, the [IGBT S1 switching ON failure] event, and the [IGBT S2 switching OFF failure] event. In case of D3 failure or IGBT S1 ON failure, the current path to create the zero level is opened and the zero leveler is not formed. In the case of IGBT S2 OFF failure, the current is delivered to the output stage through C1, so the zero level is not formed. In case of IGBT S1 or S2 ON failure, the current path is open and no output voltage level is formed. The [capacitor $V_j$ function failure] event is designed as an OR-gate combination of IGBT S3 and S4 switching OFF failure and has the same failure cause as the flying capacitor event in Figure 7. The [capacitor discharge failure] event is a capacitor failure that can cause the level formation to fail. In the [capacitor $V_j$ function failure] event, $V_{d}c$ voltage is applied to $V_j$ when S4 OFF fails, causing $V_j$ failure and level failure. And when $V_j$ fails, level formation may fail. The [capacitor C1 function failure] event can cause the same level of formation failure when C1 fails.

2.2.3. TNPC Fault Tree Design

Figure 10 shows the fault tree considering the operation characteristics when in level 1 capacitor charging mode. Each sub-step is defined based on 1-level voltage formation and capacitor charging. The [Level formation fault] event is designed as an OR-gate combination of the [D1 failure] event and the [IGBT S3 switching OFF failure] event. In case of D1 failure, regardless of IGBT S1 control failure, the current path is open and the output voltage level is not formed. In the case of IGBT S3 OFF failure, the current is conducted to S3 and D2, resulting in a zero level. The [capacitor function failure] event occurs when IGBT S4 switching OFF fails, and a short circuit occurs with C1 and C2 through S1 and S2, resulting in component failure and level failure. If the C1 capacitor itself fails, the level formation may fail.

Figure 11 shows a fault tree considering the operation characteristics when in 1-level capacitor discharging mode. Each sub-step is defined based on 1-level voltage formation and capacitor discharge. The [Level formation fault] event is designed as an OR-gate combination of the [IGBT S1 switching ON failure] event and the [IGBT S3 switching OFF failure] event. In case of IGBT S1 ON failure, the current path is open and the output voltage level is not formed. When IGBT S3 OFF fails, current is conducted to S3 and D2, causing C1 to be short-circuited, resulting in part failure and level failure. The [capacitor function failure] event has the same failure cause as the C1 capacitor event in Figure 10.

Figure 12 shows the fault tree considering the operation characteristics in zero-level mode. Each sub-step is defined based on the 1-level voltage formation and capacitor function. The [Level formation fault] event is designed as an OR-gate combination of the [D1 failure] event, the [IGBT S2 switching ON failure] event, and the [IGBT S1 switching OFF failure] event. In the case of IGBT S1 OFF failure, the current is delivered to the output terminal through C1 so that zero-level is not formed. In the case of IGBT S2 ON failure or D3 failure, the current path is open and no output voltage level is formed. The [capacitor function failure] event occurs when IGBT S4 OFF fails and C2 is short-circuited through S2, D3, and S4, causing device failure and level failure.

2.3. Part Failure Rate Based on MIL-HDBK-217F

To calculate the failure rate of the failure tree for each topology by reflecting the failure rate in the basic event of the failure tree, it is necessary to calculate the part failure rate for the main parts, IGBT, diode, and capacitor [41,42]. The stratospheric 3-phase multilevel inverter has a rated power of 3000 W and an IGBT rating of 250 V, 55 A. The diode is an IGBT internal body diode, and the zero-level diode of the DCC is rated at 250 V, 40 A. The capacitor specifications reflected in the design have a capacity of 680 μF and an insulation withstand voltage of 250 V. Regarding temperature, the junction temperature of the switching device and the ambient temperature of the capacitor vary depending on the loss and heat dissipation structure. Since many factors other than temperature must be reflected in the failure rate, we would like to analyze trends while setting the temperature as the same for each topology. The junction temperature of the switching element is analyzed in the range of 25 °C to 180 °C, and the ambient temperature of the capacitor is interpreted in the range of −40 °C to 115 °C.

2.3.1. IGBT Failure Rate

MIL-HDBK-217F does not provide failure rates for IGBT components. Since an IGBT is internally composed of a bipolar junction transistor (BJT) and a metal-oxide-semiconductor field-effect transistor (MOSFET) in series, the combination of the two can be used to estimate the IGBT component failure rate [43,44]. The BJT component failure rate is shown in Equation (1).

$${\lambda }_{BJT}={\lambda }_b{\pi }_T{\pi }_A{\pi }_R{\pi }_S{\pi }_Q{\pi }_E[\mathrm{Failures}/{10}^6 \mathrm{h}]$$

(1)

Here, the basic failure rate ${\lambda }_b$ of BJT is 0.00074, the application factor ${\pi }_A$ is 0.7 because it is a switching type, the quality factor ${\pi }_Q$ is 2.4, which is the standard value for military and aviation applications, and the environment factor ${\pi }_E$ is 9.0, which is the value of $G_M$ under the condition that it operates in an environment with large changes in ambient temperature. Temperature factor ${\pi }_T$ is defined by Equation (2), and $T_j$ represents the junction temperature.

$${\pi }_T=\exp \left[-2114\left(\frac{1}{T_J+273}-\frac{1}{298}\right)\right]$$

(2)

Since the power rating factor, ${\pi }_R$ has a rated power of 0.1 W or more, Equation (3) is applied and $P_r$ represents the rated power.

$${\pi }_R={\left(P_r\right)}^{0.37}$$

(3)

The voltage stress factor ${\pi }_S$ is defined by Equation (4), where $V_{Rated\_CEO}$ is the collector-emitter rated voltage at base open and $V_{Applied\_CE}$ is the voltage applied to the device.

$${\pi }_S=0.045\times \exp \left[3.1\left(\frac{V_{Applied\_CE}}{V_{Rated\_CEO}}\right)\right]$$

(4)

The MOSFET component failure rate is given by Equation (5).

$${\lambda }_{MOSFET}={\lambda }_b{\pi }_T{\pi }_A{\pi }_Q{\pi }_E[\mathrm{Failures}/{10}^6 \mathrm{h}]$$

(5)

Here, the basic failure rate ${\lambda }_b$ of MOSFET is 0.012, the application factor ${\pi }_A$ is selected as 10 because the rated power is more than 250 W, and the quality factor ${\pi }_Q$ and environment factor ${\pi }_E$ are the same as BJT. Temperature factor ${\pi }_T$ is defined by Equation (6), and $T_j$ represents the junction temperature.

$${\pi }_T=\exp \left[-1925\left(\frac{1}{T_J+273}-\frac{1}{298}\right)\right]$$

(6)

Since the IGBT is composed of a BJT and a MOSFET in series, if either of them fails, the failure of the IGBT occurs. Therefore, the failure rate of the IGBT is defined as follows through the OR-gate operation of the two devices.

$${\lambda }_{IGBT}[\mathrm{Failures}/{10}^6\mathrm{h}]=1-(1-{\lambda }_{BJT})(1-{\lambda }_{MOSFET})$$

(7)

2.3.2. Capacitor Failure Rate

The capacitor is analyzed as a metalized film capacitor sealed in a durable metal case, and the failure rate equation is as follows.

$${\lambda }_{CAP}={\lambda }_b{\pi }_T{\pi }_C{\pi }_V{\pi }_{SR}{\pi }_Q{\pi }_E[\mathrm{Failures}/{10}^6 \mathrm{h}]$$

(8)

The default failure rate ${\lambda }_b$ for metalized film capacitors is 0.00037 and the series resistance factor ${\pi }_{S}R$ is 1.0. The quality factor ${\pi }_Q$ is 1.5, which is the reference value for military and aviation applications, and the environment factor ${\pi }_E$ is 20 of $G_M$. Temperature factor ${\pi }_T$ is defined by Equation (9), where T is the capacitor ambient temperature.

$${\pi }_T=\exp \left[\frac{-0.15}{8.617\times {10}^{-5}}\left(\frac{1}{T+273}-\frac{1}{298}\right)\right]$$

(9)

The capacitance factor ${\pi }_C$ is defined by Equation (10), where C is the capacitance value $\mathit{\mu }F$ of the capacitor.

$${\pi }_C={\left(C\right)}^{0.09}\left[\mathit{\mu }F\right]$$

(10)

The voltage stress factor ${\pi }_V$ is defined by Equation (11), where $V_{Rated}$ is the rated voltage of the capacitor and $V_{operating}$ is the operating voltage applied to the capacitor.

$${\pi }_V={\left(\frac{S}{0.6}\right)}^5+1,\because S=\left(\frac{V_{operating}}{V_{Rated}}\right)$$

(11)

2.3.3. Diode Failure Rate

The component failure rate of a diode is given by Equation (12).

$${\lambda }_D={\lambda }_b{\pi }_T{\pi }_S{\pi }_C{\pi }_Q{\pi }_E[\mathrm{Failures}/{10}^6\mathrm{h}]$$

(12)

The diode’s basic failure rate ${\lambda }_b$ is 0.025, the contact construction factor ${\pi }_C$ is 1 for metallurgically bonded, the quality factor ${\pi }_Q$ is 2.4 for military and aviation applications, and the environment factor ${\pi }_E$ is 9 for $G_M$. Temperature factor ${\pi }_T$ is defined by Equation (13), where $T_j$ represents the junction temperature.

$${\pi }_T=\exp \left[-3091\left(\frac{1}{T_J+273}-\frac{1}{298}\right)\right]$$

(13)

The electrical stress factor ${\pi }_S$ is equal to Equation (14), where $V_{Applied\_CE}$ is the voltage applied to the diode and $V_{Rated\_CEO}$ is the reverse voltage across the diode.

$${\pi }_S={\left(\frac{V_{Applied\_CE}}{V_{Rated\_CEO}}\right)}^{2.43}$$

(14)

Table 4. The failure rate of IGBT, diode, and capacitor.

Temp	Failures/${10}^4$ h
	IGBT	Diode (in IGBT)	Diode (DCC)	Capacitor
25 (−40)	0.02629370	0.00430735	0.00430735	0.00013098
85 (20)	0.07769091	0.02450135	0.02450135	0.00060481
125 (60)	0.13335677	0.05835091	0.05835091	0.00123467
150 (85)	0.17742397	0.09234005	0.09234005	0.00177865
180 (115)	0.23966516	0.14981587	0.14981587	0.00259040

shows the change in failure rate of IGBTs, capacitors, and diodes as a function of temperature. The temperature was analyzed by dividing the junction temperature of the switching device and the ambient temperature of the capacitor, and the values in parentheses in the table indicate the ambient temperature of the capacitor. IGBT Junction: When the temperature is 125 °C, the failure rate is 0.133 [Failures/${10}^4$ h], and a mean time to failure of 74,986 h and a lifetime of 8.56 years can be expected. If the operating temperature is maintained at 25 °C, the failure rate is significantly reduced to 0.0263 [Failures/${10}^4$ h], resulting in a mean time to failure of 380,319 h and a life expectancy of 43.42 years. In the case of capacitors, the failure rate is relatively good compared to IGBTs at 0.001063 [Failures/${10}^4$ h] under harsh conditions with a temperature of 85 °C and decreases to 0.000131 [Failures/${10}^4$ h] if the ambient temperature is maintained at −40 °C. As for the diode, there is some difference between the diode used in the DCC and the IGBT body diode, and it can be seen that the failure rate is lower than the IGBT and the capacitor under the same temperature condition.

3. Reliability Analysis Based on Operating Characteristics

3.1. Analysis of Failure Rate of Multi-Level Inverter Using Fault-Tree

In this chapter, we analyze the failure rate by reflecting the part failure rate in the failure tree designed for each topology. A failure tree designed with three modes for half a cycle has the same failure rate because the modes are applied repeatedly, and in the next half cycle, all the elements have the complementary operation. Therefore, it should reflect the rate at which the three modes are applied during one cycle. MI determines the ratio of the 1-level capacitor charge/discharge mode to the zero-level mode, and PF determines the ratio of the 1-level capacitor charge mode and the 1-level capacitor discharge mode.

When applying space vector PWM(SVPWM), the maximum output phase voltage is 57.7% of the DC link voltage. Generally, MI is selected between 0.8 and 0.95 based on the rated power, considering the output power margin. The 1-level voltage formation interval and the zero-level voltage formation interval are determined using the average value of the output phase voltage and the DC link voltage according to the MI. When MI is applied to 0.85, the maximum output phase voltage is 49% of the DC link voltage, and when the average value of the output phase voltage is applied, the 1-level voltage formation interval is about 62.4% and the zero-level voltage formation interval is 37.6% in one cycle. If the inverter PF is assumed to be 98% when the motor is running, the capacitor discharge mode is 93.6% of one cycle, and the capacitor charge mode is 6.4% of one cycle during the 1-level voltage formation interval. In this way, the rate at which three fault tree events are applied during a half cycle is defined as Equation (15).

$$\left\{\begin{array}{c}{\displaystyle m1=(\frac{4}{\pi }\times 0.577\times MI)\times (1-\frac{acos(PF)}{\pi })}\hfill \\ {\displaystyle m2=(\frac{4}{\pi }\times 0.577\times MI)\times (\frac{acos\left(PF\right)}{\pi })}\hfill \\ {\displaystyle m3=1-(\frac{4}{\pi }\times 0.577\times MI)\because m1+m2+m3=1}\hfill \end{array}\right.$$

(15)

Here, $m1$, $m2$, and $m3$ represent the rate at which the three fault tree events are applied in a half cycle. $m1$ is the rate of [1-level discharging failure] events, $m2$ is the rate of [1-level charging failure] events, and $m3$ is the rate of [zero-level failure] events.

Table 5. Main part number of each topology for FTA design.

Topology	Parts Type	1-Level Discharging	1-Level Charging	Zero-Level
		Failure (M1)	Failure (M2)	Failure (M3)
DCC	IGBT	3	1	3
	Diode(in IGBT)	0	2	0
	Diode	0	0	1
	Capacitor	1	1	0
FCC	IGBT	4	2	3
	Diode(in IGBT)	0	2	1
	Capacitor	1	1	2
TNPC	IGBT	3	2	3
	Diode(in IGBT)	0	1	1
	Capacitor	1	1	0

shows the number of major parts whose operation characteristics are reflected for each of the three fault tree events by the fault tree design for each topology described in Section 2.2. The failure rate for each fault tree event is calculated by OR combining the number of major components for each mode defined in Table 5.

Using the ratio of the three fault tree events according to Equation (15) and the failure rate for each fault tree event, the half-cycle average failure rate is defined as Equation (16).

$${\lambda }_{x\_half\_w}=m1\times {\lambda }_{x\_half\_M1}+m2\times {\lambda }_{x\_half\_M2}+m3\times {\lambda }_{x\_half\_M3}$$

(16)

Here, ${\lambda }_{x\_half\_w}$ means the weighted average failure rate during the half-bridge half cycle.

x represents three topologies, ${\lambda }_{x\_half\_M1}$ represents the failure rate of the [1-level discharging failure] event, ${\lambda }_{x\_half\_M2}$ represents the failure rate of the [1-level charging failure] event, and ${\lambda }_{x\_half\_M3}$ represents the failure rate of [zero-level failure].

The half-bridge one-cycle failure rate (${\lambda }_{x\_w}$) defined in Equation (17) can be obtained by connecting ${\lambda }_{x\_half\_w}$ with an OR-gate combination. In the same way, using ${\lambda }_{x\_w}$, the failure rates for the single-phase (${\lambda }_{x\_single}$) and three-phase (${\lambda }_{x\_3phase}$) multilevel inverters defined in Equations (18) and (19) can be obtained on an FTA basis.

$${\lambda }_{x\_w}=1-(1-{\lambda }_{x\_half\_w})\times (1-{\lambda }_{x\_half\_w})$$

(17)

$${\lambda }_{x\_single}=1-(1-{\lambda }_{x\_w})\times (1-{\lambda }_{x\_w})$$

(18)

$${\lambda }_{x\_3phase}=1-(1-{\lambda }_{x\_w})\times (1-{\lambda }_{x\_w})\times (1-{\lambda }_{x\_w})$$

(19)

3.2. Comparison of DCC, FCC, TNPC, and MMC

3.2.1. Comparison of Failure Rates based on PCA and FTA

PCA does not consider the operation characteristics of multilevel inverters but simply calculates the failure rate by OR combining the type and number of parts. The failure rates based on PCA and the proposed FTA are compared for three topologies.

Table 6. Part type and Number by topology.

Topology	Parts Type and Number
	IGBT	Diode(in IGBT)	Diode(DCC)	Capacitor
DCC	4	4	2	2
FCC	4	4	0	3
TNPC	4	4	0	2

shows the types and number of components for the three topologies.

Figure 13 shows the failure rates of PCA and FTA methods for the half-bridge as a function of temperature. Figure 13a shows the failure rate calculated by the PCA method using Table 2, and Figure 13b shows the failure rate calculated by the FTA method using Equations (15)–(17) when MI is 0.85 and PF is 0.98. The results show that the failure rate of DCC > FCC > TNPC is higher in the PCA method, but the failure rate of FCC > TNPC > DCC is higher in the FTA method. When comparing the average failure rate, FCC increased the failure rate by about 18.8% compared to PCA, and TNPC increased the failure rate by about 7.7% in the FTA method. DCC decreased by about 0.9%, and the difference in failure rate between DCC and TNPC was about 0.5% in the FTA method.

Figure 14 shows the comparative analysis of each topology for a three-phase multilevel inverter using Equation (19) when MI is 0.85 and PF is 0.98 based on FTA. Compared to the half-bridge, the failure rate increases overall and the expected lifetime is 862 days for DCC, 761 days for FCC, and 855 days for TNPC at 40 °C. The different results for PCA and FTA can be seen as a reflection of the risks associated with the drive characteristics.

3.2.2. Comparison of Failure Rate Based on Modulation Ratio and Power Factor

In this chapter, we use the advantages of the proposed FTA method to see how the failure rate is affected when the MI value is varied and when the PF value is varied.

Figure 15 shows the results of the failure rate when MI and PF are varied at 80 °C conditions. Figure 15a shows the change in the failure rate of the half-bridge when MI is varied from 0.7 to 0.95 at 0.98 PF. A larger MI means a larger proportion of the 1-level voltage formation interval is applied, and the failure rate of DCC and TNPC decreased by 1.83% and 1.58%, respectively, when MI was changed from 0.7 to 0.95, while FCC increased by 2.7%. Figure 15b shows the change in the failure rate of the half-bridge when PF is varied from 0.9 to 1.0 when MI is 0.83. It means that the higher the PF, the greater the proportion of the 1-level discharge interval is applied, and DCC, FCC, and TNPC increased by 3.54%, 2.7%, and 1.69%, respectively, when PF changed from 0.9 to 1.0.

Figure 16 shows the change in half-bridge failure rate values when MI changes from 0.76 to 1.0 and PF changes from 0.88 to 1.0 under 80 °C condition. Figure 16a is the failure rate value of FCC, which shows that the failure rate is proportional to PF and MI, and the minimum failure rate is 0.4127 [Failures/${10}^4$ h] and the maximum failure rate is 0.4345 [Failures/${10}^4$ h]. In terms of life expectancy, it is reduced by about 5% from 1010 days to 956 days. Figure 16b shows the result values for the TNPC, where failure rates and PF are proportional and MI is inversely proportional. The minimum failure rate is 0.6309 [Failures/${10}^4$ h] and the maximum failure rate is 0.3707 [Failures/${10}^4$ h], which is a decrease of about 3.5% from 1154 days to 1115 days in terms of expected lifetime.

4. Conclusions

This paper analyzes the failure rate from a reliability perspective for the multilevel inverter topology applicable to stratospheric drones. For each topology, we analyze the operation characteristics of the half-bridge and classify them into three operation modes, and the FTA is designed. The three FTAs for each half-bridge are easy to apply to single-phase and three-phase and have the advantage of being able to analyze reliability according to changes in MI and PF that cannot be confirmed in the PCA. The comparison of failure rates by topology between PCA and FTA shows that the values and rankings of the failure rates are different. Since PCA only considers the type, number, and failure dependence of simple components, it cannot reflect the operation characteristics of inverters by topology.

Using the proposed three FTAs for each half-bride, the failure rate and lifetime of a three-phase multilevel inverter were predicted. The effect of the variation between MI value and PF value on the failure rate was analyzed, respectively, and the failure rate was affected when the three indicators of temperature, MI, and PF changed together. In addition to the FTA-based failure rate analysis that considers conventional voltage and current stresses and voltage margins, the proposed method designs the FTA to reflect PF and MI variations. It provides various guidelines for selecting the topology of multilevel inverters from the reliability point of view. The three topologies show high failure rate in order of FCC > TNPC > DCC. In terms of reliability, DCC is the best, but when compared to TNPC, the average failure rate of 3phase is about 0.34% lower. The difference between DCC and TNPC in terms of failure rate shows a slight difference, but TNPC is better than DCC in terms of efficiency [45,46]. Among the three topologies compared in this paper, TNPC can be considered the most suitable topology for stratospheric drones.