Circuit Techniques for Immunity to Process, Voltage, and Temperature Variations in the Attachable Fractional Divider

Round 1

Reviewer 1 Report

The manuscript “Circuit Techniques for Immunity to PVT Variations in the Attachable Fractional Divider” shows some interesting results. However, I think that this manuscript requires major improvements in the following areas:

1-     Authors must ensure that the quality of English is improved (i.e., make all efforts to rectify any grammatical mistakes, typos, double spaces, missing spaces, subscripts, superscripts etc.). Minor editing of English language required. 

2-     In the Abstract, authors must write the full names of all abbreviations.

3-     The Abstract is usually written without references. Authors must remove the implemented references in the abstract.

4-     Keywords are too much. Authors must select only around 5 suitable keywords.

5-     In the introduction part, the introduction does not provide sufficient background about the attachable fractional divider. The research significance and the difference between this work and previous works are still missing. The authors must motivate that in the introduction part with one or two sentences and supported them with suitable references.

6-     In Figs. 3 and 4, the architecture of the developed fractional divider, how about the models of the used component?

7-     Authors must clarify the specific improvements in this work regarding the methodology compared to your previous work  [refs. 10, and 22] and they must mention what further controls should be considered.

8-     What is the meaning of the negative values of linearity performance of the 5-bit PI. Authors must give some explanation about that.

9-     It will be better to compare the performance of this work with previously reported based works (One more Table is required). Authors must use suitable recent references

Minor editing of English language is required. 

Author Response

Thank you very much for taking the time to review this manuscript. Please find the detailed responses below and the revisions and corrections in the re-submitted files.

>1-     Authors must ensure that the quality of English is improved (i.e., make all efforts to rectify any grammatical mistakes, typos, double spaces, missing spaces, subscripts, superscripts etc.). Minor editing of English language required.

-----We’ve reviewed our entire paper and addressed identified errors.

>2-     In the Abstract, authors must write the full names of all abbreviations.
----- Thank you for your comment. We’ve revised and wrote full names for all abbreviations.

>3-     The Abstract is usually written without references. Authors must remove the implemented references in the abstract.

----- Thank you for your comment. We’ve removed them.

>4-     Keywords are too much. Authors must select only around 5 suitable keywords.

----- Thank you for your comment. We’ve reduced keywords and 5 words/phrases are used.

>5-     In the introduction part, the introduction does not provide sufficient background about the attachable fractional divider. The research significance and the difference between this work and previous works are still missing. The authors must motivate that in the introduction part with one or two sentences and supported them with suitable references.

----- Thank you for your helpful feedback. We've updated the introduction, emphasizing differences between previous work and ours when obtaining a fractional-N PLL.

>6-     In Figs. 3 and 4, the architecture of the developed fractional divider, how about the models of the used component?

----- Thank you for your valuable feedback. We’ve added the conceptional block diagram (Fig 4(a)) to show how each output of paths (coarse, fine, and fractional) are determined. In actual implementation, both the coarse path and the fine path are created with RTL. The fractional path is made with a combination of RTL and an analog circuit, PI.

>7-     Authors must clarify the specific improvements in this work regarding the methodology compared to your previous work  [refs. 10, and 22] and they must mention what further controls should be considered.

----- Thank you for your comment. In our previous work, we have not provided all techniques and measurement results specifically in relation to PVT variations. In this article, we have provided detailed circuit techniques for the phase interpolator, a critical analog circuit in the fractional divider, emphasizing its immunity to PVT variations. Additionally, we have included a comprehensive set of measurement results with an eye towards mass production. We believe these additions enhance the completeness of our work on the proposed fractional divider.

>8-     What is the meaning of the negative values of linearity performance of the 5-bit PI. Authors must give some explanation about that.

----- Thank you for your inquiry. For instance, the negative values of PI’s linearity with LSB of 16ps occurs when the actual step is less than 16ps for DNL. Similarly, the negative INL occurs when the difference between the actual transfer curve and the ideal transfer curve, in this case interpolated time vs code, is negative.

>9-     It will be better to compare the performance of this work with previously reported based works (One more Table is required). Authors must use suitable recent references

----- Thank you for your comment. We focus on both design efficiency to meet market opportunities and low degradation in terms of jitter and reference spur. About the first one, thanks to its attachable design, it expedites time-to-market with small design effort. For the other, we achieve them with the developed phase interpolator. In this article, we introduce circuit techniques to obtain immunity to PVT used in the phase interpolator and measurement results of fractional-N PLL with the proposed divider.

Author Response File: Author Response.pdf

Reviewer 2 Report

This paper presents the design of a fractional-N PLL in a 12 nm FinFET CMOS process. The proposed divider has spread-spectrum clocking (SSC) capability and provides immunity to PVT variations. It is interesting for readers and organized well. There are some minor issues that need to be considered.

1. The measured integrated RMS jitter seems not so good. Please give some necessary discussions.

2. It is suggested to provide more measurement results under PVT variations.

3. Compared to the state-of-the-art works, what are the advantages of the proposed fractional divider?

Author Response

Thank you very much for taking the time to review this manuscript. Please find the detailed responses below and the revisions and corrections in the re-submitted files.

>1. The measured integrated RMS jitter seems not so good. Please give some necessary discussions.

----- Thank you for your comment. We focus on both design efficiency to meet market opportunities and low degradation in terms of jitter and reference spur. About the first one, thanks to its attachable design, it expedites time-to-market with small design effort. For the other, we achieve them with the developed phase interpolator. In this article, we introduce circuit techniques to obtain immunity to PVT used in the phase interpolator and measurement results of fractional-N PLL with the proposed divider.

>2. It is suggested to provide more measurement results under PVT variations.

----- Thank you for your valuable feedback. We’ve added the summary table of PVT dependency (Table3) and explanation in terms of the maximum deviation from the modulation setting.

>3. Compared to the state-of-the-art works, what are the advantages of the proposed fractional divider?

-----The advantages of our fractional divider are suitability for various types of integer-N PLLs, including ring-PLLs, LC-PLLs.

That is because routing sensitive signals between an existing integer-N PLL and the fractional divider is necessary bare minimum.

We've updated the introduction, emphasizing differences between previous work and ours when obtaining a fractional-N PLL.

Author Response File: Author Response.pdf

Reviewer 3 Report

Specific comments and recommendations:

1) It is not acceptable to include abbreviations in article titles, and this should be avoided;

2) In my opinion, the abstract needs to be revised. It has to contain a brief description of the work performed, indicating some more important results in numerical form. Also, citations of literary sources must be removed from it;

3) In all figures that contain electronic circuits, it should be indicated which are created by the authors and which of them are used off-the-shelf from the literature;

4) It is not clear whether the results presented in Section 4 are based on experimental studies or are obtained only from computer simulations. In my opinion, for the selected CMOS technology, verification through experimental research is particularly important to prove the effectiveness;

5) The authors of this manuscript should perform a more detailed comparative analysis based on Table 3. In Table 3, it is good to include only publications from the last five years because of the selected CMOS implementation technology, without reducing the number of investigated schemes;

6) Some additional parameters (such as DNL and INL and others) have to be included in Table 3 since it is not clear from the specified parameters what are the advantages and disadvantages of the proposed integrated circuit.

In my opinion, minor editing of the English language required.

Author Response

Thank you very much for taking the time to review this manuscript. Please find the detailed responses below and the revisions and corrections in the re-submitted files.

>1) It is not acceptable to include abbreviations in article titles, and this should be avoided;

----- Thank you for your comment. We’ve revised and wrote full name in the title.

>2) In my opinion, the abstract needs to be revised. It has to contain a brief description of the work performed, indicating some more important results in numerical form. Also, citations of literary sources must be removed from it;

----- Thank you for your comment. We’ve removed citations in the abstract.

>3) In all figures that contain electronic circuits, it should be indicated which are created by the authors and which of them are used off-the-shelf from the literature;

----- Thank you for your helpful feedback. For the circuit diagrams from the literature, we’ve added citations in their figure captions.

>4) It is not clear whether the results presented in Section 4 are based on experimental studies or are obtained only from computer simulations. In my opinion, for the selected CMOS technology, verification through experimental research is particularly important to prove the effectiveness;

----- Thank you for your helpful feedback. The results presented in Section 4 are all measured results. We’ve made it clear by putting the word ‘measured’ in figure captions and main text.

>5) The authors of this manuscript should perform a more detailed comparative analysis based on Table 3. In Table 3, it is good to include only publications from the last five years because of the selected CMOS implementation technology, without reducing the number of investigated schemes;

-----Thank you for your valuable feedback. We focus on both design efficiency to meet market opportunities and low degradation in terms of jitter and reference spur. About the first one, thanks to its attachable design, it expedites time-to-market with small design effort. For the other, we achieve them with the developed phase interpolator. The advantages of our fractional divider are suitability for various types of integer-N PLLs, including ring-PLLs, LC-PLLs. That is because routing sensitive signals between an existing integer-N PLL and the fractional divider is necessary bare minimum. We've updated the introduction, emphasizing differences between previous work and ours when obtaining a fractional-N PLL. We’ve updated our comparison table, including only publications from the last five years.

>6) Some additional parameters (such as DNL and INL and others) have to be included in Table 3 since it is not clear from the specified parameters what are the advantages and disadvantages of the proposed integrated circuit.

-----Thank you for your comment. However, we cannot evaluate linearity of the PI directly because of our product evaluation boards’ specifications. If the fabricated PI’s linearity was degraded, we would find its bad effects in the performances such as fractional spur, frequency difference, modulation depth.

Author Response File: Author Response.pdf

Reviewer 4 Report

This paper is evaluated as an excellent result that presents a very efficient idea in terms of signal noise. Both the system concept of the proposed idea and its expression in terms of detailed circuit implementation were written accurately and in detail. In addition, the measurement results of the manufactured chip confirmed sufficient performance under given conditions. Therefore, there will be no problem in publishing it immediately in the judgment of this reviewer.

Author Response

Thank you very much for taking the time to review this manuscript. For your information, we’ve received comments from the other reviews, so we’ve revised the paper. Thank you again.

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

Authors have been revised and corrected reviewer's comments. I suggestion this manuscript can be accepted for publication in your journal in this status.

Reviewer 3 Report

Some, minor editing of the English language is required.

In my opinion, the authors have tried to implement all the remarks and recommendations given in the review. I propose that this manuscript be accepted for publication in the journal.