# A New Design Technique for a High-Speed and High dV/dt Immunity Floating-Voltage Level Shifter

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## Abstract

**:**

^{2}active area with the 0.18 μm BCD process.

## 1. Introduction

_{HV}of the half-bridge driver, and the high-voltage VDDH of the floating power rail is equal to VSSH + VCC.

_{HV}, and the rising speed is >200 V/ns. This dVSSH/dt change is coupled to the level shifter through a bootstrap capacitor. Since the level shifter can perform voltage conversion between the low-voltage domain and the high-voltage domain, MH1 and MH2 are high-voltage transistors, whose parasitic capacitance is large. The parasitic capacitance will generate a charging or discharging current when dV/dt happens, which will interfere with the level shifter’s normal operation and cause errors in the driver’s logic voltage of the high-voltage domain [10,11,12]. In Figure 2, it can be seen that under the action of the bootstrap capacitor C

_{BOOT}, VDDH changes with VSSH, and dVDDH/dt is approximately equal to dVSSH/dt. However, since the input MOS device MH1 of the level shifter is a high-voltage transistor, there is a large parasitic capacitance Cpar at node A. The rapid change of the VDDH acts on Cpar to generate a large current, which pulls down the voltage of node A. When the noise amplitude (=R × Cpar × dVSSH/dt) generated at node A is larger than (V

_{BOOT}− V

_{T}), the recovery circuit of the subsequent stage may transmit the noise signal by mistake, where V

_{BOOT}is equal to VDDH − VSSH. Therefore, the dV/dt immunity capability of the driver is limited by the parasitic capacitance of the HV transistor of the level shifter.

## 2. Previous Level Shifter

## 3. Proposed Enhanced Level Shifter

_{NLD3}and M

_{NLD4}are connected to the low-voltage rail power supply VDDL to bear high voltage, preventing the breakdown of the low-voltage transistors M1 and M2. The M5 and M6 transistors are used in the form of diodes, with their sources connected to the floating power supply ground VSSH to ensure that the voltages of node A and node B can be higher than VSSH − V

_{TH}(V

_{TH}is the threshold voltage of the MOSFET). This prevents the drain-source voltage of the M7 and M8 devices from exceeding the safe voltage range. A narrow pulse generation circuit is adopted to generate the instantaneous driving signal and speed up the operation of the level shifter [18]. Additionally, the Fast-Slewing Circuit that was added to the circuit can speed up the voltage conversion rate of the level shifter even more, eliminating the issue of various mismatch delays.

_{A}− VSSH and V

_{B}− VSSH are low voltage and high voltage, respectively. When VSSH and VDDH quickly transition from high voltage to low voltage, both V

_{A}− VSSH and V

_{B}− VSSH rise to high voltage. When VSSH and VDDH transition from low voltage to high voltage, both V

_{A}− VSSH and V

_{B}− VSSH can drop to low voltage. Therefore, the dV/dt Noise Shielding Circuit is meant to maintain the level shifter’s output in order to avoid the succeeding stage circuit from receiving the erroneous signal output of the level shifter.

#### 3.1. Strategy for the Enhanced Level Shifter

#### 3.2. The Propagation Delay of the Proposed Level Shifter

_{A}is equal to VDDH, and V

_{B}is equal to VSSH. The signal transmission process of the level shifter is as follows:

- (1)
- When the VIN changes from low voltage to high voltage, the generation circuit, which consists of a NAND gate, a capacitor, and several inverters, generates a voltage pulse on the rising edges of the VIN signal. The delay in this process is called T
_{r0}, which is determined by the delay of the NAND gate. - (2)
- When the voltage pulse generates, the input transistor M1 is turned on, and the voltage V
_{A}at node A begins to drop rapidly. The delay in this process is called T_{r1}. The strong pull-down capability of M1 will briefly provide a large current to the branch where node A is located to increase the response speed of node A. - (3)
- The current M7 is mirrored by the M9. Due to the small current of M10, the current of M9 is much greater than that of M10, so the potential at node C is rapidly raised to VDDH. The T
_{r2}is the transmission delay from node A to node C, which is determined by the delay of the current comparator. - (4)
- The edge detection circuit can identify the rising edge signal of node C. When V
_{C}becomes high, a short pulse signal is generated at node S under the action of the delay chain composed of INV1-INV3 and NAND1. T_{r3}is the delay of the edge detection circuit. - (5)
- The generation of a short pulse signal V
_{S}triggers the flipping voltage of NAND4. At this point, the VOUT transitions from low to high and remains at VDDH until a short pulse occurs at node R. The delay between V_{S}and VOUT is described by T_{r4}, which is the delay of NAND4.

_{D}is slower than the ascent speed of V

_{A}, the drop of V

_{D}is not detected by the edge detection circuit and is just prepared for the next reset. Therefore, when the input signal VIN changes from low to high, the speed at which the voltage at node D changes has no effect on the circuit.

_{d_f}of the signal consists ofT

_{f0}, T

_{f1}, T

_{f2}, T

_{f3}, T

_{f4}, T

_{f5}, and T

_{f6}. Due to the good symmetry of the proposed level shifter, T

_{r0}is equal to T

_{f1}, T

_{r1}is equal to T

_{f2}, T

_{r2}is equal to T

_{f3}, T

_{r3}is equal to T

_{f4}, and T

_{r4}is equal to T

_{f5}. Therefore, it can be seen that T

_{d_f}has two more delay items, T

_{f0}and T

_{f6}, than T

_{d_r}, which are the delays of the two NAND gates. Therefore, T

_{d_r}is smaller than T

_{d_f}.

#### 3.3. The dV/dt Immunity of the Proposed Level Shifter

## 4. Simulation Results

_{S}and V

_{R}have no erroneous logic signals during the period when the input signal VIN is high, the output signal VOUT is not disturbed by dV/dt noise, and the state remains unchanged. Therefore, this can demonstrate that the level shifter proposed in this paper can achieve ±500 V/ns dV/dt immunity, which is also suitable for other supply voltages and processes. Figure 13 shows the layout of the proposed level shifter. The chip area is only 127 μm × 178 μm at the 0.18 μm BCD process.

## 5. Conclusions

^{2}active area. The FOM is very small, which is only 0.041. The suggested level shifter can be utilized in multi-MHz converters because of its low propagation delay and its ability to provide 500 V/ns of slewing immunity, making it suitable for drivers of wide-bandgap power device applications.

## Author Contributions

## Funding

## Data Availability Statement

## Acknowledgments

## Conflicts of Interest

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**Figure 8.**The suggested level shifter’s switching operation: (

**a**) low-to-high switching operation; (

**b**) high-to-low switching operation.

**Figure 11.**Simulation results of the proposed level shifter’s delay: (

**a**) rising delay; (

**b**) falling delay.

Latch Name | [13] | [14] | [19] | [20] | This Work |
---|---|---|---|---|---|

Year | 2016 | 2015 | 2019 | 2021 | 2023 |

Process | 0.18 μm CMOS | 0.5 µm UHV | 0.18 μm CMOS | 0.5 μm BCD | 0.18 μm BCD |

Voltage (V) | 20 | 700 | 50 | 30 | 200 |

Delay (ns) | 0.37 | 20 | 0.53 | 0.66 | 1.49 |

dV/dt immunity | 30 | 120 | 200 | 250 | 500 |

FoM | 0.1 | 0.06 | 0.058 | 0.044 | 0.041 |

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**MDPI and ACS Style**

Guo, M.; Wang, L.; Wang, S.; Zhao, Y.; Li, B.
A New Design Technique for a High-Speed and High dV/dt Immunity Floating-Voltage Level Shifter. *Electronics* **2023**, *12*, 4841.
https://doi.org/10.3390/electronics12234841

**AMA Style**

Guo M, Wang L, Wang S, Zhao Y, Li B.
A New Design Technique for a High-Speed and High dV/dt Immunity Floating-Voltage Level Shifter. *Electronics*. 2023; 12(23):4841.
https://doi.org/10.3390/electronics12234841

**Chicago/Turabian Style**

Guo, Min, Lixin Wang, Shixin Wang, Yuan Zhao, and Bowang Li.
2023. "A New Design Technique for a High-Speed and High dV/dt Immunity Floating-Voltage Level Shifter" *Electronics* 12, no. 23: 4841.
https://doi.org/10.3390/electronics12234841