# A Surface Potential Model for Metal-Oxide-Semiconductor Transistors Operating near the Threshold Voltage

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Numerical Device Simulation

_{a}= 2 × 10

^{17}cm

^{−3}. The source and drain regions were doped with donors at a concentration of N

_{d}= 10

^{20}cm

^{−3}and the junction depth was approximately 0.2 μm. Portions of the source and drain regions were placed under the gate electrode. A constant electron mobility of 1200 cm

^{2}/V-s was assigned to eliminate the mobility degradation factor in the numerical simulation. A simulation was performed for each gate length (L

_{g}) to obtain the transconductance according to the I

_{d}-V

_{g}curves at V

_{d}= 0.05 V.

_{d}-V

_{g}curves for devices with different lengths. The current of the device with L

_{g}= 0.7 μm is higher than that with L

_{g}= 10 μm. However, the slope of the subthreshold current is similar between the curves for devices with different gate lengths. The threshold voltages of the two devices do not exhibit significant difference. This implies that conventional short-channel effects are not evident in the simulation study for devices with L

_{g}= 0.7 μm. The transconductance of field-effect transistors depends on the channel length. Therefore, the simulated transconductance was normalized to 1/L

_{g}, as shown in Figure 3. The transconductance increases with the formation of inversion carriers in the channel. For the transistor with L

_{g}= 10 μm, the transconductance approached a constant value as the gate voltage increased further. The normalized transconductance increased slightly with decreasing gate length. This was caused by a reduction in the channel length owing to encroachment from the source and drain regions. However, the device with L

_{g}= 0.7 μm showed an evident transconductance overshoot at the gate bias just above the threshold voltage. The transconductance decreased by more than 10% as V

_{g}increased from 1 to 5 V. Because the carrier mobility in the simulation was constant, the influence of mobility degradation on the transconductance could be neglected.

_{g}= 0.5 V was extracted from the simulation results with different gate voltages. Current density J and electron concentration n in the middle of the channel were verified for a transistor with L

_{g}= 0.7 μm. Figure 4 shows the depth profiles of the electron concentration as a function of V

_{g}. Although both n and J increased with the gate bias, ∆n/n remains similar while ∆J/J decayed more than 10% when V

_{g}increased from 1 to 5 V. Clearly, the decay in current density was related to the transconductance overshoot while the amount of inversion carriers in the channel was irrelevant. Figure 5 shows the magnitude of the lateral electric field along the y direction in the middle of the channel at L

_{g}= 0.7 μm. Interestingly, the magnitude of the electric field at V

_{g}= 1 V was larger than that at 5 V, with a difference of approximately 10%. This suggests that the overshoot in the transconductance was caused by a change in the lateral electric field. However, the magnitude of the lateral electric field was much smaller than that of the vertical field. This results in difficulty to further analyze the two-dimensional electric field. Therefore, a surface potential model should be developed.

## 3. Analytical Modeling of Surface Potential

_{i}along the channel region can be approximated as

_{d}. Based on the quasi-two-dimensional Poisson’s equation [13,14], ${\mathrm{Q}}_{\mathrm{i}}$ can be derived from

^{16}cm

^{−3}to describe the evolution of the surface potential in the junction regions. The effective junction doping is lower than that in the numerical simulation because of the strong perturbation of the gate bias on the two-dimensional electrostatics near the junctions.

## 4. Discussion

_{d}= 10

^{20}cm

^{−3}. Electrons accumulated in these n-type regions. The influence of hole concentration on the surface potential can be ignored. Only electrons and ionized donors were considered in Equation (15). Figure 8 shows the increase of the surface potential at the edges of the gate electrode. The surface potential predicted by the analytical model matches well with that obtained from the numerical simulation. This confirms that Equations (15) and (18) capture the potential change in the n-type source and drain regions.

_{g}= 0.7 μm. However, the transconductance overshoot in the short-channel device is significant. This is because of the high ratio of the widening effect in the channel length. In fact, the potential change around the source and drain junctions is similar between devices with L

_{g}= 0.7 and 10 μm. The flooding of inversion carriers is expected to occur in advanced non-planar devices. However, its influence on the widening of the channel length needs further investigation. The formation of inversion carriers in non-planar devices is hard to predict because of strong three-dimensional effects. The channel widening effect only becomes evident when the carrier flooding occurs at the major current conducting path.

## 5. Conclusions

## Author Contributions

## Funding

## Data Availability Statement

## Acknowledgments

## Conflicts of Interest

## References

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**Figure 2.**Numerical simulation result showing the I

_{d}-V

_{g}curves for devices with different gate lengths.

**Figure 3.**Numerical simulation result showing the normalized transconductance as a function of gate bias and length.

**Figure 4.**Depth profiles of electron concentration in the middle of the channel with a gate length of 0.7 μm obtained from numerical simulation.

**Figure 5.**Depth distribution of lateral electric field in the middle of the channel with a gate length of 0.7 μm extracted from the result of numerical device simulation.

**Figure 6.**Surface potential for a p-type substrate in the strong inversion regime based on Equations (9) and (11).

**Figure 7.**Surface potential as a function of the gate bias calculated by Equations (15) and (18) regarding an n-type substrate in the accumulation regime.

**Figure 8.**Comparison of the distributions of the surface potential along the channel obtained from the analytical model and numerical simulation.

**Figure 9.**Comparison between the magnitude of the lateral electric field in the middle of the channel extracted from the results of numerical simulation and analytical model.

**Figure 10.**Schematic showing the electric field and channel length (

**a**) before and (

**b**) after the flooding of inversion carriers in the channel.

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**MDPI and ACS Style**

Chow, H.-C.; Lee, B.-W.; Cheng, S.-Y.; Huang, Y.-H.; Chang, R.-D.
A Surface Potential Model for Metal-Oxide-Semiconductor Transistors Operating near the Threshold Voltage. *Electronics* **2023**, *12*, 4242.
https://doi.org/10.3390/electronics12204242

**AMA Style**

Chow H-C, Lee B-W, Cheng S-Y, Huang Y-H, Chang R-D.
A Surface Potential Model for Metal-Oxide-Semiconductor Transistors Operating near the Threshold Voltage. *Electronics*. 2023; 12(20):4242.
https://doi.org/10.3390/electronics12204242

**Chicago/Turabian Style**

Chow, Hwang-Cherng, Bo-Wen Lee, Shang-Ying Cheng, Yung-Hsuan Huang, and Ruey-Dar Chang.
2023. "A Surface Potential Model for Metal-Oxide-Semiconductor Transistors Operating near the Threshold Voltage" *Electronics* 12, no. 20: 4242.
https://doi.org/10.3390/electronics12204242