Ultra-Low-Power Compact Neuron Circuit with Tunable Spiking Frequency and High Robustness in 22 nm FDSOI

Abstract

Recent years have seen an increasing popularity in the development of brain-inspired neuromorphic hardware for neural computing systems. However, implementing very large scale simulations of neural networks in hardware is still an open challenge in terms of power efficiency, compactness, and biophysical resemblance. In an effort to design biologically plausible spiking neuron circuits while restricting power consumption, we propose a new subthreshold Leaky Integrate-and-Fire (LIF) neuron circuit designed using 22 nm FDSOI technology. In this circuit, problems of large leakage currents and device mismatch are effectively reduced by deploying the back-gate terminal of FDSOI technology for a tunable design. The proposed neuron is able to operate in two spiking frequency modes with tunable bias parameter setting of key transistors, and it results in complex firing behaviors, such as adaptation, chattering, and bursting, through varying bias voltages. We present circuit post-layout simulation results and demonstrate the biologically plausible neural dynamics. Compared with published state-of-the-art neuron circuits, the circuit dissipates ultra-low energy per spike, on the order of femtojoules per spike, at firing rates ranging from 30 Hz to 1 kHz. Furthermore, the circuit is proven to maintain a good robustness over process variation and Monte Carlo analysis, with relative error 3.02% at a firing rate of approximately 67.1 Hz.

1. Introduction

The sophistication of artificial neural networks (ANNs) algorithms is constantly advancing. However, traditional Von Neumann-based computers are plagued by “storage access bottlenecks”, leading to inefficient computing abilities and high power consumption that fall short of the demands posed by complex AI algorithms [1,2,3]. In order to solve these problems, brain-inspired spiking neural networks (SNNs) have emerged as the third generation of ANNs, mimicking biological brain processes in hardware [4,5,6,7,8,9]. The basic computing unit in a spiking neural network is the neuron, which communicates with its peers via synapses using electrical impulses known as spikes [10,11,12,13].

Several brain emulation engines have been developed, based on mixed-signal neuromorphic circuits, to improve the efficiency of brain-inspired computing [14,15,16]. To emulate brain-like functionality, a very large number of neurons are required in SNNs. As a result, neuron cells are considered as an efficient component with respect to saving power consumption and silicon real estate [17,18,19]. This also highlights the need for simple neuron circuits with a minimum number of transistors and high computing efficiency. Over the last few decades, the Resonate and Fire [20], Hindmarsh–Rose [21], Mihalas–Niebur, and Izhikevich [22,23] models have been the primary sources of inspiration for the development of next-generation neuromorphic circuits. Of all neuron models, the Leaky Integrate-and-Fire (LIF) neurons are claimed to be compact and more computationally efficient. Nevertheless, standard design methods of LIF neurons do not provide adequate firing behaviors and lead to bulky areas and high power consumption. Therefore, various circuits such as voltage-amplifier, tau-cell, low-pass filter (LPF), and differential pair integrator (DPI) have been used to develop and generalize the operation of the traditional neurons [24,25,26,27]. Moreover, the circuitry parts of a DPI-based subthreshold neuron presented in [24,25] can be reconfigured using the simplest low-voltage analog circuits to offer a silicon neuron with the capability of operating under ultra-low-voltage supplies, which provides the potential for subthreshold neuron circuit design.

To solve the energy issue, transistors are preferably biased in the subthreshold region. However, nano-scale CMOS devices suffer from significant leakage currents and device mismatch issue in subthresholds [28]. Hence, emerging technologies such as Fully Depleted Silicon on Insulator (FDSOI) have emerged that show superior performance in leakage and power consumption [29,30]. Using back-gate bias is a new possibility in FDSOI technology to tune circuit performance. In this paper, for the first time, a novel neuron design is introduced that utilizes a 22 nm FDSOI process. This design allows the back-gate voltage to modulate the spiking frequency of the compact LIF neuron, while keeping the leakage unaffected. The neuron operates in the subthreshold region, which can display complex firing behaviors, and consumes an ultra-low energy per spike on the order of a few femtojoules. The final layout of the core neuron is only 484 μm² in size.

The rest of this paper is organized as follows: Section 2 demonstrates the feasibility of implementing biophysically complex neural dynamics using ultra-low-power analog circuits in advanced scaled FDSOI processes, while also addressing leakage currents and device mismatch effects in neuron design. An analysis of the neuron operation and post layout optimization is also presented in Section 2. Post-layout simulation analysis, including complex firing behavior and variable frequency operation through tunable bias parameter settings, is presented in Section 3. The paper also quantifies the impact of device mismatch through Monte Carlo analysis and validates neuron performance against process variations and parasitic components. Finally, Section 4 concludes this brief.

2. FDSOI-Based LIF Neuron Circuit

2.1. Advantages of FDSOI Technology in Neuron Circuit Design

Neuron circuits typically employ subthreshold-operated transistors with currents ranging from fractions of picoamperes to hundreds of nanoamperes [24,25,26,27,28,29,30]. However, non-ideal effects of advanced complementary metal–oxide–semiconductor (CMOS) technology nodes, such as drain-induced barrier lowering (DIBL), gate-induced drain leakage (GIDL), or random dopant fluctuation (RDF), can lead to leakage currents in the picoampere range and bring serious impacts for the functionality of subthreshold neuron circuits. The approach which utilizes above-threshold neuron circuit design has been proposed to mitigate leakage current effects; it can accelerate time constants by a factor of 1000 [31], but requires giving up the capacity to optimally process slowly changing synapse current signals. Another option is to employ switched capacitor techniques [32,33], which can increase circuit complexity and power consumption. Alternatively, one can leverage the capabilities of FDSOI technology. Figure 1 depicts the structural diagram of FDSOI devices. FDSOI technology adopts a thin buried oxide (BOX) insulating layer and shallow trench isolation to enhance electrical isolation between the thin and excellent uniformity channel and the substrate; this significantly mitigates bulk effects such as source/drain leakage, latch-up, parasitic capacitance of the source/drain junction, and substrate noise coupling. It is essential to stress that no latch-up effect occurs. The BOX layer structure of FDSOI devices enables the silicon layer to be fully depleted of charge carriers, providing better control over the threshold voltage and reducing leakage current, requiring less doping. The lower doping levels result in decreased threshold voltage variance and device mismatch in analog neuron circuits. In addition, the introduction of a second gate terminal allows improved channel control and reduced junction capacitance, referred to as “body” or “back-gate”. The back-gate can be biased forward or in reverse to optimize transistor performance in low leakage or high efficiency modes. We analyzed a 22 nm FDSOI PDK process that features two primary types of transistors with varying gate oxides—thin and thick. This affords designers a range of transistor models with differing threshold voltages and, thus, varied levels of leakage currents. In subthreshold neuron circuit designs, employing non-minimum size devices (i.e., large transistors) is often a necessary measure. For these cases, thick gate oxide devices need to be used to avoid gate leakage due to tunneling effects. Moreover, they can provide Low-Threshold-Voltage (LVT) and are typically flip-well devices with the same doping type for their well and channel. The threshold-voltage (V_th) and drain current (I_d) can be further adjusted with back-gate biasing. For the neuron design, we utilized 1.2 V I/O thick gate oxide Low Threshold Transistors (LVT) with a V_dd of 0.4 V.

Figure 2 reveals simulated subthreshold I_dV_g characteristics of NMOS/PMOS devices with varying channel lengths. |V_ds| is fixed at 400 mV and the device’s width is 1 µm. The drain current I_d, ranging from picoamps to nanoamps, exhibits linear dependence on V_g. Figure 3 shows the I_dV_g characteristics of n-type and p-type FDSOI devices with W = 400 nm, L = 28 nm, and V_ds = 400 mV, at different back-gate voltages V_bs of −400 mV, 0 V, and 400 mV. Seen here, higher values of V_bs result in smaller threshold voltage and greater drain current for NMOS devices, whereas the opposite effect occurs for PMOS.

2.2. Proposed Method

The basic structure of the LIF neuron model is illustrated in Figure 4. Previous neuron spikes are received at the synapse and converted into a current that is multiplied by the synaptic intrinsic weight. This current is then integrated into the membrane potential capacitor C_mem. When the membrane potential exceeds the action potential of the neuron, a spike output is generated and transmitted to the subsequent neuron [13]. Following the spike, the neuron resets the membrane potential using a Low Pass Filter (LPF) circuit and waits for the next stimulus. Leaky path models the leakage conductance of the LIF neuron and provides a constant leakage current path I_leak. In addition, the presence of the leakage current path causes the membrane potential to decay over time if there is no input stimulus from the pre-neuron for an extended period.

The firing dynamics of LIF neurons are governed by Equations (1) and (2) [13]:

$$C_{mem}\frac{d{V}_{mem}\left(t\right)}{dt}=I\left(t\right)-\frac{V_{mem}\left(t\right)}{R}$$

(1)

$$\mathrm{if} V_{mem}\left(t\right)>V_{thr} \mathrm{then} V_{mem}\left(t+\Delta t\right)>V_{RET}$$

(2)

where V_mem(t) represents membrane potential, C_mem is membrane capacitance, I(t) stands for the input current, R is the total leakage resistance of LIF neuron, V_thr is the threshold voltage, and V_RET denotes the reset potential.

If a variable I_var represents the current change in I_mem and is generated due to mismatch issues in subthreshold region, the firing dynamics of the LIF neuron is primarily regulated by the current I_leak, which is determined by the resistance R_leak, while the reset current I_ret is controlled by the output spike V_spk. Naturally, the firing rate of the neuron can deviate from its desired set value due to mismatch issues. These issues may result in a decrease in firing rate, likely caused by the number of leakage paths on the membrane capacitor of the neuron exceeding the number of charging paths. Additionally, if the external input current to the neuron remains constant, an increase in the bias voltage (e.g., V_thr) may also lead to a decrease in firing frequency. Consequently, maintaining a balance in the charging and discharging of neurons in the membrane capacitor to match the firing dynamics of neurons is critical for solving mismatch issues, particularly in compensating for leakage current paths.

$$C_{mem}\frac{d{V}_{mem}\left(t\right)}{dt}=I_{in}-I_{leak}-I_{ret}\pm I_{var}$$

(3)

While the leakage current cannot be decreased, the circuit can compensate for it by increasing the charging current of the membrane capacitor. A simplified diagram of the method is shown in Figure 5. If V_RFB is at a low level, the analog switches are activated, and the back-gate bias of PMOS (M₁, M₂, M₄) is set to a lower voltage to achieve a higher charge current (I_mem). Otherwise, the back-gate bias must be connected to V_dd without the assistance of the tolerant circuit. The back-gate bias effect can adjust the transconductance of PMOS transistors. By isolating PMOS transistors in a well, the current in the path can be tuned to compensate for mismatches by varying the well voltage, as previously mentioned (refer to Figure 3). Moreover, we adjusted the back gate voltage of critical NMOS transistors using the unique advantages of the 22 nm FDSOI process. The aim was to prevent excessive compensation current from affecting the circuit, which greatly enhances the potential to regulate complex biologically realistic behaviors of neurons.

2.3. Proposed Subthreshold Neuron Circuit

The benefits of utilizing FDSOI technology in neuron circuit design, coupled with feasible design methods, have been previously explained. To simulate real environmental signals in SNN architectures, it is crucial to ensure that the neurons’ and synapses’ time constants reflect biologically plausible dynamics in circuit design. As described in [24], neuron conductance dynamics can be modeled by using first-order differential equations, which can be implemented via current-mode subthreshold circuits. Among such circuits, the differential pair integrator (DPI) provides a compact and low-power solution [24]. Unlike other approaches, such as log-domain low-pass filters and tau-cells [24], DPI circuit avoids transistors with bulk-source connections, resulting in a smaller silicon area and lower power consumption. Furthermore, DPI circuit is unaffected by any mismatches between its current sources. Thus, we employed a DPI circuit as an input current integrator. We proposed a wide range of spiking behavior LIF neuron circuits with adjustable spike frequency, which aim to provide optimal support for SNNs in terms of achieving remarkable learning and pulse coding performance [34]. The following text clearly discusses the design parameters, functions, and low-power design concept of the circuit.

The proposed neuron was designed with 22 nm FDSOI technology and the topology is shown in Figure 6. The supply voltage V_dd was set to 0.4 V for the subthreshold operation. The capacitances were realized using Alternate Polarity Metal on Metal (APMOM) structures. The capacitance density is dependent on the number and value of the metal layers employed: higher capacitances can be achieved with more metal layers. However, these devices also exhibit parasitic resistance effects that scale with area, imposing limitations on the maximum achievable capacitance. To account for parasitic effects and area cost, the capacitances were implemented using three metal layers in this design. The corresponding capacitance values and sizes are shown in

Table 1. Capacitance values and sizes used in the neuron design.

	Cmem	Cref	Cadp
Value	383 fF	227 fF	639 fF
Width	9 µm	9 µm	15.5 µm
Length	12 µm	7 µm	18 µm

.

The circuit schematic can be subdivided into different functional blocks:

DPI (M_L1–M_L5): Integrate the input current onto the membrane capacitance (C_mem), model the neuron’s leak conductance, and provide exponential subthreshold dynamics in response to constant input currents;

Na+ (M_N1–M_N6): Generate two current-based positive feedback branches, model the neuron’s sodium (Na⁺) activation and inactivation channels, and trigger a spike;

K+ (M_K1–M_K3): Control the neuron spike reset with refractory period functionality and model the neuron’s potassium (K⁺) channels;

AHP (M_A1–M_A2): Negative feedback LPF (Low Pass Filter) circuit models calcium-dependent after-hyperpolarization potassium currents, observed in real neurons, to produce the spike-frequency adaptation mechanism.

As previously mentioned, the transistors of circuits are designed to operate in subthreshold regions. The external input current, I_syn, acts as an excitatory synaptic current in the neuron. Transistors M_L1–M_L5 configure a DPI circuit operating as current-mode integrator to integrate the input current and generate pulse current onto the membrane capacitance, C_mem, while the gain in the DPI circuit is adjusted by I_gain. All transistors in the DPI module were configured with identical operating parameters. The bias voltage, V_leak, was set to a minimal value, resulting in a diminutive I_leak, to ensure that I_syn $\gg$ I_leak, thus generating exponential characteristics. This also prevents excessive current from leaking out of the circuit through M_L5, thereby greatly reducing the dynamic power consumption of circuit. Moreover, the neuronal membrane voltage is increased as the DPI circuit integrates more input current onto C_mem. Once the membrane voltage V_mem exceeded the open threshold of transistor M_N5 with an adjustable threshold controlled by the back-gate voltage V_thrb, a positive feedback current I_fb was activated to increase V_mem more sharply through M_N1. When V_mem increased enough to make the transistor M_N5 switch, the voltage V_f was brought to ground and a spike was generated by the inverter (M_N4, M_N6). Transistors M_N2, M_N5, M_N4, and M_N6 comprised two cascaded inverters, which constituted a simple amplifier topology for controlling spike generation of the neuron. These inverters are sensitive to supply variations. However, the impact of supply sensitivity was not significant in this circuit, due to the use of LVT (Low-Threshold-Voltage) transistors that enhanced the robustness of cascaded inverters. The input voltage swing for the two cascaded inverters was restricted, which also helped to reduce the sensitivity of the neuron circuit to supply variations. Considering the variability in the inverter transistors’ threshold voltage with the process, we chose to scale up the size of certain transistors, such as M_N4, M_N5, and M_N6, to mitigate the inverter threshold voltage fluctuations. Back-gate biasing is also a reliable tackle for adjusting the transistor threshold voltage (e.g., M_N5), to compensate for and mitigate inverter threshold voltage variations due to the processing technique.

As the spike was generated, a current I_rep with amplitude set by V_rep was fed into the capacitor C_ref, causing an increase in the voltage V_ret. When V_ret became high enough, the current I_ret exceeded I_fb, so the membrane capacitor C_mem was discharged back to the ground through the reset transistor M_K3. Following this, the V_f rose rapidly to V_dd, while the voltage V_spk was slowly reset to zero at a rate controlled by the bias voltage V_ref and the size of C_ref. Here, to ensure that the capacitor C_mem was fully discharged during the reset phase, the size of M_K3 was selected to be large enough. By employing V_ref in M_K2, C_ref discharged slowly, allowing the current I_ret to remain sufficiently high, preventing the input current from charging C_mem. This effectively established the refractory period. We adjusted the back-gate voltage V_refb of M_K2 to further change the neuronal refractory period and achieve varied firing rates. Once the refractory period was over, the neuron started operation again if there was any remaining input current.

During the spike emission period (while V_f is low), a current I_ahp with amplitude set by V_pfb and a time constant set by V_ahp were sourced into the adaptation DPI. With each spike, the voltage on capacitor C_adp accumulated step-by-step, causing the adaptive current I_ahp to continuously increase following the same first order dynamics as I_in. Due to the negative-feedback property of I_ahp, the neuron’s initial output firing rate to a step input current was directly proportional to the input, but decreased gradually until reaching an equilibrium. This behavior accurately replicates the observed spike-frequency adaptation in real neurons. In addition, by adjusting the back-gate voltage V_pfb of M_N3, the current I_pf could be fine-tuned to allow variable step-by-step accumulation of voltage amplitude on capacitor C_adp, leading to a wide range of stable adaptive firing frequencies for the neuron. The back-gate voltage V_adpb was utilized to set the gain negative feedback low-pass filter, while the frequency of spike adaptation could be changed by varying the ratio between the currents I_pf and I_adp. By choosing appropriate values for the bias voltages V_rep, V_ref, V_pfb, and V_adp, a wide range of spiking patterns could be achieved.

After analyzing the neuron operations stated above, the subthreshold performance of this neuron can be derived as follows. Here, we neglect the reset current I_ret and adaptation current I_ahp, as they become non-negligible only after the first spike. Applying Kirchhoff’s current law on the membrane V_mem node leads to Equation (4):

$$C_{mem}\frac{d}{dt}{V}_{mem}=I_{in}-I_{leak}+I_{fb}$$

(4)

The gain in the DPI circuit can be fine-tuned using an additional control parameter, I_gain. By applying the trans-linear principle across the DPI circuit in the subthreshold region, $I_{gain}\cdot I_{ML3}=I_{in}\cdot I_{mem}$. Assuming uniform transistor parameters and operation in the subthreshold regime and in saturation [24], the circuit’s node currents are expressed as follows:

$$\begin{gathered} I_{syn}=I_{ML3}+I_{in} I_{in}=I_{leak}+I_C \\ {I}_C=C_{mem}\frac{d}{dt}{V}_{mem} I_{mem}=I_0{e}^{\frac{\kappa V_{mem}}{U_T}} \end{gathered}$$

(5)

where I₀ represents the dark current of the transistor, U_T represents the thermal voltage, and κ represents the subthreshold slope factor [24]. Specifically, based on the conversion properties of the exponential function, I_C can be expressed as shown:

$$I_C=C_{mem}\frac{U_T}{\kappa I_{mem}}\frac{d}{dt}{I}_{mem}$$

(6)

Considering the drain current relationship in the weak inversion region (or subthreshold) and assuming the subthreshold slope coefficients, κ for both n and p-FETs are equal. Based on Equations (4)–(6), the dynamic characteristics of the neuron can be expressed as a first-order nonlinear differential equation:

$${\tau }_m\frac{d}{dt}{I}_{mem}+I_{mem}\left(1-\frac{I_{fb}}{I_{leak}}\right)=I_{syn}\left(\frac{I_{mem}}{I_{leak}}\right)/\left(1+\frac{I_{mem}}{I_{gain}}\right)$$

(7)

where ${\tau }_m=U_T{C}_{mem}/\kappa I_{leak}$, and $I_{gain}=I_{0}exp\left(\kappa V_{gain}/U_T\right)$ is the node current of V_gain. At the beginning of an action potential, while the membrane capacitor charges, the DPI circuit exerts dominance over the positive feedback branch and allow us to neglect the current I_fb. Moreover, the right-hand side of Equation (7) can be simplified to $I_{syn}\cdot I_{gain}/I_{leak}$, if I_mem $\gg$ I_gain, and our design takes it into consideration. In these conditions Equation (7) can be rewritten as a first-order linear differential Equation (8):

$${\tau }_m\frac{d}{dt}{I}_{mem}+I_{mem}=I_{syn}\frac{I_{gain}}{I_{leak}}$$

(8)

Based on the analysis provided above, for small membrane V_mem values and sufficiently large membrane I_mem values (where I_mem $\gg$ I_gain), the subthreshold neuron displays a classical RC-filter behavior. As has been shown, it also represents a Leaky Integrate-and-Fire conductance-based neuron model.

The layout of the neural circuit is shown in Figure 7. Total area is 484 μm², considering all transistors and capacitors, and a two-stage inverter is included for spike buffering. The triple-well structure, utilizing PMOS in NWELL and NMOS in PWELL, was used for all transistors. This structure allowed us to isolate the NMOS device from the global substrate through an NWELL ring surrounding the device and enabled application of an independent bias to the back-gate node [35]. We utilized dummy transistors and multi-finger transistors for handling layout dependent effects, such as Length of Diffusion and Well Proximity, and a cross-coupled layout design was used to minimize mismatch.

3. Results

3.1. Neuron Circuit Post-Layout Simulation

Figure 8 shows LIF neural post-layout simulation results, exemplifying biologically plausible behaviors. It highlights distinct spiking patterns for a constant dc-current input, in contrast to the neuronal behavior described in [36]. In Figure 8, the input current for (a) to (e) was maintained at a constant value of 400 pA while, for (f), it varied linearly from 0 to 400 pA. The voltage values used to obtain spiking patterns are given in the figure description.

For a regular spiking (RS) pattern, the AHP module is currently closed and does not generate any leakage current for C_mem. The frequency adaptation (FA) spiking pattern allows C_adp to charge, causing the voltage V_ahp to settle at a fixed value after a few spikes, resulting in slow-rate tonic spiking. The fast spiking (FS) pattern found in cortical layers is characterized by high-frequency periodic trains of spikes without adaptation, achieved by not allowing the membrane potential to reset all the way to the ground. Modulating the control voltage of K⁺ and AHP modules can manipulate tonic spiking (TS) and chattering (CH) spiking patterns. A tonic bursting neuron generates a burst of spikes at the beginning of a constant input current, followed by tonic spiking. A chattering neuron generates repetitive bursts of high-rate spikes in response to a constant input current. The neocortical RS excitatory neurons exhibit tonic spiking frequency that is proportional to the intensity of the input, ranging from 2 Hz to 200 Hz, or even higher. The property of firing low-frequency spikes at weak inputs is termed as Class 1 excitability [37]. These neurons can effectively represent the input strength through their firing rate, as depicted in Figure 8f.

The neuron biologically plausible behavior can be further verified. Figure 9 illustrates the behavior of neuronal refractory periods. The membrane current, I_mem, was recorded at various I_ref values by adjusting V_ref in the K⁺ block of Figure 6. As I_ref increases, the refractory period of the neuron is shorter and, hence, results in an increase in its maximum firing rate. This enables frequency modulation over a wide range in the neuron and exhibits significant potential for larger SNN systems [14,15,16,17]. The firing rate of neurons is the number of action potentials, or spikes, emitted over a defined time period, quantified in units of hertz (Hz) or spikes per second.

As previously stated, regulating the refractory period can shift the firing of neurons between high and low frequency modes. Due to the adjustable gate voltage feature of FDSOI devices, it is able to independently adjust the bias of the transistor M_K2′s front-gate V_ref and back-gate V_refb. Figure 10 illustrates the F–I curve of the neuron at varying bias levels of V_ref and V_refb. Specifically, Figure 10a,b show the F–I curves in low-frequency and high-frequency modes,. When the back gate voltage, V_refb, is set to ground, the resulting lower current, I_ref, results in a longer refractory period and low frequency operation with the input current, until it reaches saturation at a level determined by the refractory period setting. Moreover, as V_ref increases, the refractory period shortens, thereby increasing the neuron’s maximum firing rate. In addition, maintaining a proper fixed value for V_ref and increasing the back-gate voltage V_refb can lead to a shorter refractory period. As depicted in Figure 10b, as V_refb increases, the firing rate of neurons also increases, operating at kilohertz levels. The maximum spiking firing rate is directly proportional to the input current and saturates only for extremely high input current values. When V_refb reaches 300 mV, the refractory period is brief (a few hundred μs), and the maximum spike firing rate does not saturate, even for high input currents. This enables neurons to operate at higher frequencies as input current increases.

Figure 11 illustrates the spike frequency adaptation behavior. This was obtained by applying an input current step with an amplitude of 300 pA and a gain current (I_gain) of 80 pA, with V_thrb = 0 V, V_leak = 60 mV, V_rep = 100 mV, V_ref = 80 mV, V_pfb = −200 mV, V_adp = 25 mV, and V_adpb = 0 V. As each spike is generated, the adaptive after-hyperpolarization potential (V_ahp) rises, leading to a corresponding increase in the adaptive current (I_ahp) by M_A2, which reduces the charging current of the membrane capacitance (C_mem). Once V_ahp reaches a stable state, the spiking firing of the neuron remains constant, albeit at a lower rate compared to the initial firing. This process reduces the firing rate to lower energy consumption as a form of frequency adaptation.

In a large-scale spiking neural network, neurons are required to process information from multiple network layers. It is crucial for neurons to adapt the spiking information of varying frequencies at different network layers. Recent studies on mixed-signal neuromorphic systems [18,38] have suggested the use of wide-band adaptive neurons with time constants that are well-suited for signal processing. This neuron can also effectively achieve adaptive behavior at different frequencies, as illustrated in Figure 12. Adaptive frequencies can vary by adjusting the proportion between currents I_pf and I_adp. As can be seen, as the ratio of I_pf to I_adp increases, the adaptive spiking frequency also rises. Hence, the neuron is adept at implementing complex neuromorphic systems.

3.2. Energy Per Spike

It has been demonstrated that the proposed neural circuit exhibits sophisticated biologically resembling behavior. In order to evaluate its energy efficiency, energy consumption per spike is a significant figure of merit (FoM), and the FoM has been utilized in several studies to effectively assess the energy efficiency of neuron circuits [39,40,41,42]. Energy per spike can be calculated by dividing the average power consumption P_ave by the maximum spiking frequency Freq. Averaged power is given by Equation (9):

$$P_{ave}=\frac{Freq}{N}{\displaystyle {\int }_0^{T_{sim}}{I}_{dd}}\left(t\right)\cdot V_{dd}dt$$

(9)

where T_sim is the simulation time, I_dd (t) represents the total (static and dynamic) current flowing through the supply voltage V_dd, and N indicates the number of spikes in the simulation time T_sim. The energy per spike, denoted by E_S, is extracted from Equation (9) and expressed as follows:

$$E_S=\frac{P_{ave}}{Freq}=\frac{1}{N}{\displaystyle {\int }_0^{T_{sim}}{I}_{dd}\left(t\right)}\cdot V_{dd}dt$$

(10)

Figure 13 demonstrates the energy per spike versus firing rate curve of the neuron. It is apparent that the low-frequency mode consumes more energy than the high-frequency mode. Energy consumption for lower frequencies is around tens of pJ, decreasing to hundreds of fJ for higher frequencies. This is because, at lower frequencies, the inverters operate in high-gain regions where both transistors conduct for longer periods, and this occurs due to slower charging of V_mem compared to higher frequencies. Furthermore, static power consumption when operating at 30 Hz represents about 11% of total power consumption, while, at higher frequencies (i.e., at 1 kHz), this percentage drops to 5%.

Table 2. The proposed circuit in comparison with other works.

Work	[32]	[41]	[42]	This Work
Techn.	28 nm CMOS	28 nm FDSOI	22 nm FDSOI	22 nm FDSOI
Vdd	0.7–1 V	1 V	0.8 V	0.4 V
Area	-	20 μm2	900 μm2	484 μm2
Results	Exp	Sim	Sim	Sim
En./spike	2.3nJ@1kHz	50pJ@30Hz	14pJ@30Hz	326fJ@1kHz 8.3pJ@30Hz

presents a comparison of the energy per spike of our circuit with previously published state-of-the-art neuron circuits. The simulation results of our neuron circuit are compared with both simulation data [41,42] and experimental data [32].

Compared to a similar 28 nm CMOS circuit [32], our design exhibits superior energy efficiency with energy consumption per spike at approximately 326 fJ at 1 kHz, which is three orders of magnitude lower than the firing rate of 1 kHz observed in the reference neuron. The neuron developed in this study consumes less energy per spike than a comparable circuit [41] using similar technology (28 nm FDSOI) at a biologically plausible spiking rate (30 Hz), and the circuits utilized in [41] and our study share comparable C_mem, which we can regard as the dominant capacitance impacting power consumption. Thus, based on the scaling factor, the circuit in [41] is expected to have comparable energy per spike when scaled down to the 22 nm process. Our circuit has a larger area than the circuit in [41], as the circuit includes an adaptive capacitor (C_adp) for enabling complex neural behaviors and a wide range of adjustable frequencies. Additionally, the capacitance density of 22 nm FDSOI devices exceeds that of 28 nm FDSOI devices with equivalent value, leading to a high capacitance utilization in the circuit area. Furthermore, the circuits proposed in both [42] and our study used the same technology (22 nm FDSOI). It can be noted that our circuit design offers greater efficiency in terms of area and energy consumption.

3.3. Monte Carlo Analysis

The proposed circuit is adaptable and can be flexibly controlled through parameter adjustments in various situations. However, process variability and mismatch cause device conducting currents that deviate from the intended values. If the mismatch is excessive, the output of neurons in a spiking neural network will exhibit significant variability from one neuron to another. To minimize transistor mismatch effects, we selected those that operate with small currents and assigned them longer length values (e.g., L_PMOS = 28 nm, L_NMOS = 32 nm). Key transistors relevant to mismatch, such as M_A1 and M_K2, were designated even larger sizes, up to 36 nm/4 μm. To evaluate the neuron’s performance in relation to mismatches, we conducted a series of Monte Carlo simulations. The neuron circuit performed analysis with 500 runs, with a dc-current being injected into the DIP block depicted in Figure 6, while the bias currents were adjusted to obtain a firing rate of approximately 67.1 Hz.

As depicted in Figure 14, the Monte Carlo distribution results demonstrate that the average firing rate of neurons is around the expected value (≈67.1 Hz), with a standard deviation of 2.026. Consequently, the variability in the neuron circuit amounts to 3.02% (Std Dev/Mean). Our analysis revealed that the variability is modulated by Na⁺ inhibition, specifically, M_N2 and M_N5. The circuits in the DIP and K⁺ blocks (as shown in Figure 6) are also sensitive to mismatches, especially with respect to M_L1 and M_L2 for the DIP block, and M_K2 for the K⁺ block.

3.4. Process Robustness

Subthreshold neural circuits are highly sensitive to fluctuations in processing. In this FDSOI circuit design, we leveraged the advantages of back-gate voltage to regulate critical current paths and ensure robust process variation tolerance at extreme process corners, such as FF and SS.

Figure 15 illustrates the process variation for SS, TT, and FF. Specifically, the C–SS and C–FF curves were obtained by adjusting the transconductance between M_N5, M_K2, and M_A1 at the corresponding process corners for SS and FF. It is evident that optimizing the back-gate voltage of key transistors improves the circuit’s robustness, and we can conclude that C–SS exhibits a 75.6% reduction in frequency deviation compared to TT, while C–FF experiences an 80.3% reduction relative to FF. As a result, the distinctions between C–SS and TT, as well as C–FF and TT, become negligible, suggesting that the proposed neural circuit can mitigate process variances.

4. Conclusions

We proposed a new efficient analog LIF neuron circuit, operating in the subthreshold regime, with ultra-low-power consumption and wide dynamics. It was implemented using an advanced 22 nm FDSOI process that had been scaled for optimal performance. A differential pair integrator circuit generated exponential subthreshold dynamics to accurately simulate the realistic time constant of neurons and synapses. The back-gate bias of FDSOI technology enables the generation of varied neuron dynamics over a wide frequency range, including low- and high-frequency modes, as well as adaptive frequencies. Moreover, this neuron is capable of displaying complex firing behaviors, such as adaptation, chattering, and bursting. These features render the suggested circuits well-suited for neuromorphic hardware systems. Compared to similar circuits, the proposed design exhibits lower energy consumption per spike, achieving 8.3 pJ at a 30 Hz firing rate. Monte Carlo simulations were performed to analyze the sensitivity of the neuron circuit to mismatches. Results indicate that the firing rate relative error is only 3.02% (Std Dev/Mean), highlighting the Na⁺ block, DPI block, and K⁺ block as the more sensitive sub-parts of the silicon neuron circuit. Finally, due to the significant transistor’s back-gate bias, this neuron exhibits higher process robustness across varying process corners.