A Novel 4H-SiC Double Trench MOSFET with Built-In MOS Channel Diode for Improved Switching Performance

Abstract

This study proposed a novel 4H-SiC double trench metal-oxide-semiconductor field-effect-transistor (DTMCD-MOSFET) structure with a built-in MOS channel diode. Further, its characteristics were analyzed using TCAD simulation. The DTMCD-MOSFET comprised active and dummy gates that were divided horizontally; the channel diode operated through the dummy gate and the p-base and N+ source regions at the bottom of the dummy gate. Because the bult-in channel diode was positioned at the bottom, the DTMCD-MOSEFT minimized static deterioration. Despite having a 5.2% higher specific on-resistance (R_on-sp) than a double-trench MOSFET (DT-MOSFET), the DTMCD-MOSFET exhibited a significantly superior body diode and switching properties. In comparison to the DT-MOSFET, its turn-on voltage (V_F) and reverse recovery charge (Q_rr) were decreased by 27.2 and 30.2%, respectively, and the parasitic gate-drain capacitance (C_rss) was improved by 89.4%. Thus, compared with the DT-MOSFET, the total switching energy loss (E_tot) was reduced by 41.4%.

1. Introduction

Wide-bandgap materials have a higher critical electric field and higher electron velocity than silicon, making them suitable for use in high-voltage and high-speed power MOSFETs [1,2]. In particular, silicon carbide (SiC) has high thermal conductivity and can be used stably at high temperatures; thus, SiC MOSFETs have been evaluated as substitutes for Si IGBTs [3]. SiC MOSFETs primarily fall into two categories: trench-structured UMOSFETs and planar diffusion MOSFETs (DMOSFETs). By lowering the cell pitch, UMOSFETs can enhance the cell density per unit area, while decreasing the JFET area through the gate trench. However, their trench structure renders them susceptible to electric fields [4]. A double-trench MOSFET (DT-MOSFET) and a gate P+ shielding construction have been proposed as solutions to this issue [5,6]. The gate and source trench configuration of the DT-MOSFET facilitates the distribution of the electric field in the gate trench, and the bottom P+ shielding region (BPR) protects the gate oxide from high drain voltages. In addition, attempts have been made to reduce the switching loss of SiC power devices. The decrease in switching time has been investigated as a way to decrease switching loss. Further, a split-gate configuration has been proposed to shorten the switching times, because the gate-drain capacitance (C_gd) is correlated with the switching time [7]. This minimizes the gate-drain overlap region by separating the gate region, thereby reducing C_gd and the switching time and loss. Moreover, the introduction of BPR not only protects the gate oxide, but also reduces C_gd by preventing a coupling effect between the gate and the drain [8].

Reducing the circuit’s antiparallel diode reverse recovery charge is another method for lowering the switching loss. The reverse recovery charge is lower for the SiC Schottky barrier diode (SBD) than for the PiN diode because it functions as a unipolar device with fewer minority carriers still present in the N-drift [9]. Consequently, SiC SBDs are now frequently employed as antiparallel diodes in power circuits. Additionally, considerable research has been conducted on the built-in SBD-MOSFET, which shrinks the size of the power module system and prevents parasitic components of the inductance via the integration of an external SBD inside the MOSFET [10,11,12]. However, there is a barrier lowering owing to the image charge force in the Schottky contact, which can result in a large leakage current when the MOSFET is off due to thermionic field emissions at the lowered barrier, as well as low short-circuit withstand characteristics [13,14].

Another option for lowering the switching loss is a built-in MOS channel diode MOSFET (MCD-MOSFET), which incorporates a channel diode into the MOSFET [15,16,17]. In a typical MOSFET construction, an MCD-MOSFET comprises a source-contacted dummy gate and an active gate that contacts the gate. A channel is established in the P-base region beyond the gate oxide film when a diode turn-on voltage is applied to the dummy gate, which is in contact with the source. Consequently, electrons pass from the drain to the source, resulting in a diode current flow. MCD-MOSFETs have a higher short-circuit withstanding ability and nearly no off-state leakage current problems caused by interface characteristics compared with SBD-MOSFETs. However, when the MCD-MOSFET is in the operating state of a MOSFET rather than a diode, the channel is not activated in the P-base region next to the divided dummy gate that is in contact with the source. This increases the channel resistance and the specific on-resistance. In addition, owing to the electric field crowding effect, a strong electric field is delivered to the gate oxide edge produced by the split-gate construction, which reduces the dependability of the gate dielectric oxide [18,19,20,21].

In this study, a novel double-trench MOSFET (DTMCD-MOSFET) structure was pro-posed, and a TCAD simulator was used to analyze its electrical properties. The DTMCD-MOSFET has a source-contacted dummy gate at the bottom of the active gate, and the BPR consists of a P+ shielding region, an N+ source, and a P-base channel. The channel diode operates through the BPR part. Thus, the DTMCD-MOSFET can utilize the P-base area on both sides during the on state, and a reduction in the channel resistance is prevented. Consequently, the DTMCD-MOSFET offers the benefit of utilizing an internal channel diode to reduce the switching power losses while minimizing the deterioration of the MOSFET’s static properties.

2. Device Structures and Proposed Fabrication Procedures

2.1. Device Structures and Optimization

A standard double-trench MOSFET (DT-MOSFET) with BPR and the proposed DTMCD-MOSFET are depicted in the cross-sectional view in Figure 1 [8,22]. The suggested DTMCD-MOSFET is such that the gate is divided horizontally from the current DT-MOSFET, and the source is connected to the dummy gate at the bottom. In addition, the DTMCD-MOSFET features an N+ source and a P-base region in the bottom P+ shielding region (BPR). When a DTMCD-MOSFET is employed as a free-wheeling diode in the switching-off state, the source bias of the dummy gate increases than the drain bias, and the increased bias creates a channel in the P-base region at the BPR. Consequently, the channel diode is activated, generating a current flow from the N+ source at the BPR to the drain. Apart from a few minor differences, the device parameters of the DT-MOSFET and the DTMCD-MOSFET are basically the same. The doping concentrations of N-drift and CSL are 7 × 10¹⁵ cm⁻³ and 2 × 10¹⁵ cm⁻³, respectively. Also, the doping concentration of the P-base and P+ shielding region are 2 × 10¹⁷ cm⁻³ and 2 × 10¹⁸ cm⁻³, respectively. As for the length parameters, the gate and source trench depths of both devices are 1.5 µm, the N-drift length is 10 µm, and the cell pitch is 4.8 µm. For both devices, the active gate oxide (Tox₁) thickness is 50 nm. Only the DTMCD-MOSFET has the length parameters Tox₂, Tox₃, and L_SG; Tox₂ was set to 210 nm, Tox₃ to 10 nm, and L_SG was set to 0.4 µm. The device parameters for the DT-MOSFET and the DTMCD-MOSFET are summarized in

Table 1. Device parameters comparison.

Parameter	DT–	DTMCD–
Cell pitch [μm]	4.8	4.8
Gate trench width [μm]	1.2	1.2
Source trench width [μm]	0.6	0.6
Source trench depth [μm]	1.5	1.5
N-drift thickness [μm]	10	10
Tox1 [nm]	50	50
Tox2 [nm]	-	210
Tox3 [nm]	-	10
BPR width [μm]	1.1	1.1
BPR depth [μm]	5	5
LSG [μm]	-	0.4
N-drift doping concentration [cm−3]	7 × 1015	7 × 1015
CSL doping concentration [cm−3]	2 × 1016	2 × 1016
P+ doping concentration [cm−3]	2 × 1018	2 × 1018
P-base doping concentration [cm−3]	2 × 1017	2 × 1017
N+ doping concentration [cm−3]	1 × 1019	1 × 1019

.

According to the split dummy gate length L_SG, Figure 2 depicts the DTMCD-MOSFET’s optimization features. The active gate length decreased as the L_SG increased, which resulted in a reduction in the gate-drain coupling effect and a consequent decrease in the parasitic gate-drain capacitance (C_gd). However, because of the shorter active gate length, the accumulation layer declined, increasing the specific on-resistance (R_on-sp) [23]. In this case, the high-frequency figure-of-merit (H-FOM; H-FOM = R_on-sp × C_gd) can be used to determine the optimal point [24]. Owing to the possibility of reducing the conduction and switching losses with a decrease in the R_on-sp and C_gd, the point with the smallest H-FOM value is the optimal device, and it was obtained when L_SG = 0.4 µm.

In contrast to the DT-MOSFET, the DTMCD-MOSFET undergoes two thermal oxidation stages. In the gate trench region, the first oxidation yielded 10 nm Tox₁ and 10 nm Tox₃, whereas the second oxidation, which proceeded after dummy gate deposition, yielded the remaining Tox₁ and Tox₂. Owing to the fact that the oxidation rate of polysilicon is higher than that of silicon carbide, Tox₂ grew thicker than Tox₁ [25,26,27]. Wet thermal oxidation with H₂O was conducted using Sentaurus process simulation at 1215 °C, resulting in the formation of 210 nm of Tox₂ and 50 nm of Tox₁. The following subsection provides additional information on the proposed fabrication process sequence for the DTMCD-MOSFET.

2.2. Proposed Fabrication Procedures

Figure 3 shows the proposed fabrication process flowchart of the DTMCD-MOSFET. First, the N-drift and current spread layer (CSL) regions were formed through a 4° off-axis epitaxial growth (Figure 3a) [28]. Ion implantation was then used to create the BPR region, which consists of the P+ shielding, P-base, and N+ source regions of the channel diode gate (Figure 3b) [29]. In Figure 3c, the remaining CSL and P-base regions were created through epitaxial growth, and N+ source regions were subsequently created through ion implantation [30]. The source trench and side P+ shielding shown in Figure 3d were created using RIE-ICP etching and tilt-ion implantation [31]. Subsequently, the source region was filled using oxide deposition, as shown in Figure 3e, and the gate trench was created using etching, as shown in Figure 3f, followed by wet thermal oxidation to form Tox₃ [32]. In addition, N+-doped polysilicon was deposited and etched to create the dummy gate shown in Figure 3g, and wet thermal oxidation was used once again to create Tox₁ and Tox₂ in Figure 3h [33,34,35]. As shown in Figure 3i, an active gate was formed through polysilicon deposition and etch-back processes, followed by oxide deposition [36]. Finally, the oxide was etched to form an ILD oxide, and the deposition of the source metal completed the discrete MCD-MOSFET device process (Figure 3j).

3. Simulation Results and Discussions

In this section, we present and analyze the simulation results for the electrical characteristics of the proposed and compared devices. The simulation was performed using the Sentaurus TCAD tool from Synopsys, and Poisson’s equations and the electron/hole continuity equations were solved in a two-dimensional (2D) MOSFET structure [37]. For the simulation conditions, physical models, such as the mobility, recombination, generation, and avalanche models, and the density of the interface states at the SiC/SiO₂ interface, were performed under the same conditions as in our previous study [18]. Through simulations, the static performance of the MOSFETs in their on and off states, the body diode properties of the MOSFETs, and their dynamic performance, including their parasitic capacitance and switching characteristics, were compared. Furthermore, the reverse recovery, capacitance, and switching characteristics were simulated using the circuit configuration of the mixed-mode simulation.

3.1. Static Performances

Figure 4 depicts the drain current characteristics versus the drain voltage of the DT-MOSFET and DTMCD-MOSFET properties in the on state. Because of the reduced accumulation layer caused by the split-gate construction, the R_on-sp of the DTMCD-MOSFET was slightly higher than that of the DT-MOSFET, although there were no discernible differences between the two devices. Figure 5a,b show the current density distribution of the two different-structured DT-MOSFETs with integrated channel diodes in the on state. The proposed DTMCD-MOSFET with the gates separated horizontally is shown in Figure 5a, and a DTMCD-MOSFET with the gates divided vertically is shown in Figure 5b. A channel was not formed in the right P-base region of Figure 5b because the divided right dummy gate was connected to the source. Consequently, no current flowed at the right side P-base region, thereby increasing the channel resistance and R_on-sp. In contrast, in the DTMCD-MOSFET in Figure 5a, the channel formed in both the left and right P-base regions, resulting in a current flow through it. Figure 6 shows the drain current characteristics of both MCD-MOSFETs in the on state. It is clear that the proposed MCD-MOSFET has a 38.6% smaller R_on-sp than that of an MCD-MOSFET with a single operating channel.

The drain current characteristics of the DT-MOSEFT and DTMCD-MOSFET in the off state are shown in Figure 7. Impact ionization caused an avalanche breakdown in both the devices at nearly the same voltage. The electric field distributions of the DT-MOSFET and DTMCD-MOSFET in the off state are shown in the cross-sectional view in Figure 8. The major element that impairs the reliability of the oxide film in the on or off state is leakage current resulting from Fowler Nordheim (FN) tunneling at the dielectric. The FN tunneling current is defined as:

$$J_{F-N}=A{E}^{2}exp\left(-\frac{B}{E}\right)$$

(1)

where J_F−N is F − N tunneling current, E is electric field at the gate dielectric, and A and B are constants dependent on the junction’s band offset, which is based on the barrier height between the dielectric and the semiconductor [20]. Since the conduction band offset of 4H-SiC/SiO₂ (~2.7 eV) is smaller than that of Si/SiO₂ (~3.2 eV), in order to avoid leakage current caused by FN tunneling at the gate oxide, the maximum electric field of the gate dielectric should be lower than 2–3 MV/cm [38]. It is evident from both instruments that the maximum electric field of the oxide film does not exceed 2 MV/cm. Moreover, the thin gate oxide of the DTMCD-MOSFET was efficiently shielded by the gate’s P+ shielding region, which prevented the gate oxide reliability issue.

3.2. Body Diode Characteristics

The third quadrant properties of the DT-MOSFET and DTMCD-MOSFET are shown in Figure 9. When the voltage drop between the source and drain of the DT-MOSFET is higher than the knee voltage, the current can flow through the forward PN junction, which is referred to as a PiN body diode [39]. The diode turn-on voltage (V_F) is based on the voltage at I_SD = 80 A, and the V_F of the DT-MOSFET is approximately 2.68 V. However, for a DTMCD-MOSFET, the V_F is determined by the threshold voltage on the dummy gate. When the V_SD of the dummy gate is above the threshold voltage, a channel forms at the P base of the BPR region, allowing the diode current to flow from the source to the drain, and the channel diode operates. The built-in channel diode in a DTMCD-MOSFET, however, has a lower V_F of 1.95 V than that of DT-MOSFET; thus, it is turned on before the PiN diode. Consequently, the operation of the PiN diode of the DTMCD-MOSFET was suppressed, and, since the channel diode had a lower V_F, the DTMCD-MOSFET can reduce diode conduction losses compared to the DT-MOSFET.

Figure 10a,b depict the body diode reverse recovery characteristics of the DT-MOSFET and DTMCD-MOSFET according to the L_C value, and Figure 10c illustrates a circuit diagram for the double pulsed test (DPT) that was utilized to simulate the switching and reverse recovery characteristics. The reverse recovery charge (Q_rr) is defined as:

$$Q_{rr}={{\displaystyle \int }}_{t1}^{t2} I_d\left(t\right)dt= Q_{bip}+ Q_{oss}$$

(2)

where Q_bip is the bipolar stored charge produced when the remaining minority carriers in the drift region are swept out by recombination during the diode turn-off state, Q_oss is the capacitance charge produced by the charging displacement current of the output capacitance (C_oss), t1 marks the first time that the reverse recovery current drops to zero, and t2 marks the point at which V_SD reaches 2% of V_DD [40,41,42].

Since the DT-MOSFET uses a PiN body diode as the free-wheeling diode (FWD), both electrons and holes are involved in the current flow. When the diode turns off, due to the requirement for complete recombination of the considerable number of minority carriers still present in the drift region, Q_bip is increased [43]. The DTMCD-MOSFET, on the other hand, uses a built-in channel diode as the FWD and has little Q_bip since the diode current flow only involves electrons traveling from the drain to the source via the channel. When more diode current flows as the L_C value decreases, this difference becomes even more obvious. For DT-MOSFET, Q_rr rises as the diode current increases, because more holes remain in the drift region. For the DTMCD-MOSFET, however, there is only a transient caused by Q_oss regardless of the amount of the diode current, and the Q_rr value is not much of a difference, since there is no hole that influences reverse recovery in this device. The comparison of the reverse recovery characteristics of the DT-MOSFET and MCD-MOSFET is summarized in

Table 2. Reverse recovery charge according to L_C value.

Parameter	DT–	DTMCD–
Qrr (@LC = 60 µH) [µC·cm−2]	2.33	1.62
Qrr (@LC = 30 µH) [µC·cm−2]	3.17	1.47
Qrr (@LC = 20 µH) [µC·cm−2]	3.79	1.51
Qrr (@LC = 12 µH) [µC·cm−2]	4.78	1.4

.

3.3. Dynamic Performances

The characteristics of a DT-MOSFET and a DTMCD-MOSFET’s parasitic capacitance are shown in Figure 11, which includes C_iss (C_gs + C_gd), C_rss (C_gd), and C_oss (C_ds + C_gd) [44]. A gate voltage of 0 V and a small AC signal of 1 MHz were used in the mixed-mode simulation. Since the dummy gate of the DTMCD-MOSFET is connected with the source, the drain-source coupling effect increased, which in turn enhanced C_ds. The increased source area does, however, result in a shorter gate length, since there is less overlap between the gate and the drain, which lessens the gate-drain coupling effect. DTMCD-MOSFETs therefore have lower C_rss and C_iss than DT-MOSFETs, and C_oss also has comparable values as a result of the lower C_rss. Because the dummy gate of the DTMCD-MOSFET is in source contact, which caused the C_DS to be slightly higher than that of the DT-MOSFET, C_oss is almost the same for the two devices as C_rss decreases. Compared to the DT-MOSFET, C_rss, which affects the switching time, decreased because the overlap area of the gate and drain was reduced. The C_rss of the DTMCD-MOSFET was 2.1 pF/cm², which is a drop of approximately 89.4% from that of the DT MOSFET (19.9 pF/cm²).

Figure 12 depicts the transient response of the gate input voltage, drain voltage, and drain current during the switching on/off operation of the DT-MOSFET and DTMCD-MOSFET. The DPT used for the switching simulation is shown in Figure 8c, and the L_C value was set to 60 µH. The switching-on time (T_on) was calculated as the total time required for V_GS to reach from 10% of V_IN to 90% of V_DD (T_d-on), and the time required for V_DS to reach from 90 to 10% of V_DD (T_r) [45]. The switching-off time (T_off) was also calculated as the total time required for V_GS to reach from 90% of V_IN to 10% of V_DD (T_d-off), and the time required for V_DS to reach from 10 to 90% of V_DD (T_f). In the switching behavior of a MOSFET, the gate-source voltage to drain-source voltage switching ratio over time is defined as:

$$V_{GS}=R_G{C}_{rss}\frac{d{V}_{DS}}{dt}\left(1-e^{\frac{-t}{R_G{C}_{iss}}}\right)$$

(3)

where the switching time and drain-source voltage change rate are highly dependent on C_iss and C_rss components [46]. As the C_rss and C_iss values lower, the parasitic capacitance components charge or discharge more quickly in the switching operation, which increases the V_DS change rate and decreases the switching time.

The rate of change of VDS in DTMCD-MOSFETs is higher due to their lower C_rss and C_iss values compared to the DT-MOSFET, which leads to faster switching times. When compared to the DT-MOSFET, the DTMCD-MOSFET has 55.1% and 31.4% better switching-off and -on times, respectively. The DTMCD-MOSFET exhibited faster switching times than the DT-MOSFET because of its lower C_rss.

The switching power dissipations of the DT-MOSFET and the DTMCD-MOSFET are shown in Figure 13. The drain voltage and current in Figure 12 were multiplied to estimate the power dissipation. Calculations for the switching-off loss (E_off) and switching-on loss (E_on) are as follows:

$$E_{off}={{\displaystyle \int }}_{ T_1 \left(90\% of V_{GS}\right)}^{T_1+T_{off} } V_{DS}\left(t\right) I_{DS}\left(t\right)dt$$

(4)

$$E_{off}={{\displaystyle \int }}_{ T_2 \left(10\% of V_{GS}\right)}^{T_2+T_{on} } V_{DS}\left(t\right) I_{DS}\left(t\right)dt$$

(5)

where it is estimated by integrating the power dissipation curves over the switching time. DTMCD’s E_off and E_on can be reduced owing to faster switching times compared to the DT-MOSFET. Furthermore, when the MOSFET is turned on, the load current that was flowing through the free-wheeling body diode and the load inductor during off time transforms into a reverse recovery current and flows to the MOSFET, creating a switching overshoot in the drain current. In comparison to the DT-MOSFET, the DTMCD-MOSFET feature a lower reverse recovery current and charge, which leads to less drain overshoot and thus a lower E_on.

The E_off and E_on of the DTMCD-MOSFET were reduced by 57.1% and 33.5%, respectively, compared to those of the DT-MOSFET, owing to the fast switching time and low Q_rr. Consequently, the total switching loss (E_tot; E_tot = E_off + E_on) was reduced by 41.4%. A comparison of the static and dynamic characteristics of the DT-MOSFET and the DTMCD-MOSFET is presented in

Table 3. Static and dynamic characteristics of devices.

Parameter	DT–	DTMCD–
BV [V]	2137	2139
Ron-sp [mΩ·cm2]	2.48	2.61
EMOX (@VDS = 1.2 kV) [MV/cm]	1.41	1.14
VF (@ISD = 80 A·cm−2) [V]	2.68	1.95
Ciss (@VDS = 1.2 kV) [nF·cm−2]	36.3	21.1
Coss (@VDS = 1.2 kV) [pF·cm−2]	839	839
Crss (@VDS = 1.2 kV) [pF·cm−2]	19.9	2.1
H–FOM [pF·mΩ]	49.4	5.5
Ton [ns]	159	109
Toff [ns]	917	412
Eon [mJ·cm−2]	8.045	5.352
Eoff [mJ·cm−2]	4.087	1.753
Etot [mJ·cm−2]	12.132	7.105

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4. Conclusions

This study proposed a novel 4H-SiC DTMCD-MOSFET with an integrated MOS channel diode. Furthermore, a TCAD simulation is used to examine its static, dynamic, and body diode characteristics. By positioning the channel diode at the bottom of the gate, the proposed MOSFET can activate both side channels of the MOSFET in the on state, thereby minimizing the on-state current decrease caused by single-channel activation in the built-in MCD-MOSFET. Additionally, gate P+ shielding protects the thin gate oxide layer, eliminating any issues with the oxide film dependability caused by strong electric fields. Because the DTMCD-MOSFET has better V_F, Q_rr, and C_rss values than the DT-MOSFET, the E_off and E_on of the DTMCD-MOSFET were improved by 57.1 and 33.5%, respectively, whereas the E_tot was enhanced by 41.4% when compared to the DT-MOSFET. These electrical properties make the DTMCD-MOSFET structure a potential substitute for the conventional devices in high-voltage and high-frequency power circuits.