Parasitic-Aware Simulation-Based Optimization Design Tool for Current Steering VGAs

Abstract

Designing millimeter-wave variable gain amplifiers (VGAs) is very challenging owing to the parasitic effects of the interconnects of both active and passive devices. An automated parasitic-aware optimization RF design tool is proposed in this paper to address this challenge. The proposed tool considers the parasitic effects prior to layout. It employs a knowledge-aware optimization technique. The augmentation between parasitic-aware and knowledge-aware techniques speeds up the design process and leads to a design as close to the final design after finalizing the layout. The proposed tool gives limitless and guaranteed converged solutions in a wide range of RF frequencies. A four-bits current steering VGA design is used as a validation of the tool. The tool is tested on three different frequencies using the 65 nm-technology node. The three tested frequencies (7, 10, and 13 GHz) show a root mean square gain error at approximately 0.1 dB and a phase variation at approximately 3.5° within a 16-dB gain control range. To our knowledge, it is the first reported automated design tool for a current steering VGA.

1. Introduction

Today, the telecom industry is rapidly expanding the deployment of mm-wave 5G technologies to meet the demand for higher data rate wireless signals. Phased-array beamforming is used to mitigate the range difficulty in these systems. Controlling the phase and magnitude of the signals at every antenna element creates constructive and destructive electromagnetic interference patterns over the air, generating physical, 3D beams. A variable gain amplifier (VGA) circuit is an essential building block that is responsible for controlling the gain of different streams for beamforming applications [1]. VGA is used to produce a range of gain states with minimal RMS gain step error smaller than 0.2–0.3 dB where this amplitude adjustment helps the phased array to achieve high sidelobe suppression, while maintaining the least possible RMS phase error between states.

Designing VGAs at mm-wave frequencies is challenging because of the parasitics that contribute to performance at these high frequencies. Electromagnetic simulations are necessary at these frequencies to capture the effect of wiring and coupling between the different passive components, such as on-chip inductors [2]. This increases the design cycle significantly and optimum design may not be achievable. Parasitic-aware design techniques help to speed up the design processes by estimating the parasitics of interconnects of both active and passive devices. In addition, automation and optimization of the design can reduce the design time as well as lead to an optimum design.

Design automation is mainly divided into two main categories, knowledge-based approach and optimization-based approach [1,2,3,4,5]. The main advantage of the former is the speed, while the disadvantage is the time needed to develop the knowledge database, done before the process. The latter is divided into sub-categories, equation-based optimization, and simulation-based optimization [3]. The equation-based approach suffers from accuracy, especially if parasitics are included, while for the simulation-based approach a larger processing time is required [3]. An equation-based approach suffers from accuracy, especially if parasitics are included, while for the simulation-based approach a larger CPU time is required [3]. For both approaches, parasitic estimation during the optimization leads to a higher accuracy as well as fewer design iterations. A parameterized layout generator and parasitic extraction are used to consider the effect of on-chip inductors and interconnect parasitics shown in [4]. The parasitics are modeled with ideal components within the schematics of the circuit that is being optimized. Other approaches use approximate inductor analytical models, 2–π-models [5] and have been applied to different circuit classes. In [2], an algorithm that performs parasitic-aware automatic layout for analog/RF integrated circuits is presented. The algorithm creates a reduced-template-graph from original layouts and adds parasitic constraints. Using a two-dimensional hybrid scheme of graph-based optimization and nonlinear programming, the nonlinear problem is solved. The algorithm has successfully retargeted operational amplifiers and an RF low-noise amplifier within minutes of CPU time. An optimization methodology, presented in [6], based on adaptive simulated annealing (SA) with tunneling algorithm and a post-optimization PVT design centering strategy is used to model the parasitics of a self-biased fully differential RF CMOS PA. More recently another approach that combines genetic optimization algorithm and performance models (PMs) is presented in [7]. Device and interconnect parasitics are modeled into symbolic models, using foundry-provided equations and analytical models, respectively. Finally, to avoid in-the-loop EM simulations, in [8,9], a Pareto-optimal front (POF) of EM-simulated inductors is obtained prior to any circuit optimization, then, the POF is used as inductor design space (IDS) during circuit sizing. Another approach in [10] exploits the full capabilities of the most established computer-aided design tools for RF design available nowadays, i.e., RF circuit simulator as performance evaluator, electromagnetic simulator for inductor characterization, and layout extractor to determine the complete circuit layout parasitics. Liu et al. [11] proposed a simulation-based optimization approach for RF amplifiers, where machine learning techniques are used to build an inductor surrogate model. The accuracy of such a model is iteratively improved by refining the model with EM simulation results of promising inductors, instead of performing EM simulation of each candidate inductor, shown in [12].

A novel automated parasitic-aware simulation-based optimization design tool for designing mm-wave current steering VGAs is proposed in this paper. The augmentation between the parasitic-aware and knowledge-aware optimization methodologies speeds up the design process and help to achieve a design as close to the final design after finalizing the layout. To our knowledge, it is the first reported automated tool used to design current steering VGAs.

The paper is organized as follows: Section 2 presents the chosen architecture of the mm-wave digitally controlled current steering VGA. In Section 3, an overview of the proposed tool will be presented. Two subsections of Section 3 will address in detail the parasitic estimation methodology and the knowledge-aware simulation-based optimizer. The optimizer subsection explains the RF design trade-offs and the optimization flow. Section 4 presents the verification and simulation results, where the results of three test cases for the adopted VGA and the template layout are presented. Finally, in Section 5, conclusions are drawn.

2. N-Bits Digitally Controlled Current Steering Variable Gain Amplifier (VGA)

The most common topology of mm-wave VGAs relies on current steering using a cascode device [13,14]. Another circuit topology of VGA is to use an amplifier followed by a digital step attenuator [15,16,17], but the attenuator increases the circuit noise losses. Finally, current splitting techniques are another method to control the gain of the VGA [18].

Current steering topology is preferred over its alternatives due to its constant current and transconductance under different gain states, but the operating bandwidth would be limited by the current steering circuits. This topology is usually implemented using differential architecture for enhanced linearity [19,20,21,22].

In this paper, the automatic sizing of the digitally controlled current steering VGA shown in Figure 1 is proposed. The VGA is similar to a differential amplifier with a cascode input stage [1]. Four control bits enable/disable a few of the cascode devices to steer the current away/to the load to control the gain. Transistors Mp1-4 are used to ensure that a constant current is flowing through the main transistor Mm. By correctly sizing the transistors (Mm, Mcas, Mp1-4, and Mc1-4) a linear-in decibel gain step can be achieved. Turning on the auxiliary transistors decreases gain but the output impedance changes, which results in phase variations between the different gain states. An RC feedback network ($R_F$ and $C_F$) is added to the cascode transistor for stability and wide bandwidth realization.

The cascode amplifier is conventionally used in broadband circuits to improve reverse isolation of the transistor. At high frequencies, design of cascode amplifiers entails resolving several issues one of them is the effect of parasitic inductive components associated with bias lines, interconnects, ground back-vias, bypass capacitors and bond-wires. This inductive effect results in cascode amplifiers instability at high frequencies. The stability can be improved by inserting a series gate resistance in the gate of the CG device and in some cases, it is needed to add capacitance. It has been shown that this RC network should be selected within the specific ranges to improve stability; otherwise, it can even degrade the amplifier stability [23].

Decreasing the root mean square (RMS) phase error is achieved by adjusting the values of the output matching network together with adjusting the interstage inductor to help tune out the equivalent parasitic capacitance at the intermediate node to minimize the phase/impedance variation during gain tuning. Source degeneration is added to improve linearity.

3. Proposed Automated Web-Based Design Tool

Figure 2 shows a top-level description of the proposed parasitic-aware design tool for the mm-wave digitally controlled current steering VGAs. The four main pillars of the presented tool are a web interface, a CAD RF circuit simulator, a simulator-based optimizer, and a parasitic device model generator. The proposed tool uses a parasitic device model generator to model the parasitics of both active and passive devices such that the generated design is as close as possible to the final design after finalizing the layout.

The web interface is developed using PHP, HTML, CSS, and JavaScript. It is used to get the user’s required specifications. Shell scripting is used to handle the logic of the design flow. It communicates with the RF simulator using ocean scripting and calls the optimizer to run the proposed optimization algorithm. Once the design is finalized, the final report is generated and displayed to the user through the web interface.

The parasitic device model generator estimates the parasitics to be used during the optimization phase to speed up the design time and reduce the iterations after generating the layout. Knowledge-aware simulation-based optimization is used to quickly size the circuit with a reduced number of iterations. In the following subsections, the parasitic device model generator and the knowledge-aware simulation-based optimizer are explained in detail.

3.1. Parasitic Device Model Generator

Modeling of inductors and capacitors includes lots of non-idealities. For inductors, ohmic losses, parasitic inductive effects, substrate effects, unknown ground return paths, and self-resonances are examples of those non-idealities. While for capacitors, those non-idealities include parasitic capacitance to ground, ohmic losses, and self-resonances [23]. For the proposed design automation tool, the models of capacitors and inductors provided by the foundry PDK are used directly because of the high accuracy of modeling.

Regarding the active devices, the proposed parasitic device model generator estimates the parasitics of the active device after extraction during the optimization loop. Those parasitic capacitances include the interconnections capacitance, extra gate-to-source capacitance $\left(C_{gs}\right)$, extra gate-to-drain capacitance $\left(C_{gd}\right)$, and extra drain-to-source capacitance $\left(C_{ds}\right)$ introduced because of wiring. The model was generated using linear regression method to have an analytical expression for those capacitances. The linear equations for those extra capacitances are defined as follows:

$$C_{gs}\left(fF\right)=\left(-18.46+0.676 N+14.93 w \left(\mu m\right)\right)M,$$

(1)

$$C_{gd}\left(fF\right)=\left(-17.83+0.683 N+13.87 w \left(\mu m\right)\right)M,$$

(2)

$$C_{ds}\left(fF\right)=\left(-29.02+0.907 N+23.45 w \left(\mu m\right)\right)M,$$

(3)

where N is the number of fingers, M is the number of multipliers, and w is the width per finger in $\mathsf{\mu }\mathrm{m}$ of the CMOS transistor. Figure 3 and Figure 4 show a comparison of the extracted extra capacitance versus the one generated using (1)–(3) for different channel width and assuming minimum channel length. As depicted, the equation models the extra capacitance with high accuracy. This analytical expression helps to speed up the optimization loop.

3.2. Knowledge-Aware Simulation-Based Optimizer

RF design tradeoffs are very challenging, where the value of one design parameter could determine several of the design specifications. This could lead to a longer optimization time as well as the optimizer may not reach a solution. The proposed optimization algorithm is based on the knowledge of the designer by dividing one complex optimization into several smaller optimization steps to overcome the problem. Weighting factors are also used to determine which design specification is important to meet. The optimization core uses Broyden–Fletcher–Goldfarb–Shanno (BFGS) optimization algorithm implemented within the virtuoso environment [24]. The details of the knowledge-aware simulation-based optimization are discussed below starting from determining the different design specifications trade-offs and their dependency on the design parameters and ending with the proposed design flow.

3.2.1. Design Specifications Trade-Offs

The VGA, shown in Figure 1, has several design parameters. These design parameters determine the final specifications. The design specifications include input/output matching, gain, linearity, phase variation with step, etc. To avoid having time-consuming iterations during the optimization, the sensitivity of the design specification to the various design parameters is analyzed below. The sensitivity is determined using analytical equations and verified with simulations.

The input impedance of the VGA, shown in Figure 1, can be obtained using the simplified schematic in Figure 5. In the analysis below, the gate to source parasitic capacitance is considered. It could be shown that the input impedance is given by:

$$\begin{gathered} {\mathit{Z}}_{\mathit{i}\mathit{n}}\mathbf{=}\frac{{\mathit{s}}^{\mathbf{2}}{\mathit{C}}_{\mathit{m}\mathit{l}}{\mathit{L}}_{\mathit{m}\mathit{i}}{\mathit{Z}}_{\mathbf{1}}\mathbf{+}\mathit{s}{\mathit{L}}_{\mathit{m}\mathit{i}}\mathbf{+}{\mathit{Z}}_{\mathit{1}}}{\mathbf{1}\mathbf{+}\mathit{s}{\mathit{C}}_{\mathit{m}\mathit{l}}{\mathit{Z}}_{\mathbf{1}}\mathbf{+}\mathit{s}{\mathit{C}}_{\mathit{m}\mathit{s}}{\mathit{Z}}_{\mathbf{1}}} \\ \mathit{w}\mathit{h}\mathit{e}\mathit{r}\mathit{e}\mathbf{,} {\mathit{Z}}_{\mathbf{1}}\mathbf{=}\frac{\mathbf{1}}{\mathit{s}{\mathit{C}}_{\mathit{g}\mathit{s}\mathbf{1}}}\mathbf{+}\mathit{s}{\mathit{L}}_{\mathit{s}}\mathbf{+}\frac{{\mathit{g}}_{\mathit{m}\mathbf{1}}{\mathit{L}}_{\mathit{s}}}{{\mathit{C}}_{\mathit{g}\mathit{s}\mathbf{1}}} \end{gathered}$$

(4)

where $\mathit{s}$ is Laplace variable s ($=\mathit{j}\mathit{\omega }$), ${\mathit{L}}_{\mathit{m}\mathit{i}} \mathbf{\left(}\mathit{H}\mathbf{\right)}$ is the inductance of the input matching network, ${\mathit{C}}_{\mathit{m}\mathit{s}}$ and ${\mathit{C}}_{\mathit{m}\mathit{l}}$ are the capacitances of the input matching network, ${\mathit{C}}_{\mathit{g}\mathit{s}\mathbf{1}}$ and ${\mathit{g}}_{\mathit{m}\mathbf{1}}$ are the main transistor (${\mathit{M}}_{\mathit{m}}$) gate-to-source parasitic capacitance and transconductance, respectively, and ${\mathit{L}}_{\mathit{s}}$ is the source degenerated inductance. As depicted in (4), the input impedance depends mainly on the input matching network parameters, the transconductance of the main transistor, and the source degenerated inductor, ${\mathit{L}}_{\mathit{s}}$.

The max gain for the VGA is given by:

$${\mathit{A}}_{\mathit{v}}\mathbf{=}\frac{\mathit{s}\mathit{g}{\mathit{m}}_{\mathbf{1}}{\mathit{L}}_{\mathit{o}}}{\mathbf{\left(}\mathit{s}{\mathit{L}}_{\mathit{o}}\mathbf{+}\raisebox{1ex}{$\mathbf{1}$}\!\left/ \!\raisebox{-1ex}{$\mathit{B}$}\right.\mathbf{\right)}\mathbf{\times }\mathbf{\left(}\mathit{B}\mathbf{\right)}\mathbf{\times }\mathbf{\left(}\mathbf{1}\mathbf{+}\mathit{S}{\mathit{g}}_{\mathit{m}\mathbf{1}}{\mathit{L}}_{\mathit{s}}\mathbf{\right)}}$$

where

$$\mathit{B}\mathbf{=}\frac{\mathbf{1}}{\mathit{s}{\mathit{L}}_{\mathit{o}\mathbf{1}}\mathbf{+}{\mathit{r}}_{\mathit{o}2}\mathbf{\left[}\raisebox{1ex}{${\mathit{g}}_{\mathit{m}\mathbf{2}}\mathbf{\left(}\mathit{s}{\mathit{g}}_{\mathit{m}\mathbf{1}}{\mathit{L}}_{\mathit{i}\mathit{n}\mathit{t}}\mathbf{-}\mathbf{1}\mathbf{\right)}$}\!\left/ \!\raisebox{-1ex}{$\mathbf{\left(}{\mathit{s}}^{\mathbf{2}}{\mathit{g}}_{\mathit{m}\mathbf{1}}{\mathit{c}}_{\mathit{g}\mathit{s}\mathbf{2}}{\mathit{L}}_{\mathit{i}\mathit{n}\mathit{t}}\mathbf{-}\mathit{s}{\mathit{c}}_{\mathit{g}\mathit{s}\mathbf{2}}\mathbf{+}{\mathit{g}}_{\mathit{m}\mathbf{1}}\mathbf{\right)}$}\right.\mathbf{+}\mathbf{1}\mathbf{\right]}\mathbf{+}\raisebox{1ex}{$\mathbf{1}$}\!\left/ \!\raisebox{-1ex}{$\mathit{s}{\mathit{L}}_{\mathit{o}\mathit{p}}$}\right.}$$

(5)

where ${\mathit{A}}_{\mathit{v}}$ is the overall gain, $\mathit{s}$ is Laplace variable s ($=\mathit{j}\mathit{\omega }$), $\mathit{g}{\mathit{m}}_{\mathbf{1}}$ and $\mathit{g}{\mathit{m}}_{\mathbf{2}}$ are the main and the cascode transistor’s transconductance, respectively, (${\mathit{L}}_{\mathit{o}}$, ${\mathit{L}}_{\mathit{o}\mathbf{1}}$, and ${\mathit{L}}_{\mathit{o}\mathit{p}}$) are the inductors of the output matching network, ${\mathit{L}}_{\mathit{i}\mathit{n}\mathit{t}}$ is the interstage inductor between the main and the cascode transistors, ${\mathit{c}}_{\mathit{g}\mathit{s}\mathbf{2}}$ is the parasitic gate-to-source capacitance of the cascode transistor, and ${\mathit{r}}_{\mathit{o}\mathbf{2}}$ is the output resistance of the cascode amplifier.

In addition, the RMS gain error between its different steps can be found using the:

$$\mathit{R}\mathit{M}\mathit{S} \mathit{g}\mathit{a}\mathit{i}\mathit{n} \mathit{e}\mathit{r}\mathit{r}\mathit{o}\mathit{r}\mathbf{=}\sqrt{\frac{\mathbf{1}}{\mathit{N}\mathbf{-}\mathbf{1}}{\displaystyle \mathbf{\sum }}_{\mathit{n}\mathbf{=}\mathbf{2}}^{\mathit{N}}{\mathbf{\left|}\mathsf{\Delta }\mathit{S}{\mathbf{21}}_{\mathit{i}}\mathbf{-}\mathit{S}{\mathbf{21}}_{\mathit{s}\mathit{t}\mathit{e}\mathit{p}}\mathbf{\right|}}^{\mathbf{2}}}$$

(6)

where N is the number of states, $\mathsf{\Delta }\mathit{S}{\mathbf{21}}_{\mathit{i}}$ is the step between the gain of state (i) and gain of state (i−1), and $\mathit{S}{\mathbf{21}}_{\mathit{s}\mathit{t}\mathit{e}\mathit{p}}$ is the achieved gain step between the N states.

Equation (5) indicates that the max gain depends on the output matching network parameters, the transistors transconductances, and the interstage inductor, and is inversely proportional to the source degenerated inductor. Furthermore, those parameters have a direct impact on the linearity (Input P1dB). Figure 6 shows the simulated gain, ${\mathit{S}}_{\mathbf{21}}$, and the simulated IP1dB versus the value of the input matching inductor, ${\mathit{L}}_{\mathit{m}\mathit{i}}$. As depicted, the max gain is achieved for an inductance value of 500 pH, while the input P1dB reaches its minimum value. This shows the trade-off between those design specifications. During the optimization, the inductance of the input matching network, ${\mathit{L}}_{\mathit{m}\mathit{i}}$, should be considered during gain and input P1dB optimization.

Another trade-off between gain and the input P1dB appears versus current through the main device and it’s sizing as shown in Figure 7 and Figure 8. Simulations show another trade-off between gain and stability for the presented VGA architecture also seen in Figure 8. As depicted, increasing the main amplifier channel width (${\mathit{W}}_{\mathit{m}})$ increases the gain of the VGA but decreases its stability factor (${\mathit{K}}_{\mathit{f}})$.

Phase variations between states are another important design specification at VGAs design, which is targeted to be minimal. The phase of every state is obtained using the:

$$\begin{gathered} \angle A_v={\tan }^{-1}\frac{Imaginary \left(A_v\right)}{Real \left(A_v\right)}= \\ \begin{array}{cc}90°-\hfill & {\tan }^{-1}(\frac{\omega L_o+\omega L_{o1}-\raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$\omega L_{op}$}\right.-\omega g{m}_{2}g{m}_1^2{C}_{gs2}{L}_{int}}{r_{o2}})\hfill \\ \hfill & -{\tan }^{-1}(\frac{\omega L_{o1}-\raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$\omega L_{op}$}\right.-\omega g{m}_{2}g{m}_1^2{C}_{gs2}{L}_{int}}{r_{o2}})\hfill \\ \hfill & -{\tan }^{-1}\left(\omega g_{m1}{L}_s\right)\hfill \end{array} \end{gathered}$$

(7)

Some parameters which help in decreasing the phase variations between states to minimum also affect linearity. Figure 9 shows that increasing the output inductance increases the input P1dB but also increases the phase variations. This shows the trade-off between those design specifications. During the optimization, the inductance of the output matching network, $L_o$, should be considered during phase and input P1dB optimization.

The RMS phase error is given by:

$$RMS phase error=\sqrt{\frac{1}{N}{\displaystyle \sum }_{n=1}^N{\left|{\varnothing }_i-{\varnothing }_{i-1}\right|}^2}$$

(8)

where N is the number of states, ${\varnothing }_i$ is the phase of state (i) and ${\varnothing }_{i-1}$ is the phase of state (i−1).

Figure 10 shows that well-sizing of the controlling transistors ($M_{C1-4}$) results in increasing the gain-step between states and decreasing the phase variations between them.

Table 1. Specifications and the corresponding parameters in the control.

Controlling Parameters	Specifications
	Gain Step	Phase Variation	Stability	Linearity
Controlling transistors sizes (Wcontrolling)	✓
Output matching network (Co, Lct, Lo1, and Lop)	✓	✓		✓
Interstage inductor (Lint)		✓
Transistor sizing (Wm and Wc)			✓	✓
RC—feedback network (CF and RF)			✓
Source degenerated inductor (Ls)	✓			✓
DC source (Idc)	✓			✓

summarizes the main specifications with their corresponding controlling design parameters to better guide the optimization process. Together with the weighting factors methodology, the optimizer operates faster and its possibility to enter an infinite loop diminishes.

3.2.2. Knowledge-Aware Simulation-Based Optimization Flow

The proposed optimization algorithm depends on the optimizer core algorithm (BFGS) built within the virtuoso environment, and the proposed knowledge-aware and the weighting factor methodologies.

The knowledge-aware methodology divides the complex optimization problem into several smaller optimization steps. Those steps depend on the knowledge and experience of the designer to identify the sensitivity of the performance specifications to the design parameters. The studied sensitivity test is done through deriving analytical expressions and is verified by simulations.

Table 2. The optimizer different stages with the corresponding parameters to be optimized for the required specification.

Steps	Targeted Specification	Parameters to Be Optimized
1	S11	I/P matching network elements (Lmi, Cin, Cms, and Cml)
2	S21	I/P matching network elements (Lmi, Cin, Cms, and Cml) and O/P matching network elements (Lo, Lo1, Lop, Co, and Cop)
3	Gain Step and RMS gain error	Sizing of the controlling transistors (Wcon)
4	RMS Phase error	Interstage inductor (Lint) and O/P matching network elements (Lo, Lo1, Lop, Co, and Cop)
5	Linearity (IP1dBc and IIP3)	Source degenerated inductor (Ls), Transistor sizing (Wm), Idc, and O/P matching network elements (Lo, Lo1, Lop, Co, and Cop)
6	Stability and Bandwidth realization	F.B. RC network elements (Rcas and Ccas) and the inductor of the output matching network (Lo1)

illustrates the different optimization steps to speed up the optimization process. It includes the optimization steps, the corresponding performance specification, and the design parameters to optimize.

Weighting factors are used for the different goals to help the optimizer to converge and reach an optimum solution that satisfies the different specified constraints. These weighting factors are entered by the user into the input interface of the proposed tool according to his priority list of specifications.

The RF simulator generates the inclusive netlist and then invokes the optimizer using the initial design parameters saved within the tool. The optimizer starts its optimization algorithm. After each optimization stage, according to Table 2, the inclusive netlist is updated by the results of each optimization stage. Below is a summary of the design flow:

• The user enters the required specifications with their weighting factors through the web GUI, while initial design parameters are available within the tool.
• The spice simulator generates the schematic inclusive netlist from virtuoso and the parasitic device model generator.
• The optimizer starts its optimization algorithm (BFGS) guided by the weighting factors entered by the user to know which design specification to meet first.
• Firstly, it checks on the transistors’ regions making sure that transistors are in their correct region. If this check fails, the optimizer will sweep on the transistor’s sizes and the dc current source till it passes. Every optimization loop will be on a more confined range for the concerned design parameters.
• The optimizer then simulates all the specifications giving a message indicating which specification passes and which fails.
• Depending on the weighting factor optimization methodology, the optimizer chooses which specification to meet first. Following table II, shown below, the optimizer will enter the right step stage and thereby sweeps on the parameters in favor of the specified specification.
• Repeat steps 4 to 6 till all the targeted specifications are achieved.
• Finally, the tool displays the optimized parameters, the achieved specifications, the circuit schematic, and the template of the layout with the GDSII file for further modification.

Figure 11 shows a comprehensive flow chart describing the optimization algorithm. Additionally, Table 2 shows the different step stages the optimizer can enter with the corresponding parameters to optimize on for the specification needed to be met.

4. Verification and Simulation Results

Simulation Results

The proposed tool is used for the automatic sizing of the current steering VGAs. It shows optimal design performance on a range of frequencies up to 15 GHz. The design of the VGA, using the proposed tool, is done at 7 GHz, 10 GHz, and 13 GHz using a 65nm-technology node.

Table 3. Initial design parameter values for the optimizer.

Input Matching Network		Output Matching Network		Intermediate Inductance
Cin (fF)	850	Lct (pH)	600	Lint (pH)	700
Cml (fF)	700	Lo1 (pH)	600	Cascode RC network
Cms (fF)	700	Lop (pH)	600	Rcas (KΩ)	10
Lmi (pH)	400	Cmo (fF)	400	Ccas (fF)	80
Channel width for RF CMOS transistors				Feedback network
Wm = Wc =Wp (um)	2	Ncon3 = Np3	8	RF (KΩ)	1
Wcon (nm)	600	Ncon4 = Np4	4	CF (fF)	80
Nm = Nc	32	Mm	2	Source degenerated inductance
Ncon1 = Np1	32	Mc	1	Ls (pH)	300
Ncon2 = Np2	16	Mcon	1

where m: main, C: cascode, con: controlling, p: parallel, W: width per finger, N: number of fingers, and M: number of multipliers.

shows the initial design parameters for any design specifications. In addition, a template for the layout is generated to help the user to finalize the layout. For the three test frequencies, Figure 12 shows the simulated phase and gain versus the number of states, respectively. Figure 13 and Figure 14 show the simulated ${\mathit{S}}_{\mathbf{21}}$ and ${\mathit{S}}_{\mathbf{11}}$ versus frequency, respectively. As depicted in the graphs and

Table 4. Comparison between the achieved specifications from the proposed tool at the three test frequencies and the required ones.

Specifications	Required Specifications at 7 GHz	Achieved Specifications at 7 GHz	Required Specifications at 10 GHz	Achieved Specifications at 10 GHz	Required Specifications at 13 GHz	Achieved Specifications at 13 GHz
S11Frf	<−7 dB	−8 dB	<−7 dB	−14.11 dB	<−7 dB	−12.05 dB
S21max	>5 dB	6.64 dB	>5 dB	7.2 dB	>5 dB	7.11 dB
IP1dBmin	>−3 dBm	5.2 dBm	>−3 dBm	0.83 dBm	>−3 dBm	3.7 dBm
Bandwidth-min	3 GHz	3 GHz	1.5 GHz	1.7 GHz	3 GHz	4 GHz
Phase Variation	(−5°)–5°	−5°	(−5°)–5°	4.49°	(−5°)–5°	3.295°
Gain Step	0.3 dB	0.2581 dB	0.5 dB	0.417 dB	0.4 dB	0.3367 dB
IIP3	>3 dB	12.67 dBm	>3 dB	8.6 dBm	>3 dB	11.95 dBm
RMS Gain Error	0.1–0.2	0.05	0.2–0.3	0.085	0.1–0.3	0.035
RMS Phase Error	0.2°–0.3°	0.34°	0.2°–0.3°	0.26°	0.4°–0.6°	0.6°

, the requested specifications for the three test frequencies are achieved.

The high current of RF circuits puts high constraint on the devices’ layout. Electromigration is considered to avoid device breakdown. The circuit’s layout was made for the 10 GHz design as a template layout for other designs. The layout took an active area $960 \mathsf{\mu }\mathrm{m}\times 1090 \mathsf{\mu }\mathrm{m}$, as shown in Figure 15.

5. Conclusions

Web-based parasitic-aware automation and optimization RF design tool for mm-wave digitally controlled current steering VGAs has been proposed in this paper. The tool uses an optimizer embedded in a virtuoso environment, which uses the BFGS algorithm to reach optimal design parameters for the users’ targeted specifications. The theory and the optimization algorithm were demonstrated in this paper. The tool considers before design procedures the parasitics of both the active and the passive devices. MOSFETs’ parasitics and its interconnections are modeled as physical ideal capacitances, and analytical equations for the estimated parasitic capacitances are obtained through a linear regression method which relates the parasitic capacitance to the transistor sizes. Inductors and capacitors are used from the technology design kit, 65nm technology node, for parasitic inclusion. The obtained results for the three test frequencies assure the effectiveness of the parasitic aware design technique proposed in the presented tool.