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Article

CNTFET-Based Ternary Multiply-and-Accumulate Unit

by
Amr Mohammaden
1,
Mohammed E. Fouda
1,2,*,
Ihsen Alouani
3,
Lobna A. Said
1 and
Ahmed G. Radwan
4,5
1
Nanoelectronics Integrated Systems Center (NISC), Nile University, Giza 12588, Egypt
2
Center for Embedded and Cyber-Physical Systems, University of California-Irvine, Irvine, CA 92612, USA
3
IEMN DOAE, UMR CNRS 8520, Polytechnic University Hauts-de-France, 59300 Valenciennes, France
4
Engineering Mathematics and Physics Department, Faculty of Engineering, Cairo University, Giza 12613, Egypt
5
School of Engineering and Applied Sciences, Nile University, Giza 12588, Egypt
*
Author to whom correspondence should be addressed.
Electronics 2022, 11(9), 1455; https://doi.org/10.3390/electronics11091455
Submission received: 31 January 2022 / Revised: 6 April 2022 / Accepted: 7 April 2022 / Published: 30 April 2022
(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)
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Abstract

Multiply-Accumulate (MAC) is one of the most commonly used operations in modern computing systems due to its use in matrix multiplication, signal processing, and in new applications such as machine learning and deep neural networks. Ternary number system offers higher information processing within the same number of digits when compared to binary systems. In this paper, a MAC is proposed using a CNTFET-based ternary logic number. Specifically, we build a 5-trit multiplier and 10-trit adder as building blocks of two ternary MAC unit designs. The first is a basic MAC which has two methods to implement, serial and pipeline. The second is an improved MAC design that optimizes the number of transistors, offers higher performance and lower power consumption. The designed MAC unit can operate up to 300 MHz. Finally, a comparative study in terms of power, delay, and area variations is conducted under different supply voltages and temperature levels.
Keywords: ternary logic gates; CNTFET; ternary full adder; ternary multiplier; multiply-and-accumulate ternary logic gates; CNTFET; ternary full adder; ternary multiplier; multiply-and-accumulate

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MDPI and ACS Style

Mohammaden, A.; Fouda, M.E.; Alouani, I.; Said, L.A.; Radwan, A.G. CNTFET-Based Ternary Multiply-and-Accumulate Unit. Electronics 2022, 11, 1455. https://doi.org/10.3390/electronics11091455

AMA Style

Mohammaden A, Fouda ME, Alouani I, Said LA, Radwan AG. CNTFET-Based Ternary Multiply-and-Accumulate Unit. Electronics. 2022; 11(9):1455. https://doi.org/10.3390/electronics11091455

Chicago/Turabian Style

Mohammaden, Amr, Mohammed E. Fouda, Ihsen Alouani, Lobna A. Said, and Ahmed G. Radwan. 2022. "CNTFET-Based Ternary Multiply-and-Accumulate Unit" Electronics 11, no. 9: 1455. https://doi.org/10.3390/electronics11091455

APA Style

Mohammaden, A., Fouda, M. E., Alouani, I., Said, L. A., & Radwan, A. G. (2022). CNTFET-Based Ternary Multiply-and-Accumulate Unit. Electronics, 11(9), 1455. https://doi.org/10.3390/electronics11091455

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