A Figure of Merit for Selection of the Best Family of SiC Power MOSFETs

Abstract

This paper proposes a criterion to select the best family of commercial SiC power metal–oxide–semiconductor field-effect transistors (MOSFETs) that provides the highest quality and reliability. Applying a recently published integrated-charge method, a newly proposed figure of merit is correlated to the density of near-interface traps that degrade the quality and reliability of SiC MOSFETs. The applicability of the proposed figure of merit is experimentally demonstrated with the most widely used and commercially available planar and trench MOSFETs from different manufacturers.

1. Introduction

Power semiconductor devices are key components of advanced power conversion systems. The SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) are now available commercially and contribute towards the development of power-conversion systems with a reduced size and reduced power losses. Compared to silicon, SiC permits the use of much higher doping concentrations and thinner drift layers for a given blocking voltage [1,2]. This results in a much smaller on-resistance, $R_{DS\left(on\right)}$ [3]. Moreover, continued effort by the industry to improve the performance and reliability results in modified processes and device structures for the case of both planar and trench MOSFETs.

Despite all of the advancements, oxide defects near the SiO${}_2$/SiC interface continue to degrade the quality and reliability of SiC MOSFETs [4]. These defects act as near-interface traps (NITs) that capture and release electrons, creating both performance and reliability issues [5,6,7]. At sub-threshold voltages, the NITs energetically located below the conduction band capture electrons and appear as fixed charge that increases the threshold voltage. The density of these NITs can increase during device operation, which degrades the reliability of the device [8,9]. However, when the gate voltage is increased above the threshold voltage, the quantum confinement effect sets the Fermi level inside the conduction band. In that case, the NITs with energy levels aligned to the Fermi level inside the conduction band constantly capture and release electrons from the MOSFET channel. This drops the effective mobility of channel carriers from a trap-free level of around 200 cm${}^2$/Vs down to around 30–40 cm${}^2$/Vs, because—on average—more than 80% of electrons attracted by the gate voltage can be trapped by NITs at any instant of time [7,10,11]. This reduction in the effective channel-carrier mobility increases the on-resistance of the MOSFET [12,13].

The on-resistance can be reduced by increasing the effective channel width of the MOSFET, but this will increase the output capacitance, which will cause an increase in the dynamic power dissipation, which becomes increasingly important as the switching frequency is increased. However, if a specific technology process or device structure—such as planar or trench MOSFETs—reduces the density of near-interface traps ($N_{NIT}$), the quality and reliability of all MOSFETs in this family will be higher.

Every manufacturer provides several device parameters in their datasheets of the device. Even then, various other device parameters that are not provided in the datasheets have a significant impact on the quality and reliability of MOSFETs. As a result of that, circuit designers are unable to select the best family of MOSFETs and then decide on a specific MOSFET from that family, based on the values of the on-resistance and output capacitance that would minimize the power dissipation in their circuits.

In this paper, we propose a simple criterion to select the best family of MOSFETs. Using our recently published method [7,14] for the measurement of the density of near-interface traps in commercial MOSFETs, we demonstrate in the paper that the simple criterion ensures the selection of the commercially available MOSFET family with the lowest density of NITs and, therefore, the highest quality and reliability.

2. Theory

2.1. Dependence of on-Resistance on the Density of near Interface Traps

The constant endeavor of the semiconductor industry is to minimize the power dissipation and increase the current handling capability by reducing $R_{DS\left(on\right)}$ through improvements in the manufacturing process [15]. However, there exists a high density of NITs at the SiO${}_2$/SiC interface of the SiC MOSFETs [13,16]. These NITs trap electrons from the channel and reduce the effective channel-carrier mobility of the device [14]. This reduction in mobility increases the channel resistance ($R_{CH}$) and consequently increases the $R_{DS\left(on\right)}$ of the MOSFET [17,18].

2.2. The Figure of Merit for Selection/Comparison of SiC MOSFET Families

The width of the channel (W) is a critical parameter that is not available in the power MOSFET datasheets. It is a well known fact that the $R_{DS\left(on\right)}$ of the power MOSFET is inversely proportional to W [16,17,19]. Accordingly, MOSFETs with different $R_{DS\left(on\right)}$ values that are in a single family have different W values, whereas all other technological parameters are the same. In power MOSFETs, W is proportional to the gate area and, consequently, the gate-capacitance ($C_G$) of the device is directly proportional to W [16,17]. Multiplying $R_{DS\left(on\right)}$ and $C_G$ results in a quantity that is independent of W:

$$R_{DS\left(on\right)}\times C_G=\kappa$$

(1)

Due to the fact that the constant $\kappa$ groups all of the technical parameters of a particular MOSFET family, it can be considered as a figure of merit for that family of MOSFETs.

The proposed constant $\kappa$ is different from Baliga’s figure of merit [16], defined as $R_{DS\left(on\right)}\times Q_{GD}$, where $Q_{GD}$ is the charge at the gate-to-drain capacitance ($C_{GD}$) at the maximum drain-to-source voltage when the MOSFET is turned off ($V_{GS}=0$). In Baliga’s figure of merit, $Q_{GD}$ and $C_{GD}$ relate to the dynamic power dissipation, whereas $C_G$ in the proposed figure of merit is measured at $V_{DS}=0$ and, therefore, is unrelated to the dynamic power dissipation. The proposed figure of merit relates to the performance and reliability affected by NITs, which is different from optimizing dynamic and static power dissipation.

The $R_{DS\left(on\right)}$ is available in the datasheet of every MOSFET and only $C_G$ needs to be measured at the operating gate voltage ($V_G$) to obtain the value of $\kappa$.

3. Experimental Demonstration

3.1. Measurement of Gate Capacitance and On-Resistance

In this paper, we used 1200 V commercial N-channel SiC power MOSFETs manufactured by different manufacturers, with the parameters listed in

Table 1. On-resistance and measured gate capacitance at $V_G$ = 18 V for 1200 V commercial power MOSFETs.

MOSFET ID	Manufacturer	Gate Structure	On-Resistance (m$\Omega$)	Gate Capacitance (pF)
A-T	A	Trench	90	977
			350	280
B-P	B	Planar	281	530
C2-P	C	Planar	360	583
C3-P	C	Planar	282	592
D-T	D	Trench	105	1424
D-P	D	Planar	280	1635
E-P	E	Planar	192	1295

. The $R_{DS\left(on\right)}$ was determined using standard I–V measurements provided in the datasheets by the manufacturers.

For $C_G$ at the operating $V_G$, the C–V measurements were conducted with the source and drain terminals grounded. The $C_G$ can be given by:

$$C_G=C_{GS}+C_{GD}$$

(2)

where $C_{GS}$ is the gate-to-source capacitance and $C_{GD}$ is the gate-to-drain capacitance of the MOSFET at the operating gate voltage. It is important to note that $C_G$ is different from the input capacitance ($C_{iss}$) given in the datasheets. The datasheets provide $C_{iss}$ at zero gate voltage, rather than the operating $V_G$, and large drain-to-source voltages ($V_{DS}$) that deplete the drift region under the gate. Both $C_G$ and $C_{iss}$ are directly proportional to W, but $C_G$ is inversely proportional to the gate-oxide thickness, whereas $C_{iss}$ is inversely proportional to the depletion layer width, which can be different in different device structures [17].

Figure 1a shows the cross-section of a power MOSFET with a planar gate structure to illustrate that the capacitance $C_G$ at the operating gate voltage and $V_{DS}$ = 0. It can be observed that the MOSFET channel of electrons is created by the inversion of the P-type body at the semiconductor surface. Meanwhile, the drift region forms an accumulation layer, which means that the active area of the capacitance is equal to the gate area, $A_G$. The capacitance $C_{iss}$ at zero gate bias is illustrated in Figure 1b. As a result of small $V_G$ and large $V_{DS}$ values, the drift region under the gate is depleted. This creates a much thicker dielectric and, consequently, $C_{iss}$ is much lower than $C_G$.

Since most of the manufacturers provide $R_{DS\left(on\right)}$ at $V_G$ = 18 V, $C_G$ was measured at $V_G$ = 18 V to obtain the values of $\kappa$. The circuit designers can measure $C_G$ at $V_G$ = 18 V with standard AC measurements at 1 kHz, using any commercial instrument, such as Agilent or Keithley. However, it is important to note that the standard AC measurements at high frequencies (≥100 kHz) are not reliable because the high density of fast NITs distort the sinusoidal waveforms [17,20]. The issue with this distortion is that the AC method of capacitance measurements assumes undistorted sinusoidal signals.

3.2. Measurement of the Density of Near-Interface Traps

Trapped channel electrons by NITs do not contribute to the MOSFET current, which results in higher $R_{DS\left(on\right)}$ when the density of NITs is higher [17]. Given that the gate capacitance $C_G$ is a constant determined by the thickness of the gate oxide and the gate area, the value of $\kappa$ is also directly proportional to the density of NITs. In this section, we present an experimental demonstration that smaller values of $\kappa$ correspond to lower densities of NITs. The purpose is to justify the use of $\kappa$ as a figure of merit in terms of quality and reliability.

Measurement of the density of NITs ($N_{NIT}$) in commercial MOSFETs is possible by applying our recently published integrated-charge method [7,14]. This method can detect NITs with response times between 500 ns and 500 $\mathsf{\mu }$s.

To apply the integrated-charge method to a MOSFET, the drain and the source were connected to the ground and an external resistance $R_{EXT}$ was connected to the gate. The series $RC$ circuit was biased with a DC voltage, whose value was changed from +20 V to −20 V. At a set DC voltage, small voltage steps ($\Delta V_{step}$) of a variable step interval ($t_{step}$) were superimposed to the DC voltage in the form of a pulse waveform with the frequency $f=1/2t_{step}$. A Tektronix DPO 7104 oscilloscope with Tektronix P6139B voltage probes was used to measure the voltage across the $R_{EXT}$, and, in that way, to determine both the current charging the gate capacitance during $t_{step}=1/2f$ when $\Delta V_{step}$ is applied and the current discharging the capacitor during $t_{step}=1/2f$ when the pulse is removed. The charging and discharging currents are integrated to obtain the charge $q\Delta N_{carriers}$ in response to the applied voltage step. This charge corresponds to an apparent or electrically active gate capacitance $C_G=q\Delta N_{carriers}⁄\Delta V_{step}$.

Figure 2 shows the C–V curves obtained using the integrated-charge method and the standard AC measurement for both planar and trench MOSFETs from manufacturer D. All of the experiments were performed at room temperature. The integrated-charge measurements were performed with step intervals of 500 $\mathsf{\mu }$s and 500 ns. The standard AC measurements were performed at 1 kHz using an Agilent B1505A Power Device Analyzer. The purpose of showing a standard AC measurement at 1 kHz is to demonstrate that $C_G$ at $V_G$ = 18 V, needed to determine the value of $\kappa$ in (1), can be obtained either by commercial instruments or by the integrated-charge method.

It can be observed from Figure 2 that there is a reduction in the apparent capacitance when the measurements were performed with the shorter step interval. This is because the trapped charge with response times longer than ${\tau }_{min}=t_{step}$ does not contribute to the charging and discharging current. As a result, the integrated charge $q\Delta N_{carriers}$ is smaller and so is the apparent capacitance. Therefore, the density of trapped carriers per unit area with response times longer than 500 ns and shorter than 500 $\mathsf{\mu }$s is equal to:

$$\Delta N_{trapped}=\frac{\Delta N_{carriers}\left(500\mathsf{\mu }\mathrm{s}\right)-\Delta N_{carriers}\left(500\mathrm{ns}\right)}{A_G}$$

(3)

where $A_G$ is the gate area.

Given that the typical value of the gate-oxide thickness in commercial MOSFETs is 50 nm [7,21], $A_G$ was determined from the measured $C_G$ at $V_G$ = 18 V. The step interval of 500 $\mathsf{\mu }$s was selected as the reference because the trap density with a response time longer than 500 µs was too small to be detected.

The C–V curves in Figure 2 show that there is a trapping of electrons for positive gate voltages and trapping of holes for negative gate voltages. Since the trapping of holes does not impact the channel resistance, the trapping of electrons is considered for the calculation of the relevant $N_{NIT}$. The total density of trapped electrons at the relevant near-interface traps at a given $V_G$ can be calculated as:

$$N_{NIT}=\sum _0^{V_G}\Delta N_{trapped}$$

(4)

4. Application to Commercial Devices

We measured 1200 V commercial SiC power MOSFETs with both planar and trench structures. The $R_{DS\left(on\right)}$ and $C_G$ at $V_G$ = 18 V for all the MOSFETs are listed in Table 1. The density of NITs at $V_G$ = 18 V, measured for each MOSFET, and the corresponding figure of merit, $\kappa$, are shown in Figure 3. The planar MOSFETs are represented by the squares, whereas the trench MOSFETs are shown with circles. These results verify the theory that the figure of merit ($\kappa$) is proportional to the density of near-interface traps ($N_{NIT}$). The difference in $N_{NIT}$ in different families of MOSFETs is six times, which represents a significant difference between different manufacturers. This leads to the difference in the figure of merit of five times, which is due to the dominant impact of near-interface traps on $R_{DS\left(on\right)}$. Different manufacturers apply different processes for the gate dielectric, but the proposed method is applicable to these different dielectrics because $N_{NIT}$, as the ultimate result of these processes, is the quantity that directly impacts $R_{DS\left(on\right)}$ and the figure of merit.

Figure 3 also shows that the trench MOSFETs are better in comparison to the planar MOSFETs. This result may be surprising, but it is consistent with the higher channel-carrier mobility that is commonly observed in trench SiC MOSFETs.

It is important to note that the values of $C_G$ obtained by the standard AC measurements at 1 kHz, along with the values of $R_{DS\left(on\right)}$ available in the datasheets, are sufficient to determine the values of $\kappa$ by (1). This enables circuit designers to compare SiC MOSFET families and to select the MOSFET family with the lowest value of $\kappa$. This will ensure the lowest density of NITs and, hence, the best quality and reliability.

5. Conclusions

This brief proposes a figure of merit, $\kappa$, as a criterion for the selection of the best family of SiC power MOSFETs. The applicability of the proposed figure of merit was experimentally demonstrated for two gate structures—planar and trench—from five manufacturers. The values of $\kappa$ can easily be calculated using $R_{DS\left(on\right)}$ given in the MOSFET datasheets and a standard measurement of gate capacitance. The proposed figure of merit will enable power engineers to select the best MOSFET family in the first instance, and then to select a specific MOSFET from this family with the specific values of $R_{DS\left(on\right)}$ and output capacitance that minimize the sum of static and dynamic power dissipation in the designed circuit.