Low-Power Regulated Cascode CMOS Transimpedance Amplifier with Local Feedback Circuit

Abstract

In this paper, we propose a multistage transimpedance amplifier (TIA) based on the local negative feedback technique. Compared with the conventional global-feedback technique, the proposed TIA has the advantages of a wider bandwidth, and lower power dissipation. The schematic and characteristics of the proposed TIA circuit are described. Moreover, the proposed TIA employs inductive peaking to increase bandwidth. The TIA is implemented using a 65 nm complementary metal oxide semiconductor (CMOS) technology and consumes 23.9 mW with a supply voltage of 1.0 V. Using a back-annotated simulation, we obtained the following characteristics: a gain of 46 dB$\mathsf{\Omega }$ and −3 dB frequency of 11.4 GHz. TIA occupies an area of 366 $\mathsf{\mu }$m × 225 $\mathsf{\mu }$m.

1. Introduction

A transimpedance amplifier (TIA) is a very important building block for current optoelectronic communication systems, e.g., optical receivers for optical frequency combs [1,2,3], localized machine-to-machine (i.e., short distance) communication systems [4,5], or optical metro long-haul fiber communication systems [6,7,8]. The TIA is one of the most important components of optical receivers. Figure 1 shows the conceptual block diagram of an integrated optical heterodyne receiver [9]. For optical heterodyne receiver systems, we are confronted with a new problem of extending the bandwidth of the TIA, as well as the photodiode (PD) to maximize the range of synthesizable frequencies. TIAs can be fabricated using many different transistor processes, but CMOS process offers the ability of direct integration with digital logic circuits. This integration is vital, as the challenges encountered by optical heterodyne receivers include cost (e.g., chip size and power consumption). In [2,3], Costanzo proposed a current reuse regulated cascode (RGC) CMOS TIA; they then fabricated and measured it, but the proposed TIAs still had a high-power consumption.

In [8], to extend the frequency response, we proposed multiple shunt–shunt feedback (i.e., overall feedback) and fabricated it using a 0.25 $\mathsf{\mu }$m InP heterojunction bipolar transistor (HBT) process. The proposed TIA was designed for long-haul fiber communications using the InP HBT process; hence, when designing a complete optical receiver system, a digital part of the chip, such as field-programmable gate array or application-specific integrated circuit, is needed. This paper proposes an RGC type TIA based on a local feedback technique. Using the modified feedback technique, the frequency band of the proposed TIA is wider than that of our proposed shunt–shunt feedback. In this study, we designed a TIA using a 65 nm CMOS process and simulated it through post-layout. The results obtained were a 46 dB$\mathsf{\Omega }$ Gain and −3 dB frequency of 11.4 GHz. The remainder of this paper is organized as follows. Section 2 describes the conventional TIA based on the traditional broadband design technique using a multiple shunt–shunt overall feedback, then the proposed TIA based on the modified feedback technique is presented The post-layout simulation results are presented in Section 3 and the conclusions are summarized in Section 4. In Appendix A, the measured 2-port S-parameters of the fabricated TIA is presented, in order to simplify testings.

2. TIA Design

2.1. Conventional TIA Based on Overall Feedback Technique

Figure 2 shows a schematic of a conventional RGC TIA based on a feedback technique [8]. The TIA is composed of the following three parts: an RGC input stage (blue dotted line in Figure 2), two feedback-gain stages (red dotted line) and a source follower output stage [10]. Because the input current of the TIA core is divided by the shunt feedback network, the input impedance can be reduced. Therefore, the bandwidth of the proposed circuit is further expanded compared with the conventional simple RGC input stage.

2.2. Proposed TIA

2.2.1. Circuit Structure

Figure 3 shows the proposed TIA with overall and local feedback stages. Compared with the conventional TIA shown in Figure 2, the second feedback-gain stage of the proposed TIA has a local feedback configuration. The resulting frequency of the proposed TIA is expanded. To understand the circuit mechanism of the conventional and proposed TIA, we analyze their transfer functions in Section 2.2.2.

2.2.2. Analysis of Circuit Topology

To analyze the transfer function of feedback circuit, we consider the conventional and proposed TIA transfer models as shown in Figure 4 and Figure 5, where A is the gain of common source amplifier (transistor MN${}_2$ or MN${}_4$), $A_1$–$A_4$ are the gains of the amplifier in the first and second feedback stage, and $H_1$–$H_4$ are the gains of the feedback circuit.

From the transfer models shown in Figure 4b and Figure 5b, the conventional and proposed transfer functions of the feedback circuit are expressed as follows:

$$\mathrm{Conventional}:\frac{v_{d2}}{v_{in}}=\frac{A}{1+A{A}_1{H}_1+A{A}_1{A}_2{H}_2},$$

(1)

$$\mathrm{Proposed}:\frac{v_{d4}}{v_{in}}=\frac{A}{1+A{A}_3{H}_3+{\displaystyle \frac{A{A}_3{A}_4{H}_3{H}_4}{1+A_3{H}_4}}}.$$

(2)

By comparing Equations (1) and (2), the difference in gain between the conventional and proposed TIAs can be expressed as the following equation:

$$\frac{H_1}{1+A_2{H}_2},$$

(3)

where, assume that $A_1=A_3$, $A_2=A_4$, $H_1=H_3$, and $H_2=H_4$. Therefore, because the input impedance of the RGC stage can be reduced by the value shown in the aforementioned equations, the frequency of the proposed TIA can be extended compared with the conventional TIA circuit.

Figure 6 shows the small-signal equivalent circuit for transimpedance gain and cutoff frequency calculation. From this small-signal analysis, the transimpedance gain and cutoff frequency of each TIA are expressed as follows:

$$\mathrm{Conventional}:Z_t\left(0\right)\approx -\frac{g_{m1}{R}_1\left(R_{f1}\left|\right|R_{f2}\right)}{1+g_{m1}\left(R_{f1}\left|\right|R_{f2}\right)}A{A}_1{A}_2,$$

(4)

$$\mathrm{Conventional}:f_c\approx \frac{\left(g_{m1}+{\displaystyle \frac{A_1{A}_2}{R_{f1}\left|\right|R_{f2}}}\right)\left(1+g_{m2}{R}_2\right)}{2\pi C_{pd}},$$

(5)

$$\mathrm{Proposed}:Z_t\left(0\right)\approx -\frac{g_{m3}{R}_3\left({\displaystyle \frac{R_{f3}}{1+R_{f4}}}\right)}{1+g_{m3}\left({\displaystyle \frac{R_{f3}}{1+R_{f4}}}\right)}A{A}_3{A}_4,$$

(6)

$$\mathrm{Proposed}:f_c\approx \frac{\left(g_{m3}+{\displaystyle \frac{R_{f3}}{1+R_{f4}}}{A}_3{A}_4\right)\left(1+g_{m4}{R}_4\right)}{2\pi C_{pd}},$$

(7)

where $g_{m1}$–$g_{m4}$ are the transconductances of MOS transistors MN${}_1$–MN${}_4$, respectively, $C_{pd}$ is the equivalent capacitance of the photodiode, $R_{f1}$–$R_{f4}$ are the feedback resistances in the feedback circuits $H_1$–$H_4$, respectively.

Figure 7 depicts the normalized frequency response, assuming that $A={\displaystyle \frac{1}{s+1}}$, $A_1=A_2=A_3=A_4={\displaystyle \frac{1}{s+2}}$, and $H_1=H_2=H_3=H_4=1$. The figure shows that the cutoff frequency of the proposed TIA can be expanded compared with that of the conventional TIA.

3. Post-Layout Simulation Results

Figure 8 shows the full design of the TIA circuit, as well as the chip layout of the system implemented in a TSMC 65 nm general purpose CMOS process. The first block is the proposed TIA with a local feedback circuit, after which is a post amplifier (PA), required to convert a single-ended input to differential signals. To apply inductive peaking technique for bandwidth enhancement, a center-tapped spiral inductor was used at the drains of the PA stage. Finally, a high-speed unity gain open-drain output buffer was implemented to minimize the impact of directly driving 50 $\mathsf{\Omega }$ loads at the differential output of the amplifier.

In the first stage, TIA core is designed to wide frequency range and the 100 fF input parasitic capacitance caused by photodiode has been considered. To aim maximum output amplitude when the input DC bias voltage is 0.4 V, the aspect ratio of transistors M${}_1$ and M${}_2$ is set as W/L = 2 $\mathsf{\mu }$m/65 nm, finger = 16. Transistors M${}_3$ and M${}_4$ which is worked as a common drain amplifier correspond to the amplifier stages $A_3$ and $A_4$ shown in Figure 5, respectively. The transistor M${}_5$ is also a common drain amplifer. The aspect ratio of transistors M${}_3$–M${}_5$ is the same as M${}_1$ and M${}_2$. As will be described later in this section, the increasing of the input referred noise depends on the value of feedback resistor. Therefore, careful resistor values (300 $\mathsf{\Omega }$) were applied with due consideration of the noise environment. The dummy TIA that has the same circuit as the TIA core, provides a path signal to the PA, and balances the DC voltages at both the inputs of the PA stage.

In the second stage, PA is design as an inductively-peaked differential pair. The shunt inductive peaking is derived from the inductors placed in series with the drain resistors. The output swing is chosen to be 200 mV${}_{\mathrm{pp}}$. For the PA stage designing, an optimal inductance of 2.5 nH was used as trade-off between the bandwidth enhancement in the frequency response and chip area. The center tapped inductor was also chosen from the point of view of chip area. Final stage is the differential output amplifier to drive the 50 $\mathsf{\Omega }$ load. The MOS transistors M${}_6$–M${}_{13}$ is designed as W/L = 6 $\mathsf{\mu }$m/90 nm, finger = 16, to be able to drive the output stage.

The transimpedance gain and the current dissipation of each stage are summarized in Figure 8. Summing the gain contribution of each optical receiver; TIA, PA, and 50 $\mathsf{\Omega }$ buffer, an transimpedance gain is 46 dB$\mathsf{\Omega }$, and power dissipation is 23.9 mW (=23.9 mA × 1.0 V).

A TIA as shown in Figure 9 was implemented to evaluate its performance. The occupied layout area with I/O and DC pads was 670 $\mathsf{\mu }$m × 580 $\mathsf{\mu }$m, and the total active area of the proposed TIA was 366 $\mathsf{\mu }$m × 225 $\mathsf{\mu }$m.

Figure 10 shows the post-layout frequency response of the proposed TIA. The simulation results indicated the differential transimpedance gain was about 46 dB$\mathsf{\Omega }$ and the −3 dB bandwidth was greater than 11.4 GHz while consuming 23.9 mW of DC power. The measured results are described in Appendix A. To confirm the 2-port S-parameters, a simple function test was carried out using vector network analyzer. The resulting power dissipation was about 26 mW.

From the aforementioned results,

Table 1. Cutoff frequency and current dissipation comparison of TIA.

	Current Dissipation	Cutoff Frequency	FoM (GHz/mA)
	in TIA Core (mA)	with PA and 50 $\mathbf{\Omega }$ Buffer (GHz)
RGC TIA	8.6	6.1	0.71
Conventional TIA	10.1	10.3	1.09
Proposed TIA	10.3	11.4	1.11

summarizes the comparison of the current dissipation and cutoff frequency. Hence, the proposed TIA has a high frequency characteristic while suppressing increases in current dissipation.

Figure 11 indicates the equivalent input noise current spectral density. From this figure, we find that the average value is 46.6 $\mathrm{pA}/\sqrt{\mathrm{Hz}}$ on ${10}^7$–$11.4\times {10}^9$ Hz. Based on the noise equivalent model in [11], the simplified noise equivalent circuit of the proposed TIA is shown in Figure 12, where $C_{tot}=C_{pd}+C_{ESD}+C_{pad}+C_{gs2}+C_{sb1}$. From this analysis model, the equivalent noise current spectral density is approximately given by

$$\begin{array}{cc}\hfill \overline{i_{eq}^2}\approx & \overline{i_{n,R_{S1}}^2}+\overline{i_{n,R_{d1}}^2}+{\displaystyle \frac{\left({\displaystyle \frac{1}{R_{s1}}}+{\omega }^2{C}_{tot}^2\right)}{\left(g_{m2}+{\displaystyle \frac{1}{R_{s2}}}\right)}}\left(\overline{i_{n,d2}^2}+\overline{i_{n,R_{d2}}^2}\right)+{\displaystyle \frac{{\omega }^2{(C_{gs1}+C_{gd2})}^2}{g_{m1}^2}}\left(\overline{i_{n,d1}^2}+\overline{i_{n,R_{d1}}^2}\right)\hfill \\ \hfill & \hfill :\mathrm{RGC}\mathrm{section}\\ \hfill & +\overline{i_{n,R_{f1}}^2}+\overline{i_{n,d3}^2}+\overline{i_{n,d4}^2}+\overline{i_{n,R_{f2}}^2}:\mathrm{feedback}\mathrm{section}\hfill \\ \hfill & +\overline{i_{e{q}_{CD}}^2}+\overline{i_{n,R_{d1}}^2}:\mathrm{CD}\mathrm{section}.\hfill \end{array}$$

(8)

As shown in the aforementioned equation, we find that the input referred noise increases by adding the feedback section. Hence, we summarize that the value setting of the feedback resistor is relatively more important for this TIA design. The noise increasing is also suggested in post-layout simulation results as shown in Figure 11.

Table 2. Performance summary and comparison with other TIA works.

Reference	[12] (2014)	[13] (2015)	[14] (2016)
CMOS Technology	65 nm	65 nm	65 nm
Topology	Inverter	Inverter	Inverter
Supply Voltage	1.0 V	1.2 V	2.4 V
Transimpedance Gain (dB$\mathsf{\Omega }$)	78	51–73	51
Bandwidth (GHz)	11	0.55	8–12
${\mathrm{C}}_{\mathrm{pd}}$ (fF)	380	1400	70
Power Dissipation (mW)	45.3	(4.8) *	(0.26) *
Input-Referred Noise ($\mathrm{pA}/\sqrt{\mathrm{Hz}}$)	(3.9 $\mathsf{\mu }{\mathrm{A}}_{\mathrm{rms}})$	3.4	–
Chip Area (mm${}^2$)	0.75	(0.006) **	–
Results	Measured	Post-layout	Measured
Reference	[2](2018)	[15](2019)	This Work(2022)
CMOS Technology	65 nm	65 nm	65 nm
Topology	Current reuse	Current reuse	multistage feedback
	RGC	RGC	RGC
Supply Voltage	1.0 V	1.0 V	1.0 V
Transimpedance Gain (dB$\mathsf{\Omega }$)	65.8	43	46
Bandwidth (GHz)	11.0	10.3	11.4
${\mathrm{C}}_{\mathrm{pd}}$ (fF)	200	–	100
Power Dissipation (mW)	66	(4.3) *	23.9
			(Measured: 26) ***
Input-Referred Noise ($\mathrm{pA}/\sqrt{\mathrm{Hz}}$)	30	–	46.6
Chip Area (mm${}^2$)	0.25	–	0.39
Results	Measured	SPICE	Post-layout

* Buffer power exempted, ** Active area only, *** See, Appendix A.

compares the performance of the proposed TIA with those of recently published TIAs. The proposed method is superior in term of power dissipation compared with other TIAs implemented using the same 65 nm CMOS technology.

4. Conclusions

To enhance the frequency band of the transimpedance amplifier, we present a local feedback technique in this paper. The numerical analysis showed that the cutoff frequency of the proposed TIA is about 1.3 times wider compared with that of the conventional overall feedback TIA. The post-layout simulation results of the proposed wide-band TIA with a local feedback technique exhibits the following: a −3 dB frequency of 11.4 GHz and a transimpedance gain of 46 dB$\mathsf{\Omega }$. The TIA also has a lower power dissipation of 23.9 mW. Thus, the post-layout simulation results indicate that the local feedback technique is useful for optical TIA applications.