An Overview of Systolic Arrays for Forward and Inverse Discrete Sine Transforms and Their Exploitation in View of an Improved Approach

Abstract

This paper aims to present a unified overview of the main Very Large-Scale Integration (VLSI) implementation solutions of forward and inverse discrete sine transforms using systolic arrays. The main features of the most important solutions to implement the forward and inverse discrete sine transform (DST) using systolic arrays are presented. One of the central ideas presented in the paper is to emphasize the advantages of using regular and modular systolic array computational structures such as cyclic convolution, circular correlation, and pseudo-band correlation in the VLSI implementation of these transforms. The use of such computational structures leads to architectures well adapted to the features of VLSI technologies, with an efficient use of the hardware structures and a reduced I/O cost that helps avoiding the so-called I/O bottleneck. With the techniques presented in this review, we have developed a new VLSI implementation of the DST using systolic arrays that allow efficient hardware implementation with reduced complexity while maintaining high-speed performances. Using a new restructuring input sequence, we have been able to efficiently reformulate the computation of the forward DST transform into a special computational structure using eight short quasi-cycle convolutions that can be computed with low complexity and where some of the coefficients are identical. This leads to a hardware structure with high throughput. The new restructuring sequence is the use of the input samples in a natural order as opposed to previous solutions, leading to a significant reduction of the hardware complexity in the pre-processing stage due to avoiding a permutation stage to reverse the order. Moreover, the proposed VLSI architecture allows an efficient incorporation of the obfuscation technique with very low overheads.

1. Introduction

In the last decades, an increasing amount of information has been stored in digital form [1]. Further, a major shift from written content to image and video content has been observed. With the spectacular development and ubiquity of mobile devices, the volume of digital visual data has exploded, with more photos taken in the last decade than in the entire history until mid-2011 [2].

Advances in the fields of digital signal processing and VLSI computational architectures have led to a several orders of magnitude growth in digital visual content production and consumption. Subsequently, the growth of digital visual content has incentivized technological innovation and the search for efficient solutions in video and image compression techniques. The development of mobile devices and other resource-limited devices has led to new design requirements characterized by a low hardware complexity with tight energy efficiency constraints.

The discrete sine (DST) and cosine (DCT) transforms [3,4] are important discrete transforms that are used in many signal processing applications, especially in speech and image transform coding [5,6]. These transforms are good approximations to the statistically optimal Karhunen–Loeve transform (KLT). The choice for the DCT or DST depends on the statistical properties of the input signal. While the DCT provides better results for strongly correlated signals, the DST provides a lower bit rate for weakly correlated input signals [5]. Both the DCT and DST have some other important applications in digital signal processing, telecommunications, and cryptography. The DCT is also used in wireless communications [7,8,9], digital watermarking [10,11], and analysis of hyperspectral data [12,13]. The DST has additional important applications such as Lossless Image and Intra-Frame Compression [14], image interpolation [15], video steganography [16], and graph filtering [17]. There are some other applications as in [18,19,20], where both the DCT and DST are necessary.

For an efficient VLSI implementation, especially in the case of using systolic arrays, it is important to analyze and to consider the data flow within the algorithm’s signal flow graph (SFG). In this sense, the present paper offers a unified view of the systolic array implementations for the forward and inverse DST in such a manner that regular and modular computational structures are emphasized. In the literature, certain regular and modular computational structures, such as cyclic convolution and circular correlation, have been used for efficient VLSI implementations employing the paradigm of systolic array architectures [21,22,23,24,25,26,27,28,29,30,31,32,33,34] due to important advantages over others, especially for efficient input/output and data transfer operations, for interconnection locality, and for an efficient use of the hardware structure.

The most significant systolic array implementations of DST are presented in the papers from [35,36,37,38,39,40,41].

In [35], the DST algorithm is decomposed into two matrix-vector products that are mapped to linear systolic arrays. It is based on an even–odd decomposition of the computation of the output sequences, but the two equations have no specific structures. This is one of the first systolic array implementations of the DST and does not present regular and modular structures; therefore, it lacks the advantages of the VLSI implementations based on regular and modular computational structures (as in the case of cycle convolution or circular correlation) that lead to an efficient implementation (a regular and local interconnection structure, an efficient implementation of pipelining, reducing of the I/O bottleneck, etc.).

In [36], we have another systolic array implementation of the DST. It is based on a decomposition of the DST algorithm into two cycle convolutions that can be computed in parallel. It has some distinctive features: it uses small ROMs instead of multipliers, resulting in a memory-based implementation of the DST; the input and output sequences can be loaded and extracted from the I/O channels placed at the two extreme ends of the linear array and are used in as many processing elements as possible, thus avoiding the I/O bottleneck. Due to its modularity, regularity, and local interconnectivity, the proposed architecture is well suited for a VLSI implementation. Further, due to the use of pipelining and parallelism, high-speed performances can be obtained.

Unfortunately, the level of parallelism is reduced (only two), thus it cannot allow an efficient integration of the hardware security techniques and cannot use a further improvement of the speed performances and a reduction of the hardware complexity using the Signed Digit (SD) representation as in our approach.

Further, in [36], we have a systolic array implementation of the IDST based on a decomposition of the IDST algorithm into two cycle convolutions. It has the same advantages and drawbacks as the systolic array implementation of the DST presented in the same paper.

In [37], we have another systolic array implementation of the DST based on a decomposition of the DST algorithm into four short cycle convolutions. The four cycle convolutions have been mapped to a linear systolic array where the four multipliers from each processing element have been implemented using two dual-port memories. It has all of the advantages and drawbacks of the solution proposed in [36], but with a reduced hardware complexity and an increased level of parallelism.

In [38], we have another systolic array implementation of the IDST that uses another modular and regular computational structure called pseudo-band correlation. It was shown that this special computational structure can be efficiently mapped on a single systolic array with a low hardware complexity. It has all of the advantages of the systolic arrays based on the cycle convolution structures presented in [36,37] such as low I/O cost, high-speed performances due to two-level pipelining, high regularity, modularity, and interconnection locality, being well suited for a VLSI implementation. The hardware complexity has been reduced, although with a lower degree of parallelism and, implicitly, throughput.

In [39], another systolic array implementation of the IDST based on two quasi-band correlation structures that can be used for power of two length transforms is presented. It was shown that using this regular and modular computational structure, one can obtain two systolic arrays with length $N/2$ and $N/4$ with a reduced hardware complexity. This structure has all of the advantages of the systolic arrays based on cycle convolutions and circular correlations already mentioned.

As opposed to our solution, none of the presented solutions have investigated the potentially efficient use of SD representations to further improve the speed performances and reduce the hardware complexity of the computational structures. Another drawback is that the previous solutions do not allow an efficient incorporation of the hardware security techniques with low overheads. Moreover, in our solution, the degree of parallelism has been increased to eight, leading to an increased speed performance.

Current trends in the market make it more and more necessary to integrate different IP macro-cells produced by global vendors [42,43]. To maintain a competitive edge, it is frequently important to ensure protection from counterfeit, piracy, and other intellectual property threats in the integrated circuits business, resulting in the considerable growth of the hardware security field. The main scope is to protect the designs from piracy, reverse engineering or malicious alteration resulting in Trojan threats [44].

One of the most efficient solutions for this problem is the obfuscation technique [44,45,46,47,48,49]. In [49], Koteshwara proposes three types of obfuscation: the fixed obfuscation, the time-varying obfuscation, and the dynamic obfuscation. The principle of obfuscation is that the protected system works correctly only when the correct key is applied. This is achieved using multiplexers with multiple signals generated at their inputs, both correct and obfuscated signals. The correct signal will be generated only for the correct key, and an obfuscated signal will be selected otherwise.

In our paper, we have obtained an efficient VLSI implementation of the DST using systolic arrays that allows a parallel implementation and can incorporate in an efficient way an optimal SD representation. Further, we propose incorporating the obfuscation technique with very low overheads that is very important for common goods devices that are produced on a large scale. None of these aspects have not been investigated until now.

The main contributions of the proposed solutions are as follows:

• We have appropriately reformulated the DST algorithm such that an efficient VLSI implementation using systolic arrays with an optimal SD representation integration has been obtained. Due to the efficient use of the SD representation, a significant improvement of the speed performances and the hardware complexity has been achieved.
• We have split the computation of the DST algorithm into eight regular and modular computational structures that can be efficiently mapped on linear systolic arrays and can be computed in parallel, considerably improving the throughput of the VLSI architecture.
• Moreover, due to the appropriate reformulation of the DST algorithm, we have efficiently incorporated the hardware security techniques with low overheads. This is very important for common goods devices.

The rest of the paper is organized as follows: in Section 2 we present the main solutions for the systolic implementation of forward and inverse DST in a unified manner. In Section 3, we propose a new systolic implementation of the forward DST with reduced hardware complexity and good speed performances. In Section 4, we present the conclusions, emphasizing the main contributions, as well as a future perspective.

2. Different Solutions to Implement the Forward and Inverse DST Using Systolic Arrays

In this paper, we present a unified view of the main systolic array implementations of forward and inverse discrete sine transforms found in the literature. Systolic arrays are well suited for VLSI implementation. The systolic array paradigm overcomes some of the drawbacks of VLSI technology, such as the area-consuming interconnection nets that introduce high delays and the very high design costs, and tries to exploit the advantages of VLSI technology stemming from the fact that a high number of components can be integrated on the same chip.

Thus, systolic arrays use a local and regular interconnection structure, as well as modular and regular blocks, which leads to the reduction of the design cost and makes them well suited for an efficient implementation. Further, they extensively use concurrency such as pipelining and parallelism to achieve high-speed performances. They also reduce the I/O cost through the reuse of the input data in as many processing elements as possible.

Not all DSP algorithms are suited for an efficient implementation using systolic arrays. Systolic algorithms have some distinctive features such as [1]:

• The processing elements have a simple function that does not change over time;
• There are a few types of processing elements;
• The data flow in the algorithm are simple and regular;
• The data communications in the algorithm have a locality feature.

Therefore, to obtain an efficient VLSI implementation using systolic arrays, it is necessary to develop innovative algorithms suited for such an implementation or to appropriately restructure the existing ones. It is interesting to note here that, in developing efficient systolic algorithms, it is more important to reduce the communication complexity than the arithmetic one. Thus, to develop efficient systolic algorithms, it is very important to analyze and take into consideration the data flow in the algorithm.

One interesting solution is to use some special computational structures such as cyclic convolution and circular correlation that have shown several advantages when used for a hardware implementation using the VLSI technology. They can be efficiently used for the VLSI implementation of discrete transforms using systolic arrays [21,22,23,24,25] or distributed arithmetics [26,27]. We have extended this approach to some other regular and modular computational structures such as the band correlation structure and the pseudo-band correlation structure.

As will be seen below, all of the presented solutions for systolic array implementations of these transforms are based on the so-called odd–even decompositions of the computation of the output sequence. The solution presented in [35] offers a direct implementation of this decomposition, but all of the other ones use restructuring methods that transform the computation of the forward and inverse transforms into regular and modular computational structures such as cyclic convolution, circular correlation, pseudo-cyclic convolution, pseudo-circular correlation, or pseudo-band correlation structures.

Using these ideas, we have proposed at the end of this section a new and interesting solution for a systolic array implementation of the forward DST that offers a good trade-off between hardware complexity, power consumption, and speed performances. Moreover, the proposed systolic array offers an efficient implementation of the hardware security solution called obfuscation.

2.1. A Systolic VLSI Algorithm Based on a Direct Decomposition of Even and Odd Output Sequences

For a real input sequence $x(i):i=0, 1, \dots , N-1$, the 1-D forward Discrete Sine Transform (DST) is defined as:

$$Y\left(k\right)=\sqrt{\frac{2}{N}}\cdot {{\displaystyle \sum }}_{i=0}^{N-1}x\left(i\right)\cdot \mathit{sin}[\left(2i+1\right)k\alpha ],$$

(1)

for $k=1, 2, \dots , N$, where

$$\alpha =\frac{\pi }{2N}$$

(2)

In the following, the constant coefficient $\sqrt{\frac{2}{N}}$ has been dropped from the definition of the 1-D DST as it can be added at the end of the VLSI array using a multiplier to scale the output sequence with this constant.

In [35], the even-and odd-numbered output samples can be computed in parallel as follows:

$$Y\left(2k\right)={{\displaystyle \sum }}_{i=0}^{N/2-1}[x\left(i+1\right)-x\left(N-i\right)]S_{2k}^{2i+1},$$

(3)

$$Y\left(2k-1\right)={\displaystyle \sum }_{i=0}^{N/2-1}[x\left(i+1\right)-x\left(N-i\right)]S_{2k-1}^{2i+1}$$

(4)

with:

$$S_k^{2i+1}=\mathit{sin}[\left(2i+1\right)k\alpha ]$$

(5)

For $N=8$ we have:

$$\left[\begin{array}{c}Y\left(1\right)\\ Y\left(3\right)\\ Y\left(5\right)\\ Y\left(7\right)\end{array}\right]=\left[\begin{array}{cccc}\mathit{sin}(\alpha )& \mathit{sin}(3\alpha )& \mathit{cos}(3\alpha )& \mathit{cos}(\alpha )\\ \mathit{sin}(3\alpha )& \mathit{cos}(\alpha )& \mathit{sin}(\alpha )& -\mathit{cos}(3\alpha )\\ \mathit{cos}(3\alpha )& \mathit{sin}(\alpha )& -\mathit{cos}(\alpha )& \mathit{sin}(3\alpha )\\ \mathit{cos}(\alpha )& -\mathit{cos}(3\alpha )& \mathit{sin}(3\alpha )& -\mathit{sin}(\alpha )\end{array}\right]\cdot \left[\begin{array}{c}x\left(1\right)+x\left(8\right)\\ x\left(2\right)+x\left(7\right)\\ x\left(3\right)+x\left(6\right)\\ x\left(4\right)+x\left(5\right)\end{array}\right]$$

(6)

$$\left[\begin{array}{c}Y\left(2\right)\\ Y\left(4\right)\\ Y\left(6\right)\\ Y\left(8\right)\end{array}\right]=\left[\begin{array}{cccc}\mathit{sin}(2\alpha )& \mathit{cos}(2\alpha )& \mathit{cos}(2\alpha )& \mathit{sin}(2\alpha )\\ \mathit{cos}(4\alpha )& \mathit{cos}(4\alpha )& -\mathit{cos}(4\alpha )& -\mathit{cos}(4\alpha )\\ \mathit{cos}(2\alpha )& -\mathit{sin}(2\alpha )& -\mathit{sin}(2\alpha )& \mathit{cos}(2\alpha )\\ 1& -1& 1& -1\end{array}\right]\cdot \left[\begin{array}{c}x\left(1\right)-x\left(8\right)\\ x\left(2\right)-x\left(7\right)\\ x\left(3\right)-x\left(6\right)\\ x\left(4\right)-x\left(5\right)\end{array}\right]$$

(7)

We have obtained an algorithm based on the even–odd decomposition of the computation of the output sequences, but the two equations have no specific structures.

As can be seen in [35], Equations (6) and (7) can be mapped to the same linear systolic array, but the input and output sequences are loaded and extracted from each processing element, leading to a high number of channels and a high I/O cost. The proposed structure is not that well suited for a VLSI implementation compared to the case of using regular and modular computational structures.

2.2. A Systolic VLSI Algorithm for the Forward DST Based on Two Cycle Convolutions

To illustrate the approach presented in [36], we will consider the example of a DST with length $N=7$. If the length N of the transforms is a prime number, we can reformulate Equation (1) as follows:

We introduce two new input sequences, defined as:

$$x_a\left(N-1\right)=x\left(N-1\right)$$

(8)

$$x_a\left(i\right)=x\left(i\right)+x_a\left(i+1\right)$$

(9)

for $i=\left(N-2\right), \dots , 1, 0$, and

$$x_b\left(N-1\right)=-x\left(N-1\right)$$

(10)

$$x_b\left(i\right)={(-1)}^{i+1}x\left(i\right)-x_b\left(i+1\right)$$

(11)

for $i=\left(N-2\right), \dots , 1, 0$

Using appropriate index mappings for the new sequences, we can decompose the computation of the DST into two half-length cyclic convolutions with the same structure:

$$\left[\begin{array}{c}{T}_a\left(3\right)\\ T_a\left(2\right)\\ T_a\left(1\right)\end{array}\right]=\left[\begin{array}{ccc}{x}_a\left(1\right)+x_a\left(6\right)& x_a\left(3\right)+x_a\left(4\right)& x_a\left(2\right)+x_a\left(5\right)\\ x_a\left(2\right)+x_a\left(5\right)& x_a\left(1\right)+x_a\left(6\right)& x_a\left(3\right)+x_a\left(4\right)\\ x_a\left(3\right)+x_a\left(4\right)& x_a\left(2\right)+x_a\left(5\right)& x_a\left(1\right)+x_a\left(6\right)\end{array}\right]\cdot \left[\begin{array}{c}\mathit{cos}(12\alpha )\\ \mathit{cos}(8\alpha )\\ \mathit{cos}(4\alpha )\end{array}\right]$$

(12)

$$\left[\begin{array}{c}{T}_b\left(3\right)\\ T_b\left(2\right)\\ T_b\left(1\right)\end{array}\right]=\left[\begin{array}{ccc}{x}_b\left(1\right)+x_b\left(6\right)& x_b\left(3\right)+x_b\left(4\right)& x_b\left(2\right)+x_b\left(5\right)\\ x_b\left(2\right)+x_b\left(5\right)& x_b\left(1\right)+x_b\left(6\right)& x_b\left(3\right)+x_b\left(4\right)\\ x_b\left(3\right)+x_b\left(4\right)& x_b\left(2\right)+x_b\left(5\right)& x_b\left(1\right)+x_b\left(6\right)\end{array}\right]\cdot \left[\begin{array}{c}\mathit{cos}(12\alpha )\\ \mathit{cos}(8\alpha )\\ \mathit{cos}(4\alpha )\end{array}\right]$$

(13)

Equations (12) and (13) have specific structural properties that can be exploited to significantly increase the efficiency of the VLSI implementation, as shown in [36]. Thus, the operands $\mathit{cos}\left(k·2\alpha \right)$, with $k=1, \dots , \left(N-1\right)/2$ are time invariant and are allocated to the $\left(N-1\right)/2$ processing elements, such that one operand in each multiplier is fixed, as shown in [36] (Figure 1). Further, in the matrix of (12) and (13), all of the principal diagonal elements and all of the elements along any line parallel to the principal diagonal are identical. This feature renders the input data elements to be efficiently used in all of the processing elements, thus providing a significant reduction in the I/O cost.

The output sequence for the DST is computed using

$$\left[\begin{array}{c}Y\left(6\right)\\ Y\left(4\right)\\ Y\left(2\right)\end{array}\right]=\left[\begin{array}{c}\left[2T_a\left(3\right)+x_a\left(0\right)\right]·sin\left(6\alpha \right)\\ \left[2T_a\left(2\right)+x_a\left(0\right)\right]·sin\left(4\alpha \right)\\ \left[2T_a\left(1\right)+x_a\left(0\right)\right]·sin\left(2\alpha \right)\end{array}\right]$$

(14)

$$\left[\begin{array}{c}Y\left(1\right)\\ Y\left(3\right)\\ Y\left(5\right)\end{array}\right]=\left[\begin{array}{c}\left[2T_b\left(4\right)+x_b\left(0\right)\right]·cos\left(8\alpha \right)\\ \left[2T_b\left(5\right)+x_b\left(0\right)\right]·cos\left(10\alpha \right)\\ \left[2T_b\left(6\right)+x_b\left(0\right)\right]·cos\left(12\alpha \right)\end{array}\right]$$

(15)

and

$$Y\left(7\right)=-\left[x_b\left(0\right)+2{\displaystyle \sum }_{i=1}^3\left[x_b\left(\psi \left(i\right)\right)+x_b\left(\varphi \left(i\right)\right)\right]\right]$$

(16)

The two convolutions given by (12) and (13) can be concurrently computed, leading to an increased throughput, and have the same length and computational structures. Moreover, the two equations have a form that allows an efficient use of memory-based implementation techniques.

As shown in [36], one can obtain an efficient linear systolic array using a data-dependent graph-based design procedure [50] and the tag control scheme [51]. It has some distinctive features: since one operand in each processing element is constant, we can replace multipliers with small ROMs, resulting in an efficient memory-based implementation technique. The input and output sequences can be loaded and extracted from the I/O channels placed at the two extreme ends of the linear array and used in as many processing elements as possible to avoid the I/O bottleneck. Due to its modularity, regularity, and locality, the proposed architecture is well suited for a VLSI implementation. Further, due to the use of pipelining and parallelism, high-speed performances can be obtained.

2.3. A VLSI Algorithm for the Inverse DST Based on Two Cyclic Convolutions

The output sequence $\left\{x\left(i\right): i=1, \dots , N\right\}$ for the inverse discrete sine transform (IDST) is defined as:

$$x\left(k\right)={\displaystyle \sum }_{i=1}^{N}Y\left(i\right)·sin\left[\left(2k+1\right)i\alpha \right]$$

(17)

for $k=0, 1, \dots ., N-1$, where $\alpha =\pi /2N$.

As it has been shown in [36], if the transform length is a prime number greater than 2, the IDST transform can be concurrently computed using the following computational equations:

$$x\left(k\right)=A\left(k\right)-{(-1)}^{k}B\left(k\right)+{(-1)}^{k}Y\left(N\right)$$

(18)

$$x\left(N-k\right)=-A\left(k-1\right)+{(-1)}^{k}B\left(k-1\right)-{(-1)}^{k}Y\left(N\right)$$

(19)

for $k=1, \dots , \left(N-1\right)/2$, where the auxiliary sequences $\left\{A\left(i\right): i=0, \dots , \left(N-1\right)/2\right\}$ and $\left\{B\left(i\right): i=0, \dots , \left(N-1\right)/2\right\}$ are computed recursively as follows:

$$\begin{gathered} A\left(0\right)={\displaystyle \sum }_{k=1}^{\left(N-1\right)/2}{Y}_a\left(\psi \left(k\right)\right) \\ A\left(k\right)=2T_a\left(k\right)+A\left(k-1\right) \end{gathered}$$

(20)

$$\begin{gathered} B\left(0\right)={\displaystyle \sum }_{k=1}^{\left(N-1\right)/2}{Y}_b\left(\phi \left(k\right)\right) \\ B\left(k\right)=2T_b\left(k\right)-B\left(k-1\right) \end{gathered}$$

(21)

for $k=1, \dots , \left(N-1\right)/2$,

The following auxiliary input sequences have been introduced:

$$Y_a\left(k\right)=Y\left(\zeta \left(k\right)\right)·sin\left(2k\alpha \right)$$

(22)

$$Y_b\left(k\right)=Y\left(\zeta \left(k\right)\right)·cos\left(2k\alpha \right)$$

(23)

To illustrate the approach presented in [36], we consider an example IDST with length $N=7$.

We have used two new auxiliary sequences $\left\{T_a\left(k\right): k=1, \dots , \left(N-1\right)/2\right\}$ and $\left\{T_b\left(k\right): k=1, \dots , \left(N-1\right)/2\right\}$ that can be computed in parallel as follows:

$$\left[\begin{array}{c}{T}_a\left(3\right)\\ T_a\left(2\right)\\ T_a\left(1\right)\end{array}\right]=\left[\begin{array}{ccc}{Y}_a\left(1\right)& Y_a\left(3\right)& Y_a\left(2\right)\\ Y_a\left(2\right)& Y_a\left(1\right)& Y_a\left(3\right)\\ Y_a\left(3\right)& Y_a\left(2\right)& Y_a\left(1\right)\end{array}\right]\cdot \left[\begin{array}{c}\mathit{cos}(12\alpha )\\ \mathit{cos}(8\alpha )\\ \mathit{cos}(4\alpha )\end{array}\right]$$

(24)

$$\left[\begin{array}{c}{T}_b\left(3\right)\\ T_b\left(2\right)\\ T_b\left(1\right)\end{array}\right]=\left[\begin{array}{ccc}{Y}_b\left(6\right)& Y_b\left(4\right)& Y_b\left(5\right)\\ Y_b\left(5\right)& Y_b\left(6\right)& Y_b\left(4\right)\\ Y_b\left(4\right)& Y_b\left(5\right)& Y_b\left(6\right)\end{array}\right]\cdot \left[\begin{array}{c}\mathit{cos}(12\alpha )\\ \mathit{cos}(8\alpha )\\ \mathit{cos}(4\alpha )\end{array}\right]$$

(25)

where

$$Y_a\left(k\right)=Y\left(\zeta \left(k\right)\right)·sin\left(2k\alpha \right)$$

(26)

$$Y_b\left(k\right)=Y\left(\zeta \left(k\right)\right)·cos\left(2k\alpha \right)$$

(27)

$k=1, 2, \dots , 6$.

As in the case of the forward DST, the operands $\mathit{cos}(k\cdot 2\alpha )$ are fixed and the same for any given $k$, which allows an efficient use of the memory-based implementation techniques. The relations used in (22) and (23) represent cyclic convolutions having similar forms and the same length.

Finally, the output sequence can be computed as follows:

$$\left[\begin{array}{c}x\left(0\right)\\ x\left(1\right)\\ \begin{array}{c}x\left(2\right)\\ x\left(3\right)\end{array}\end{array}\right]=\left[\begin{array}{c}\begin{array}{c}A\left(0\right)+Y\left(7\right)\\ A\left(1\right)-Y\left(7\right)\\ A\left(2\right)+Y\left(7\right)\end{array}\\ A\left(3\right)-Y\left(7\right)\end{array}\right]-\left[\begin{array}{c}\begin{array}{c}B\left(0\right)\\ -B\left(1\right)\\ \mathrm{B}(2)\end{array}\\ -B\left(3\right)\end{array}\right]$$

(28)

$$\left[\begin{array}{c}x\left(6\right)\\ x\left(5\right)\\ x\left(4\right)\end{array}\right]=-\left[\begin{array}{c}A\left(0\right)-Y\left(7\right)\\ A\left(1\right)+Y\left(7\right)\\ A\left(2\right)-Y\left(7\right)\end{array}\right]+\left[\begin{array}{c}-B\left(0\right)\\ B\left(1\right)\\ -\mathrm{B}(2)\end{array}\right]$$

(29)

As it has been shown in [36], the systolic arrays that can be obtained using an SFG-based design procedure have some distinctive features: input and output sequences can be loaded and extracted from I/O channels placed at the two extreme ends of the linear array and used in as many processing elements as possible, avoiding I/O bottleneck. Because one operand in each processing element is constant, an efficient application of memory-based implementation techniques that involve small ROMs can be used. Due to its modularity, regularity, and locality, the proposed architecture is well suited for a VLSI implementation. Further, due to the use of pipelining and parallelism, high-speed performances can be achieved.

2.4. A Systolic Algorithm for Forward DST Using Short Cyclic Convolutions

In [37], the following input restructuring sequence was introduced:

$$x_a\left(N-1\right)=x\left(N-1\right)$$

(30)

$$x_a\left(N-i\right)=x\left(N-i\right)-x_a\left(N-i+1\right)$$

(31)

for $i=2, \dots , N$.

Using this auxiliary input sequence together with an auxiliary output sequence $T\left(k\right)$, one can obtain an appropriate decomposition of the algorithm that uses cycle convolution forms.

The output sequence $\left\{Y\left(k\right):k=1, 2, \dots , N-1\right\}$ can be computed as follows:

$$Y\left(N\right)=x_a\left(0\right)$$

(32)

$$Y\left(k\right)=\left[x_a\left(0\right)+2T\left(k\right)\cdot \mathit{sin}[k\alpha \right]]$$

(33)

for $k=1, \dots , N-1$

The new auxiliary output sequence $\left\{T\left(k\right):k=1, 2, \dots , N-1\right\}$ can be computed as follows:

$$P\left(k\right)=T\left(2k\right)={\displaystyle \sum }_{i=1}^{\left(N-1\right)/2}[x_a\left(2i\right)+x_a\left(N-2i\right)\left]\cdot \mathit{cos}[2\psi \left(k,i\right)k\alpha \right]$$

(34)

$$Q\left(k\right)=T\left(N-2k\right)={\displaystyle \sum }_{i=1}^{\left(N-1\right)/2}[x_a\left(2i\right)-x_a\left(N-2i\right)\left]\cdot \mathit{cos}[2\psi \left(k,i\right)k\alpha \right]$$

(35)

for $k=1, \dots , \left(N-1\right)/2$, where:

$$\psi \left(k,i\right)=\{\begin{array}{cc}{(2ki)}_N& if\hspace{1em}{(2ki)}_N\le \left(N-1\right)/2\\ N-{(2ki)}_N& if\hspace{1em}{(2ki)}_N>\left(N-1\right)/2\end{array}$$

(36)

If $N$ is a prime number, both Equations (34) and (35) can be converted into cycle convolution forms using the following index mappings:

$$i=\{\begin{array}{cc}{(g^{-m})}_N& if\hspace{1em}{(2ki)}_N\le \left(N-1\right)/2\\ N-{(g^{-m})}_N& if\hspace{1em}{(2ki)}_N>\left(N-1\right)/2\end{array}$$

(37)

$$k=\{\begin{array}{cc}{(g^l)}_N& if\hspace{1em}{(2ki)}_N\le \left(N-1\right)/2\\ N-{(g^l)}_N& if\hspace{1em}{(2ki)}_N>\left(N-1\right)/2\end{array}$$

(38)

where $g$ is a primitive root of unity.

For $N=13$, we can write Equations (34) and (35) in the following form:

$$\left[\begin{array}{c}T\left(2\right)\\ T\left(4\right)\\ T\left(6\right)\\ T\left(8\right)\\ T\left(10\right)\\ T\left(12\right)\end{array}\right]=\left[\begin{array}{cccccc}c\left(2\right)& c\left(4\right)& c\left(6\right)& c\left(5\right)& c\left(3\right)& c\left(1\right)\\ c\left(4\right)& c\left(5\right)& c\left(1\right)& c\left(3\right)& c\left(6\right)& c\left(2\right)\\ c\left(6\right)& c\left(1\right)& c\left(5\right)& c\left(2\right)& c\left(4\right)& c\left(3\right)\\ c\left(5\right)& c\left(3\right)& c\left(2\right)& c\left(6\right)& c\left(1\right)& c\left(4\right)\\ c\left(3\right)& c\left(6\right)& c\left(4\right)& c\left(1\right)& c\left(2\right)& c\left(5\right)\\ c\left(1\right)& c\left(2\right)& c\left(3\right)& c\left(4\right)& c\left(5\right)& c\left(6\right)\end{array}\right]·\left[\begin{array}{c}x\left(2\right)+x\left(11\right)\\ x\left(4\right)+x\left(9\right)\\ x\left(6\right)+x\left(7\right)\\ x\left(8\right)+x\left(5\right)\\ x\left(10\right)+x\left(3\right)\\ x\left(12\right)+x\left(1\right)\end{array}\right]$$

(39)

$$\left[\begin{array}{c}T\left(11\right)\\ T\left(9\right)\\ T\left(7\right)\\ T\left(5\right)\\ T\left(3\right)\\ T\left(1\right)\end{array}\right]=\left[\begin{array}{cccccc}c\left(2\right)& c\left(4\right)& c\left(6\right)& c\left(5\right)& c\left(3\right)& c\left(1\right)\\ c\left(4\right)& c\left(5\right)& c\left(1\right)& c\left(3\right)& c\left(6\right)& c\left(2\right)\\ c\left(6\right)& c\left(1\right)& c\left(5\right)& c\left(2\right)& c\left(4\right)& c\left(3\right)\\ c\left(5\right)& c\left(3\right)& c\left(2\right)& c\left(6\right)& c\left(1\right)& c\left(4\right)\\ c\left(3\right)& c\left(6\right)& c\left(4\right)& c\left(1\right)& c\left(2\right)& c\left(5\right)\\ c\left(1\right)& c\left(2\right)& c\left(3\right)& c\left(4\right)& c\left(5\right)& c\left(6\right)\end{array}\right]·\left[\begin{array}{c}x\left(2\right)-x\left(11\right)\\ x\left(4\right)-x\left(9\right)\\ x\left(6\right)-x\left(7\right)\\ x\left(8\right)-x\left(5\right)\\ x\left(10\right)-x\left(3\right)\\ x\left(12\right)-x\left(1\right)\end{array}\right]$$

(40)

Using the following index mappings:

$l$ and $m$	0	1	2	3	4	5
$I$	1	6	3	5	4	2
$K$	1	2	4	5	3	6

We can write (39) and (40) into cycle convolution forms. For the case where $N$ is a prime of the form $8K+5$, we can convert (39) and (40) into 4 cycle convolutions with an length equal of 3.

As it has been shown in [37], the 4 cycle convolutions can be mapped to a linear systolic array, where the 4 multipliers from each processing element have been implemented using two dual-port memories. It has all of the advantages of a systolic array based on a cycle convolution structure, such as a regular and modular hardware structure with local interconnections and a low I/O cost with input and output channels placed at the two extreme ends.

2.5. A New VLSI Algorithm for Inverse DST Using a Pseudo-Band Correlation

As it has been shown in [38], the output sequence of the inverse discrete sine transform (IDST) can be recursively computed using an auxiliary output sequence $\left\{T\left(k\right):k=1, 2, \dots , N-1\right\}$ as

$$x^{\prime }\left(0\right)=x\left(0\right)$$

(41)

$$x^{\prime }\left(k\right)={(-1)}^{k}T\left(k\right)-x^{\prime }\left(k-1\right)$$

(42)

for $k=1, \dots , \left(N-1\right)$, with

$$x\left(0\right)={\displaystyle \sum }_{i=1}^N{Y}_S\left(i\right)$$

(43)

where the output sequence is computed as follows:

$$x\left(k\right)={(-1)}^k{x}^{\prime }\left(k\right)$$

(44)

To illustrate the approach, we consider an example for the 1-D IDST with length $N=11$ and primitive root $g=2$.

The auxiliary output sequence $T\left(k\right)$ can be computed as follows:

$$\left[\begin{array}{c}T\left(2\right)\\ T\left(4\right)\\ T\left(8\right)\\ T\left(5\right)\\ T\left(10\right)\\ T\left(9\right)\\ T\left(7\right)\\ T\left(3\right)\\ T\left(6\right)\\ T\left(1\right)\end{array}\right]=\left[\begin{array}{ccccc}c\left(4\right)& c\left(8\right)& c\left(5\right)& c\left(10\right)& c\left(9\right)\\ c\left(8\right)& c\left(5\right)& c\left(10\right)& c\left(9\right)& c\left(7\right)\\ c\left(5\right)& c\left(10\right)& c\left(9\right)& c\left(7\right)& c\left(3\right)\\ c\left(10\right)& c\left(9\right)& c\left(7\right)& c\left(3\right)& c\left(6\right)\\ c\left(9\right)& c\left(7\right)& c\left(3\right)& c\left(6\right)& c\left(1\right)\\ c\left(7\right)& c\left(3\right)& c\left(6\right)& c\left(1\right)& c\left(2\right)\\ c\left(3\right)& c\left(6\right)& c\left(1\right)& c\left(2\right)& c\left(4\right)\\ c\left(6\right)& c\left(1\right)& c\left(2\right)& c\left(4\right)& c\left(8\right)\\ c\left(1\right)& c\left(2\right)& c\left(4\right)& c\left(8\right)& c\left(5\right)\\ c\left(2\right)& c\left(4\right)& c\left(8\right)& c\left(5\right)& c\left(10\right)\end{array}\right]·\left[\begin{array}{c}\pm \left[Y_S\left(2\right)\pm Y_S\left(9\right)\right]\\ \pm \left[Y_S\left(4\right)\pm Y_S\left(7\right)\right]\\ \pm \left[Y_S\left(8\right)\pm Y_S\left(3\right)\right]\\ \pm \left[Y_S\left(5\right)\pm Y_S\left(6\right)\right]\\ \pm \left[Y_S\left(10\right)\pm Y_S\left(1\right)\right]\end{array}\right]$$

(45)

with the introduction of the auxiliary input sequence $\left\{Y_S\left(i\right):i=1, 2, \dots , N-1\right\}$ defined as follows:

$$Y_S\left(i\right)=Y\left(i\right)\cdot \mathit{sin}(i\alpha )$$

(46)

The expression $c\left(k\right)$ denotes $2\cdot \mathit{cos}(2k\alpha ),$ and the sign of the items in relation (10) is given by the following matrix:

$$SIGN=\left[\begin{array}{ccccc}00& 00& 10& 00& 10\\ 00& 10& 00& 10& 10\\ 10& 00& 10& 10& 10\\ 01& 11& 11& 01& 01\\ 10& 10& 10& 00& 10\\ 11& 11& 01& 01& 01\\ 11& 01& 11& 11& 01\\ 01& 11& 01& 11& 01\\ 10& 00& 00& 00& 10\\ 01& 01& 01& 01& 01\end{array}\right]$$

(47)

where

-

The first bit of the element in the matrix designates the sign before the brackets (minus if “1” and plus if “0”);

-

The second bit of the element in the matrix denotes the operation inside the brackets (subtraction if “1” and addition if “0”).

Equation (45) has a specific structure called pseudo-band correlation. As it can be seen from Figure 1, in such structures, one can observe a band where all of the elements along the secondary diagonal are the same except the sign.

As it has been shown in [38] this special computational structure, called pseudo-band correlation, can be efficiently mapped on a single systolic array with a low hardware complexity. It has all of the advantages of the systolic arrays based on the cycle convolution structures presented in [36,37], such as low I/O cost, high-speed performances due to two-level pipelining, and high regularity, modularity, and interconnection locality, being well suited for a VLSI implementation. It uses only one multiplier in the preprocessing stage, which allows for an additional reduction of the hardware complexity.

2.6. A Systolic Algorithm for Inverse DST Based on Quasi-Band Correlation Structures for a Length N Power of Two

Equation (17) can be written as follows:

$$\begin{gathered} {\left[\begin{array}{cccccccc}Y\left(0\right)& Y\left(1\right)& Y\left(2\right)& Y\left(3\right)& Y\left(4\right)& Y\left(5\right)& Y\left(6\right)& Y\left(7\right)\end{array}\right]}^T= \\ \left[\begin{array}{cccccccc}\mathit{sin}\alpha & \mathit{sin}2\alpha & \mathit{sin}3\alpha & \mathit{sin}4\alpha & \mathit{sin}5\alpha & \mathit{sin}6\alpha & \mathit{sin}7\alpha & \mathit{sin}8\alpha \\ \mathit{sin}3\alpha & \mathit{sin}6\alpha & \mathit{sin}9\alpha & \mathit{sin}12\alpha & \mathit{sin}15\alpha & \mathit{sin}18\alpha & \mathit{sin}21\alpha & \mathit{sin}24\alpha \\ \mathit{sin}5\alpha & \mathit{sin}10\alpha & \mathit{sin}15\alpha & \mathit{sin}20\alpha & \mathit{sin}25\alpha & \mathit{sin}30\alpha & \mathit{sin}35\alpha & \mathit{sin}40\alpha \\ \mathit{sin}7\alpha & \mathit{sin}14\alpha & \mathit{sin}21\alpha & \mathit{sin}28\alpha & \mathit{sin}35\alpha & \mathit{sin}42\alpha & \mathit{sin}49\alpha & \mathit{sin}56\alpha \\ \mathit{sin}9\alpha & \mathit{sin}18\alpha & \mathit{sin}27\alpha & \mathit{sin}36\alpha & \mathit{sin}45\alpha & \mathit{sin}54\alpha & \mathit{sin}63\alpha & \mathit{sin}72\alpha \\ \mathit{sin}11\alpha & \mathit{sin}22\alpha & \mathit{sin}33\alpha & \mathit{sin}44\alpha & \mathit{sin}55\alpha & \mathit{sin}66\alpha & \mathit{sin}77\alpha & \mathit{sin}88\alpha \\ \mathit{sin}13\alpha & \mathit{sin}26\alpha & \mathit{sin}39\alpha & \mathit{sin}52\alpha & \mathit{sin}65\alpha & \mathit{sin}78\alpha & \mathit{sin}91\alpha & \mathit{sin}104\alpha \\ \mathit{sin}15\alpha & \mathit{sin}30\alpha & \mathit{sin}45\alpha & \mathit{sin}60\alpha & \mathit{sin}75\alpha & \mathit{sin}90\alpha & \mathit{sin}105\alpha & \mathit{sin}120\alpha \end{array}\right]· \\ {\left[\begin{array}{cccccccc}x\left(1\right)& x\left(2\right)& x\left(3\right)& x\left(4\right)& x\left(5\right)& x\left(6\right)& x\left(7\right)& x\left(8\right)\end{array}\right]}^T \end{gathered}$$

(48)

It has been shown in [39] that the matrix–vector product in (48) can be restructured by the introduction of certain auxiliary sequences and using appropriate index mappings as follows:

$$\left[\begin{array}{c}{Y}_{ap}\left(0\right)\\ Y_{ap}\left(2\right)\end{array}\right]=\left[\begin{array}{cc}\mathit{sin}2\alpha & \mathit{sin}6\alpha \\ \mathit{sin}6\alpha & -\mathit{sin}2\alpha \end{array}\right]\cdot \left[\begin{array}{c}x\left(2\right)\\ x\left(6\right)\end{array}\right]$$

(49)

$$\left[\begin{array}{c}{Y}_{as}\left(0\right)\\ Y_{as}\left(2\right)\end{array}\right]=\left[\begin{array}{cc}\mathit{sin}4\alpha & \mathit{sin}8\alpha \\ -\mathit{sin}4\alpha & \mathit{sin}8\alpha \end{array}\right]\cdot \left[\begin{array}{c}x\left(4\right)\\ x\left(8\right)\end{array}\right]$$

(50)

$$\left[\begin{array}{c}{Y}_a\left(0\right)\\ Y_a\left(2\right)\end{array}\right]=\left[\begin{array}{c}{Y}_{ap}\left(0\right)\\ Y_{ap}\left(2\right)\end{array}\right]+\left[\begin{array}{c}{Y}_{as}\left(0\right)\\ Y_{as}\left(2\right)\end{array}\right]$$

(51)

$$\left[\begin{array}{c}{Y}_a\left(3\right)\\ Y_a\left(1\right)\end{array}\right]=\left[\begin{array}{c}{Y}_{ap}\left(0\right)\\ Y_{ap}\left(2\right)\end{array}\right]-\left[\begin{array}{c}{Y}_{as}\left(0\right)\\ Y_{as}\left(2\right)\end{array}\right]$$

(52)

$$\left[\begin{array}{c}{Y}_b\left(0\right)\\ Y_b\left(2\right)\\ Y_b\left(3\right)\\ Y_b\left(1\right)\end{array}\right]=\left[\begin{array}{cccc}\mathit{sin}\alpha & \mathit{sin}5\alpha & \mathit{sin}7\alpha & \mathit{sin}3\alpha \\ \mathit{sin}5\alpha & -\mathit{sin}7\alpha & \mathit{sin}3\alpha & \mathit{sin}15\alpha \\ \mathit{sin}7\alpha & \mathit{sin}3\alpha & -\mathit{sin}15\alpha & -\mathit{sin}11\alpha \\ \mathit{sin}3\alpha & \mathit{sin}15\alpha & -\mathit{sin}11\alpha & \mathit{sin}9\alpha \end{array}\right]\cdot \left[\begin{array}{c}x\left(1\right)\\ x\left(5\right)\\ x\left(7\right)\\ x\left(3\right)\end{array}\right]$$

(53)

where $Y_a\left(0\right), Y_a\left(1\right), Y_a\left(2\right),Y_a\left(3\right)$ and $Y_b\left(0\right), Y_b\left(1\right), Y_b\left(2\right),Y_b\left(3\right)$ are elements of some auxiliary sequences that are used to compute $Y\left(k\right), k=\overline{0,7}$.

It is important to note that (53) and (49) have a modular and regular computational structure.

This specific structure is called a quasi-band correlation structure. The shape of this computational structure is shown in Figure 1. The elements along the secondary diagonal or along the lines parallel to the secondary diagonal are identical except for the sign. As further shown, this structure can be efficiently implemented using systolic arrays.

Using the auxiliary output sequences, we can finally express $Y\left(k\right), k=\overline{0,7}$ as

$$\left[\begin{array}{c}Y\left(0\right)\\ Y\left(2\right)\\ Y\left(3\right)\\ Y\left(1\right)\end{array}\right]=\left[\begin{array}{c}{Y}_b\left(0\right)\\ Y_b\left(2\right)\\ Y_b\left(3\right)\\ Y_b\left(1\right)\end{array}\right]+\left[\begin{array}{c}{Y}_a\left(0\right)\\ Y_a\left(2\right)\\ Y_a\left(3\right)\\ Y_a\left(1\right)\end{array}\right]$$

(54)

$$\left[\begin{array}{c}Y\left(7\right)\\ Y\left(5\right)\\ Y\left(4\right)\\ Y\left(6\right)\end{array}\right]=\left[\begin{array}{c}{Y}_b\left(0\right)\\ Y_b\left(2\right)\\ Y_b\left(3\right)\\ Y_b\left(1\right)\end{array}\right]-\left[\begin{array}{c}{Y}_a\left(0\right)\\ Y_a\left(2\right)\\ Y_a\left(3\right)\\ Y_a\left(1\right)\end{array}\right]$$

(55)

It can be noted that Equations (49) and (53) can be efficiently implemented using systolic arrays, based on quasi-band correlation structures, as has been shown in [39].

By noticing that $\mathit{sin}8\alpha =1$, (50) can be re-written as:

$$\left[\begin{array}{c}{Y}_{as}\left(0\right)\\ Y_{as}\left(2\right)\end{array}\right]=\left[\begin{array}{cc}\mathit{sin}4\alpha & 1\\ -\mathit{sin}4\alpha & 1\end{array}\right]\cdot \left[\begin{array}{c}x\left(4\right)\\ x\left(8\right)\end{array}\right]$$

(56)

which requires a single constant factor multiplier for the implementation.

In the case where $N$ is a power of 2, it has been shown in [39] that using the two quasi-band correlation structures, one can obtain two systolic arrays with length $N/2$ and $N/4$, leading to a reduced hardware complexity while maintaining all of the advantages of the systolic arrays based on cycle convolution and circular correlation as mentioned previously.

3. An Improved Systolic Array for Forward DST

Using some of the ideas presented in the section above, in this section we propose a new and efficient solution for a systolic array implementation of the forward DST that offers reduced hardware complexity while maintaining high-speed performances. Moreover, the proposed systolic array allows an efficient incorporation of the obfuscation technique with low overheads, which is important for modern portable devices.

3.1. A New VLSI Algorithm for Forward DST

To appropriately reformulate Equation (1) in view of obtaining a hardware structure with reduced complexity while maintaining high-speed performances, we have introduced a new input restructuring sequence defined as follows:

$$x_a\left(1\right)=x\left(0\right)$$

(57)

$$x_a\left(i+1\right)=x\left(i\right)-x_a\left(i\right)$$

(58)

for $i=1, \dots , N-1$

From Equations (57) and (58), we can see that the input auxiliary sequence $\left\{x_a\left(i\right):i=0, \dots , N-1\right\}$ can be recursively computed, but, compared to similar solutions, as in [2,3], where such auxiliary input sequences have been used, in this case the input sequence is used in natural order and not in reverse order as until now. This important distinction leads to a significant reduction of the hardware complexity of the preprocessing stage since we can avoid a permutation when computing the input auxiliary sequence $\left\{x_a\left(i\right):i=0, \dots , N-1\right\}$.

Using this auxiliary input sequence and an auxiliary output sequence $T\left(k\right)$, we can obtain a parallel decomposition of the algorithm that uses quasi-cycle convolution forms.

The output sequence $\left\{Y\left(k\right):k=1, 2, \dots , N-1\right\}$ can be computed as follows:

$$Y\left(N\right)=x_a\left(N\right)$$

(59)

$$Y\left(k\right)=\left(-1{)}^{k+1}{x}_a\left(N\right)\cdot \mathit{sin}(k\alpha \right)+T\left(k\right)\cdot \mathit{cos}[k\alpha ]$$

(60)

for $k=1, \dots , N-1$.

The new auxiliary output sequence $\left\{T\left(k\right):k=1, 2, \dots , N-1\right\}$ can be computed in parallel using 8 short quasi-cycle convolutions if the transform length $N$ is a prime number. In the following, we consider the transform length $N=17$. Thus, we have:

$$\begin{gathered} \left[\begin{array}{c}T\left(3\right)\\ T\left(7\right)\\ T\left(5\right)\\ T\left(11\right)\end{array}\right]=\left[\begin{array}{cccc}x\left(1+16\right)& -x\left(9+8\right)& x\left(13+4\right)& x\left(15+2\right)\\ x\left(15+2\right)& x\left(1+16\right)& -x\left(9+8\right)& -x\left(13+4\right)\\ -x\left(13+4\right)& x\left(15+2\right)& x\left(1+6\right)& x\left(9+8\right)\\ -x\left(9+8\right)& x\left(13+4\right)& -x\left(15+2\right)& x\left(1+16\right)\end{array}\right]·\left[\begin{array}{c}s\left(3\right)\\ s\left(10\right)\\ s\left(5\right)\\ s\left(11\right)\end{array}\right]+\dots \\ +\left[\begin{array}{cccc}x\left(3+14\right)& -x\left(10+7\right)& x\left(5+12\right)& -x\left(11+6\right)\\ x\left(11+6\right)& -x\left(3+14\right)& x\left(10+7\right)& x\left(5+12\right)\\ -x\left(5+12\right)& -x\left(11+6\right)& x\left(3+14\right)& x\left(10+7\right)\\ x\left(10+7\right)& -x\left(5+12\right)& -x\left(11+6\right)& -x\left(3+14\right)\end{array}\right]·\left[\begin{array}{c}s\left(9\right)\\ s\left(13\right)\\ s\left(15\right)\\ s\left(16\right)\end{array}\right] \end{gathered}$$

(61)

$$\begin{gathered} \left[\begin{array}{c}T\left(9\right)\\ T\left(13\right)\\ T\left(15\right)\\ T\left(1\right)\end{array}\right]=\left[\begin{array}{cccc}-x\left(11+6\right)& -x\left(3+14\right)& -x\left(10+7\right)& x\left(5+12\right)\\ -x\left(5+12\right)& x\left(11+6\right)& x\left(3+14\right)& -x\left(10+7\right)\\ x\left(10+7\right)& x\left(5+12\right)& -x\left(11+6\right)& x\left(3+14\right)\\ x\left(3+14\right)& x\left(10+7\right)& x\left(5+12\right)& x\left(11+6\right)\end{array}\right]·\left[\begin{array}{c}s\left(3\right)\\ s\left(10\right)\\ s\left(5\right)\\ s\left(11\right)\end{array}\right]+\dots \\ +\left[\begin{array}{cccc}x\left(1+16\right)& x\left(9+8\right)& x\left(13+4\right)& -x\left(15+2\right)\\ -x\left(15+2\right)& x\left(1+16\right)& x\left(9+8\right)& -x\left(13+4\right)\\ -x\left(13+4\right)& -x\left(15+2\right)& x\left(1+16\right)& -x\left(9+8\right)\\ x\left(9+8\right)& x\left(13+4\right)& x\left(15+2\right)& x\left(1+16\right)\end{array}\right]·\left[\begin{array}{c}s\left(9\right)\\ s\left(13\right)\\ s\left(15\right)\\ s\left(16\right)\end{array}\right] \end{gathered}$$

(62)

$$\begin{gathered} \left[\begin{array}{c}T\left(14\right)\\ T\left(10\right)\\ T\left(12\right)\\ T\left(6\right)\end{array}\right]=\left[\begin{array}{cccc}x\left(1-16\right)& -x\left(9-8\right)& x\left(13-4\right)& x\left(15-2\right)\\ x\left(15-2\right)& x\left(1-16\right)& -x\left(9-8\right)& -x\left(13-4\right)\\ -x\left(13-4\right)& x\left(15-2\right)& x\left(1-16\right)& x\left(9-8\right)\\ -x\left(9-8\right)& x\left(13-4\right)& -x\left(15-2\right)& x\left(1-16\right)\end{array}\right]·\left[\begin{array}{c}s\left(3\right)\\ s\left(10\right)\\ s\left(5\right)\\ s\left(11\right)\end{array}\right]+\dots \\ +\left[\begin{array}{cccc}x\left(3-14\right)& x\left(10-7\right)& x\left(5-12\right)& -x\left(11-6\right)\\ x\left(11-6\right)& -x\left(3-14\right)& -x\left(10-7\right)& x\left(5-12\right)\\ -x\left(5-12\right)& -x\left(11-6\right)& x\left(3-14\right)& -x\left(10-7\right)\\ -x\left(10-7\right)& -x\left(5-12\right)& -x\left(11-6\right)& -x\left(3-14\right)\end{array}\right]·\left[\begin{array}{c}s\left(9\right)\\ s\left(13\right)\\ s\left(15\right)\\ s\left(16\right)\end{array}\right] \end{gathered}$$

(63)

$$\begin{gathered} \left[\begin{array}{c}T\left(8\right)\\ T\left(4\right)\\ T\left(2\right)\\ T\left(16\right)\end{array}\right]=\left[\begin{array}{cccc}-x\left(11-6\right)& -x\left(3-14\right)& x\left(10-7\right)& x\left(5-12\right)\\ -x\left(5-12\right)& x\left(11-6\right)& x\left(3-14\right)& x\left(10-7\right)\\ -x\left(10-7\right)& x\left(5-12\right)& -x\left(11-6\right)& x\left(3-14\right)\\ x\left(3-14\right)& -x\left(10-7\right)& x\left(5-12\right)& x\left(11-6\right)\end{array}\right]·\left[\begin{array}{c}s\left(3\right)\\ s\left(10\right)\\ s\left(5\right)\\ s\left(11\right)\end{array}\right]+\dots \\ +\left[\begin{array}{cccc}x\left(1-16\right)& x\left(9-8\right)& x\left(13-4\right)& -x\left(15-2\right)\\ -x\left(15-2\right)& x\left(1-16\right)& x\left(9-8\right)& -x\left(13-4\right)\\ -x\left(13-4\right)& -x\left(15-2\right)& x\left(1-16\right)& -x\left(9-8\right)\\ x\left(9-8\right)& x\left(13-4\right)& x\left(15-2\right)& x\left(1-16\right)\end{array}\right]·\left[\begin{array}{c}s\left(9\right)\\ s\left(13\right)\\ s\left(15\right)\\ s\left(16\right)\end{array}\right] \end{gathered}$$

(64)

where we have noted

$$x\left(i+j\right)=x_a\left(i\right)+x_a\left(j\right)$$

(65)

$$x\left(i-j\right)=x_a\left(i\right)-x_a\left(j\right)$$

(66)

and

$$s\left(i\right)=2\cdot \mathit{sin}(2i\alpha )$$

(67)

Using the new auxiliary input sequence given by Equations (57) and (58), we have efficiently reformulated the computation of the forward DST transform into a special computational structure using 8 short quasi-cycle convolutions that can be computed in parallel and where some coefficients are similar.

In the proposed approach, we have reordered the resultant auxiliary input and output sequences using the following index mappings:

$$\xi \left(k\right)=\left(\zeta \circ \psi \right)\left(k\right)=\zeta \left(\psi \left(k\right)\right)$$

(68)

$$\eta \left(k\right)=\left(\zeta \circ \phi \right)\left(k\right)=\zeta \left(\phi \left(k\right)\right)$$

(69)

$$\varphi \left(k\right)=\{\begin{array}{cc}<g^k{>}_N& if\hspace{0.17em}k>0\\ <g^{N+k-1}{>}_N& otherwise\end{array}$$

(70)

$$\zeta \left(k\right)=<2k{>}_N$$

(71)

where we have used the primitive root $g=3$ of the Galois field formed by the transform indices.

3.2. A VLSI Architecture for the Proposed Systolic Algorithm for DST

Using the data-dependence graph-based design procedure [50] and the tag control scheme [51], we can map the first part of the Equation (61) to a linear systolic array and the second part to another systolic array. The same procedure can be applied for Equations (62)–(64). The first systolic arrays have the same length and structure and can be unified into one single systolic array instead of four. Moreover, the operands $s\left(3\right)$, $s\left(10\right)$, $s\left(5\right),$ and $s\left(11\right)$ are fixed and the same for the four systolic arrays, and the two input sequences are the same for all four linear systolic arrays. The same arguments are true for the second systolic array where the fixed operands are $s\left(9\right)$, $s\left(13\right)$, $s\left(15\right),$ and $s\left(16\right)$. This leads to an efficient unification of the four systolic arrays for the first part and of the other four for the second part, resulting in reduced hardware complexity. Because the two unified systolic arrays work in parallel and the four computations in each systolic array are also in parallel, high throughput is obtained. Using this approach, a low complexity implementation can be obtained while maintaining high-speed performance.

To further reduce the hardware complexity and improve the speed performance, we have reformulated the VLSI algorithm in a such way that in every multiplier, one operand is a constant that can be efficiently represented using an optimal signed digit representation.

It is important to mention here that the overall hardware complexity of a processing element is dominated by an efficient implementation of the four multipliers of each processing element.

• A short overview of the signed digit (SD) representations

The SD representation has been used to reduce the time of execution of the multipliers used, for example, in an artificial neural network (ANN) inference phase as in [52], or to reduce the hardware complexity of multipliers used in an FPGA implementation of an ANN architecture as in [53], but also in many other efficient VLSI implementations [54,55,56,57].

We first consider the Canonical Signed Digit (CSD) representation: instead of a binary representation using only 0 s and 1 s, we consider a ternary base system using −1, 0, and 1. In the case when for each digit we have $x_i·x_{i+1}=0$ for all $i=0, \dots , n-1$, we call such a number a Canonical Signed Digit (CSD) number [58].

In the case that the operand used in computer arithmetic is variable, to fully represent a CSD number, it is necessary to assign a location for the sign of each nonzero digit. This significantly increases the word size. To solve this problem, several SD representations have been developed. First, we have the Binary Coded Canonical Sign Digit Number representation [59] and then some more efficient ones: Compact SD [60] and CCS Representation [61].

In the case when the operand used in the computation is a constant, it is not necessary to store the sign, and it is important to reduce the numbers of 1 and −1 used in the representation. To obtain an optimal implementation, it is important to consider the so-called Non-Adjacent Form (NAF) of Canonical Signed Digit representation where we have no adjacent 1 or −1. The optimal form of a such NAF class of CSD is Minimum Signed Digit (MSD) representation [62], [63]. The MSD representation results in a minimum number of non-zero digits in an SD representation and thus in a minimum number of adders/subtracters.

B.

Our SD based VLSI Implementation

In our VLSI implementation of multipliers, we have used the MSD representation to further increase the speed performances and reduce the hardware complexity. Considering the signed digit representation of a fixed-point representation where $c_i\in \left\{-1, 0, 1\right\}$, the multiplication by a constant is given by

$$Y=CX={\displaystyle \sum }_{i=0}^{M-1}{c}_i{2}^{-i}X$$

(72)

and can be implemented using only adders and shift operations.

The shift operations do not consume any hardware as they can be implemented using appropriate hardwiring.

To determine an optimal SD representation for $\widehat{C}$, the approximate fixed-point value of $C$, we have used the following heuristic for the length (number of non-zero digits) of the SD representation:

$$L\left(x, \epsilon \right)=\{\begin{array}{cc}0,& \left|x\right|<\epsilon \\ 1,& x-\underset{\_}{x}<\epsilon ,x-\underset{\_}{x}<\overline{x}-x\\ 1,& \overline{x}-x<\epsilon ,x-\underset{\_}{x}\ge \overline{x}-x\\ L\left(x-\underset{\_}{x}, \epsilon \right),& L\left(x-\underset{\_}{x}, \epsilon \right)<L\left(\overline{x}-x, \epsilon \right)\\ L\left(\overline{x}-x, \epsilon \right),& L\left(x-\underset{\_}{x}, \epsilon \right)\ge L\left(\overline{x}-x, \epsilon \right)\end{array}$$

(73)

where $\underset{\_}{x}=\min \left(\mathrm{sgn}x\cdot 2^{{\lfloor \log }_2\left|x\right|\rfloor }, \mathrm{sgn}x\cdot 2^{{\lceil \log }_2\left|x\right|\rceil }\right)$ and $\overline{x}=\max \left(\mathrm{sgn}x\cdot 2^{\lfloor {\log }_2\left|x\right|\rfloor }, \mathrm{sgn}x\cdot 2^{\lceil {\log }_2\left|x\right|\rceil }\right)$, with $\lfloor a\rfloor$ representing the floor function and $\lceil a\rceil$ representing the ceiling function.

Using this heuristic (and the corresponding representations that result) with $\epsilon =2^{-11}$, we have obtained the following representations of the transform coefficients

Table 1. Transform coefficients fixed-point approximation and their representations.

$\mathbf{Coefficient} \left(\mathit{C}\right)$	$\mathbf{Approximate} \mathbf{Fixed}-\mathbf{Point} \mathbf{Value} \left(\widehat{\mathit{C}}\right)$	${\mathbf{log}}_2\left|\mathit{C}-\widehat{\mathit{C}}\right|$	Representation	No. of Adders
$\mathit{sin}3\alpha$	0.5263671875	−13.9	$2^{-1}+2^{-5}-2^{-8}-2^{-10}$	3
$\mathit{sin}10\alpha$	0.9619140625	−13.5	$2^0-2^{-5}-2^{-7}+2^{-10}$	3
$\mathit{sin}5\alpha$	0.7978515625	−12.6	$2^0-2^{-2}+2^{-4}-2^{-6}+2^{-10}$	4
$\mathit{sin}11\alpha$	0.89501953125	−12.8	$2^0-2^{-3}+2^{-6}+2^{-8}+2^{-11}$	4
$\mathit{sin}9\alpha$	0.99609375000	−11.4	$2^0-2^{-8}$	1
$\mathit{sin}13\alpha$	0.67382812500	−12.9	$2^0-2^{-2}-2^{-4}-2^{-6}+2^{-9}$	4
$\mathit{sin}15\alpha$	0.36132812500	−13.5	$2^{-1}-2^{-3}-2^{-6}+2^{-9}$	3
$\mathit{sin}16\alpha$	0.18359375000	−12.6	$2^{-2}-2^{-4}-2^{-8}$	2

:

The binary form for the transform coefficients and the obtained minimum signed digit (MSD) form have been presented in the following

Table 2. Transform coefficients using minimum signed digit representations.

$\mathbf{Coefficient} \mathbf{\left(}\mathit{C}\mathbf{\right)}$	$\mathbf{Approximate} \mathbf{Fixed}\mathbf{-}\mathbf{Point} \mathbf{Value} \mathbf{\left(}\widehat{\mathit{C}}\mathbf{\right)}$	Binary Representation	Minimum Signed Digit Representation
$\mathit{sin}3\alpha$	0.5263671875	$0.10000110110$	$0.1000100\overline{1}0\overline{1}0$
$\mathit{sin}10\alpha$	0.9619140625	$0.11110110010$	$1.0000\overline{1}0\overline{1}0010$
$\mathit{sin}5\alpha$	0.7978515625	$0.11001100010$	$1.0\overline{1}010\overline{1}00010$
$\mathit{sin}11\alpha$	0.89501953125	$0.11100101001$	$1.00\overline{1}00101001$
$\mathit{sin}9\alpha$	0.99609375000	$0.11111111000$	$1.0000000\overline{1}000$
$\mathit{sin}13\alpha$	0.67382812500	$0.10101100100$	$1.0\overline{1}0\overline{1}0\overline{1}00100$
$\mathit{sin}15\alpha$	0.36132812500	$0.01011100100$	$0.10\overline{1}00\overline{1}00100$
$\mathit{sin}16\alpha$	0.18359375000	$0.00101111000$	$0.010\overline{1}000\overline{1}000$

(where $\overline{1}$ represents $-1$):

In Figure 2, the VLSI systolic array architecture of the hardware core of the implementation proposed for the 1-D DST corresponding to Equations (61)–(64) is presented. The function of a processing element PE from Figure 2 is presented in Figure 3. The SR block is a shift register that is used to obtain the right order for the specific input sequence. It can be seen in Figure 2 that we have used two linear systolic arrays. Each systolic array contains four processing elements where one operand in each multiplier is a constant. This can be used to efficiently implement the multipliers using the technique presented above. The proposed architecture implements Equations (61)–(64) that represent the desired computational structure involving eight short pseudo-cycle convolutions [31,40] having an identical length and the same structure.

Using a hardware sharing technique, four such systolic arrays have been merged into one, finally obtaining only two linear systolic arrays. We can observe that some input sequences in the two systolic arrays are identical and that the others result from a rotate and shift operation using the SR block. This fact has been exploited to significantly lower the I/O cost and to reduce the hardware complexity. It is important to mention here that the so-called I/O bottleneck that can significantly limit the speed performances has been avoided by reusing the input data in as many processing elements as possible.

Moreover, the proposed VLSI architecture can incorporate the obfuscation technique with low overheads as shown below.

In Figure 2, we have used the time-varying obfuscation technique [47,64] where the right key values are represented by $K\left[\mathrm{0..11}\right]$ and $K\left[\mathrm{12..23}\right]$. The principle of the time-varying obfuscation technique is presented in Figure 4, where T1, …, T23 are the trigger signals, and the obfuscated signal is obtained as a combination between Ti and Ci where Ci represents the correct sign bits from Equations (61)–(64).

The pre-processing stage implements Equations (57) and (58) and generates and arranges the input sequences. The post-processing stage computes the output sequence using Equation (60) and arranges the output sequence in the natural order.

As it can be observed from

Table 3. Comparison of the hardware complexity of various DST designs.

Structures	Multipliers	Adders	ROM Words	Through-Put	I/O Channels
[36]	$2$	$2N+3$	$\left[\left(N-1\right)/2\right]2^{L/2}$	$2/\left(N-1\right)$	$7L+1$
[37]	$\left(N+3\right)/2$	$\left(N+11\right)/2$		$4/\left(N-1\right)$	$4L+1$
[41]	$N-1$	$N+1$		$2/\left(N-1\right)$	$5L+N-1$
Proposed	$2$	$137$		$4/\left(N-1\right)$	$8L+32$

, the proposed solution has a low hardware complexity while maintaining a high throughput. It can also be seen that our solution has a double throughput as compared with [36,41] and allows for a reduced complexity of the hardware core presented in Figure 2 since it requires only adders for its hardware implementation. Moreover, the critical computation path can be further reduced by using two-level pipelining. It requires two multipliers in the post-processing stage. Additionally, our solution allows an efficient incorporation of the obfuscation technique that is not presented in the other solutions.

In

Table 4. Summary of the synthesis results (delay, power) of the DST processing chain.

Constrained Clock Period/Fre-Quency	Critical Path Delay + Setup Time [ps]	Static Power [uW]	Dynamic Power at Constrained Clock Frequency [mW]
50 ns/20 MHz	225	110.2	0.2 for 20 MHz
10 ns/100 MHz	225	110.2	0.46 for 100 MHz
1 ns/1 GHz	229	110.0	4.6 for 1 GHz
300 ps/3.33 GHz	228	110.3	15.4 for 3.33 GHz
250 ps/4 GHz	235	109.7	18.6 for 4 GHz
200 ps/5 GHz	200	128.2	27.8 for 5 GHz
175 ps/5.71 GHz	175	151.4	36.4 for 5.71 GHz
150 ps/6.67 GHz	161	178.5	45.9 For 6.67 GHz

and

Table 5. Summary of the synthesis results (area) of the DST processing chain.

Constrained Clock Period/Frequency	Interconnect Area [um2]	Combinational Area [um2]	Flop Area [um2]	Total Area [um2]	Equivalent Gate Count
50 ns/20 MHz	865.36	1763.57	1391.59	4020.53	20,449.3
10 ns/100 MHz	865.36	1763.57	1391.59	4020.53	20,449.3
1 ns/1 GHz	864.67	1772.08	1391.59	4028.34	20,489.0
300 ps/3.33 GHz	870.20	1775.67	1391.59	4037.45	20,535.8
250 ps/4 GHz	883.97	1802.16	1391.59	4077.72	20,740.3
200 ps/5 GHz	1220.68	2041.78	1391.59	4654.04	23,671.5
175 ps/5.71 GHz	1434.74	2343.37	1391.59	5169.70	26,294.5
150 ps/6.67 GHz	1562.45	2679.82	1391.59	5633.86	28,655.5

, the results of the synthesis in terms of delay, power, and area of the RTL description of the DST processing chain are presented. The synthesis was performed using Cadence Genus 19.16 using the Nangate OpenCell Library with NCSU’s 15 nm FreePDK15.

The implementation uses a fixed-point representation for the data, and the width for the $x$ and $y$ inputs and outputs of the processing elements has been set to 12 bits (although the parametric nature of the RTL descriptions allows for a simple reconfiguration of the bus data width).

The translation to the gate level description has been done several times, setting different constraints on the system clock period (from 50 ns to 150 ps).

The DST chain can operate at a potential frequency of 5.71 GHz, while dissipating a power of 36.4 mW at this frequency. When setting the target operating clock period lower than 175 ps, the synthesis tool fails to find a solution within the constraints. The lowest achievable operating clock period is 161 ps, corresponding to a frequency of 6.21 GHz, for which the area increases by about 40% compared to the results with critical path delays close to 200 ps.

To achieve a lower power dissipation, the clock frequency must be reduced. We have obtained a reduced area of about 4000 um² and also a low power consumption that attains the value of 0.46 mW at a frequency of 100 MHz while maintaining high-speed performances. The proposed architecture can operate at a frequency of up to 6.5 GHz, generating four samples for each clock cycle. The critical path is about 200 ps, which allows a high-speed operation of the circuit.

Remarks. Using some of the ideas of the existing systolic array VLSI implementation and an appropriate reformulation of the DST algorithm based on some regular and modular computational structures, we have shown that it is possible to efficiently use the hardware structure using the systolic array architectural paradigm and, even more important, in a such way that a very efficient use of the SD representation can be obtained, leading to a maximization of the advantages of the SD representation as reduced hardware complexity and, at the same time, high-speed performance.

4. Discussion

As known, systolic arrays allow an efficient use of the hardware structures while maintaining high-speed performances using pipelining and parallelism. In our VLSI implementation, we have four systolic arrays working in parallel and, by using pipelining, we have further improved the speed performances. We also used a hardware-sharing technique to efficiently unify the four systolic arrays for the first part and of the other four for the second part of the VLSI algorithm, leading to reduced hardware complexity. Moreover, since the VLSI algorithm has been appropriately reformulated in a such manner that an efficient utilization of an optimal SD representation has been obtained, we have further significantly improved the speed performances and, at the same time, have reduced the hardware complexity. Thus, the proposed implementation can compute four samples for each clock cycle, the frequency of which can be increased up to 6.5 GHz by significantly reducing the critical path delay to about 200 ps. With the use of the presented methods, the obtained area has been significantly reduced to about 4500 um², while the power consumption can be as low as 0.46 mW. Moreover, the proposed solution allows for an efficient incorporation of the hardware security techniques at a low overhead, which is very important for common goods devices.

5. Conclusions and Perspectives

In this paper, we have presented a unified overview of some of the most important VLSI implementations of the forward and inverse discrete sine transforms using systolic arrays. The main features of these VLSI implementation solutions using systolic arrays are presented in a unified way. Thus, one of the central ideas presented shows the advantages of using regular and modular computational structures such as cyclic convolution, circular correlation, and pseudo-band correlation in the VLSI implementation of these transforms. Additionally, due to the regular and modular nature of systolic arrays that are well suited to the features of the VLSI technologies, the efficient use of the hardware structures and low I/O costs allow avoiding of the so-called I/O bottleneck.

We have shown that by applying the ideas presented in this review, we can obtain a new VLSI implementation of the DST using systolic arrays that allow for an efficient hardware implementation with reduced hardware complexity while maintaining high-speed performances. We have used a completely new restructuring input sequence that avoids reversing the input sequence and can be used to efficiently reformulate the computation of the forward DST transform into a special computational structure based on eight short quasi-cycle convolutions with a special form and structure. The partial results can be computed in parallel and shared because some coefficients are similar, leading to a low complexity and a high throughput. As the new restructuring sequence uses the input samples in a natural order as opposed to existing solutions, a significant reduction of the hardware complexity in the pre-processing stage due to avoidance of the necessity of a permutation stage to reverse the order can be achieved. Moreover, the proposed VLSI architecture allows for an efficient incorporation of the obfuscation technique with very low overheads. For future developments, we aim to find other regular and modular computational structures for efficient VLSI implementations of the forward and inverse DST using systolic arrays.