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Article

Low-Latency and Minor-Error Architecture for Parallel Computing XY-like Functions with High-Precision Floating-Point Inputs

by 1,*, 2 and 2
1
School of Microelectronics, Shenzhen Institute of Information Technology, Shenzhen 518000, China
2
Shenzhen Key Laboratory of IoT Key Technology, Harbin Institute of Technology, Shenzhen 518000, China
*
Author to whom correspondence should be addressed.
Academic Editor: Shinichi Yamagiwa
Electronics 2022, 11(1), 69; https://doi.org/10.3390/electronics11010069
Received: 22 November 2021 / Revised: 17 December 2021 / Accepted: 24 December 2021 / Published: 27 December 2021
(This article belongs to the Section Computer Science & Engineering)
This paper proposes a novel architecture for the computation of XY-like functions based on the QH CORDIC (Quadruple-Step-Ahead Hyperbolic Coordinate Rotation Digital Computer) methodology. The proposed architecture converts direct computing of function XY to logarithm, multiplication, and exponent operations. The QH CORDIC methodology is a parallel variant of the traditional CORDIC algorithm. Traditional CORDIC suffers from long latency and large area, while the QH CORDIC has much lower latency. The computation of functions lnx and ex is accomplished with the QH CORDIC. To solve the problem of the limited range of convergence of the QH CORDIC, this paper employs two specific techniques to enlarge the range of convergence for functions lnx and ex, making it possible to deal with high-precision floating-point inputs. Hardware modeling of function XY using the QH CORDIC is plotted in this paper. Under the TSMC 65 nm standard cell library, this paper designs and synthesizes a reference circuit. The ASIC implementation results show that the proposed architecture has 30 more orders of magnitude of maximum relative error and average relative error than the state-of-the-art. On top of that, the proposed architecture is also superior to the state-of-the-art in terms of latency, word length and energy efficiency (power × latency × period /efficient bits). View Full-Text
Keywords: floating point; XY-like functions; QH CORDIC; high accuracy; low latency floating point; XY-like functions; QH CORDIC; high accuracy; low latency
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MDPI and ACS Style

Liu, M.; Fu, W.; Xia, J. Low-Latency and Minor-Error Architecture for Parallel Computing XY-like Functions with High-Precision Floating-Point Inputs. Electronics 2022, 11, 69. https://doi.org/10.3390/electronics11010069

AMA Style

Liu M, Fu W, Xia J. Low-Latency and Minor-Error Architecture for Parallel Computing XY-like Functions with High-Precision Floating-Point Inputs. Electronics. 2022; 11(1):69. https://doi.org/10.3390/electronics11010069

Chicago/Turabian Style

Liu, Ming, Wenjia Fu, and Jincheng Xia. 2022. "Low-Latency and Minor-Error Architecture for Parallel Computing XY-like Functions with High-Precision Floating-Point Inputs" Electronics 11, no. 1: 69. https://doi.org/10.3390/electronics11010069

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