Modeling and Simulation-Based Layout Optimization for Tolerance to TID Effect on n-MOSFET

Abstract

In the present study, the layout structure of an n-MOSFET, which is vulnerable to radiation, was designed in a different way to enhance its tolerance to radiation. Radiation damage assessment was conducted using modeling and simulation (M&S) techniques before actual semiconductor process fabrication and radiation tests to verify its tolerance properties. Based on the M&S techniques, the role of each layer was determined to improve the radiation tolerance of semiconductors, and the layout design of an n-MOSFET with enhanced radiation tolerance was optimized. The optimized radiation-tolerant n-MOSFET design was implemented in the 0.18-um CMOS bulk process, and radiation exposure tests were conducted on the device. A cumulative radiation dose up to 2 Mrad(Si) was applied to verify its radiation-tolerant performance. Developing new devices using M&S techniques for radiation damage assessment allows reliable estimates of their electrical and radiation-tolerant properties to be obtained in advance of the actual manufacturing process, thereby minimizing development costs and time.

1. Introduction

As the fourth industrial revolution expands worldwide, the demand for special-purpose semiconductors continues to grow, especially in fields such as advanced aerospace and nuclear power industries. Electronic devices that are used in nuclear power and space industries, as well as medicine, unmanned aircraft, and autonomous driving, are subjected to a total ionizing dose (TID), caused by exposure to radiation. Semiconductors composed of silicon-based complementary metal–oxide–semiconductor (CMOS) devices, in particular, are easily affected by radiation-induced leakage currents, and this often leads to overall performance degradation. The CMOS integrated circuits (ICs) that perform various functions such as amplification, comparison, data conversion and storage, and stable voltage supply in the latest electronic systems, are required to have high-performance (high speed and high resolution) and high-integration characteristics. However, advanced ICs in a radiation environment are limited to increasing the operating speed and the precision due to the degradation of the CMOS device. In the worst case, ICs can lose function due to accumulated radiation and cause serious social/environmental problems such as radiation exposure and contamination [1,2,3,4,5,6,7,8].

Given that the safety of nuclear reactors and aircraft directly affects human lives, the radiation-tolerant design of semiconductor parts in their internal electronic systems is considered essential. This is also the case in medical applications. Mistakes in calculating the radioactivity of therapeutic radiation sources, malfunctions in X-ray devices and accelerators, or excessive radiation exposure during diagnosis and treatment could cause the intended dose to be exceeded, or lead to radiation accidents. In unmanned aircraft and autonomous driving fields, malfunctions or obstacle detection failures, which are often caused by data errors, may lead to serious consequences including the loss of lives [3,4,5,6,7,8].

CMOS semiconductors have various parameters that make them sensitive to radiation, such as the presence of impurities, and electric fields, as well as the characteristics and geometry of the silicon and oxide materials. This makes it very difficult to analyze the combined effects of such factors. Many attempts have been made to find ways to improve the radiation-tolerant properties of these semiconductors. Recently, considerable research attention has been focused on structural modifying to enhance the radiation tolerance of n-MOSFETs, which are particularly affected by cumulative radiation doses. The research is accomplished by process layout modification, an approach that does not require any additional circuits, logic (speed reduction and area increase) [9,10], or process masks (higher costs) [11]. Radiation tolerance can be achieved just by adding new layers or modifying existing layers, while maintaining the existing CMOS process procedures [12,13,14,15,16].

In previous research, efforts to improve radiation tolerance have focused on making various modifications to an existing MOSFET structure and performing radiation tests on them. Instead, the present study employed modeling and simulation (M&S) techniques for radiation damage assessment, which can predict the effect of radiation on semiconductor devices in advance, in a more efficient manner. This approach could accelerate progress in research to improve the radiation tolerance of semiconductors [17,18].

Using these M&S techniques, the role of each layer in improving the radiation tolerance of semiconductors was investigated, and the design layout of an n-MOSFET with enhanced radiation tolerance was optimized. The optimized radiation-hardened (RH) n-MOSFET design was implemented in a 0.18-um CMOS process. To verify its radiation-tolerant performance, radiation exposure tests then were conducted on the device chip while the dose was increased up to a cumulative radiation of 2 Mrad(Si). The tests were conducted at the high-level gamma-ray irradiation facility of the Advanced Radiation Technology Institute (ARTI) in Korea.

2. M&S Verification of Semiconductor Damage by Radiation

This section describes how M&S techniques were practically employed to assess the radiation damage to semiconductors with radiation dose, using the radiation-induced damage mechanism of semiconductors. The equations used for the characteristic modeling of 3D TCAD-based semiconductor devices are Poisson’s equation, the carrier continuity equations, the transport equations (drift-diffusion transport model and energy balance transport Model), and the displacement current equation.

The most suitable layers, structures, and properties for improving the radiation tolerance of semiconductor devices were determined, and the structural design was modified in various patterns. Many of the previous studies on radiation tolerance improvement have been limited when attempting structural modifications because prototypes must be repeatedly fabricated to conduct tests to verify the radiation tolerance performance of the structural patterns being designed. In contrast, one of the important advantages of the M&S techniques utilized in the present study is that multiple attempts can be made as desired in the virtual environment.

2.1. Cumulative Radiation-Induced Damage to MOSFETs

The total ionizing dose (TID) effect is one of the main causes of damage to silicon-based electronic devices It refers to the phenomenon where ionizing radiation-induced damage is long-term accumulated in electronic devices. This leads to their gradual performance degradation. Radiation has much greater energy than the bandgap of silicon dioxide and thus causes electron/hole pairs (EHPs) to be generated in the silicon dioxide layers. The movement of these EHPs is then determined by the bias applied to the gate. Generally, a positive bias is applied to the gate in n-MOSFETs, and this causes the electrons to move towards the gate electrode and the holes to move towards the silicon bulk. While the electrons are able to escape the silicon dioxide layers because they are highly mobile in the layers, few mobile holes travel across localized states inside the bandgap of the silicon dioxide layers and finally reach the Si-SiO₂ interfaces, where they are trapped. These trapped holes are called fixed charges. When radiation-induced fixed charges are generated in the oxide film layers of an n-MOSFET whose majority carriers are electrons, these fixed positive charges induce a channel inversion between the source and the drain, thereby causing the formation of leakage current paths, as shown in Figure 1 [19,20,21,22].

In the semiconductor manufacturing process, the oxide film layers of an n-MOSFET are divided into isolation oxide films for electrically isolating individual devices, and gate oxide films. In the existing 1 um-plus process, radiation-induced fixed charges can be generated in the gate oxide films, which may lead to a variety of unexpected problems. In the 0.5 um or less deep sub-micron process, however, the thickness of the gate oxide in the bulk CMOS process is set to a value of less than 10 nm. The gate oxide thickness of the 0.18-um CMOS STI process is about 4 nm, and 0.35-um CMOS LOCOS process is about 7 nm. According to previous reports, oxide films with a thickness of less than 10 nm allow the holes to be removed through tunneling, thus significantly reducing variations in the threshold voltage. Therefore, such gate oxide films were no longer considered a major concern in the process [23,24]. In contrast, hundreds-of-nanometer-thick isolation oxides generate fixed charges, which may inflict radiation damage and thus critically degrade the performance of each device. Therefore, shutting down these leakage current paths is a prerequisite to improving the radiation tolerance of the n-MOSFET structure against the TID effect.

2.2. Structural Design of Radiation-Tolerant Layout

As shown in Figure 2, the following structures were designed for each pattern to conduct the M&S of radiation damage to typical n-MOSFET layout structures: (a) a standard structure to identify radiation damage; (b) an extended gate poly structure to minimize damage; (c) a structure in which the n-active region is overlapped with the p-active region, and a p+ doping region is introduced; (d) the combined structure of (b) and (c); and (e) the same structure as (d) except that the n-active region is not overlapped with the p-active region.

Improving radiation tolerance requires minimization of the effect of the radiation-induced fixed charges present in the isolation oxide film layers. Therefore, we basically focused on the structure that can change the position of the insulation oxide films and designed various structures for each pattern in order to secure a structure that does not affect the n+ region (source and drain). This must be achieved by modifying the layout while at the same time maintaining the intrinsic electrical characteristics of the standard structure. Based on semiconductor manufacturing procedures, isolation oxide films will be formed everywhere except for the active region. The cross-sectional views of each structure are presented in Figure 3.

In Structure (a) (standard structure), the fixed charges are trapped at the isolation oxide film-silicon interfaces where sources and drains are formed. In Structure (b), even if the gate poly is extended, the position of the formation of isolation oxide films remains the same during the semiconductor manufacturing process. In Structure (c), p-active and p+ doping regions are added to the source/drain n+ region in a perpendicular direction, and thus the active region is extended. As a result, the position of the formed isolation oxide films is shifted out of the active region. Here, the p+ region remains in a floating state or 0 V voltage is applied to the region. In Structure (d), the gate poly is combined with the p-active and p+ doping regions, and thus the position of the formed isolation oxide films is changed. The gate poly is formed between the p+ and n+ regions on top of the active region [25].

2.3. Using M&S to Assess Radiation Effect

M&S was performed on each structure of the n-MOSFETs to which layout modifications had been applied, as described in Section 2.2, to determine the effect of radiation on them. The effect of cumulative radiation-induced TID on the n-MOSFET intensifies over time because cumulative doses increase, and more and more EHPs are generated over time. This leads to an increase in the number of charges trapped at the isolation oxide film-silicon interfaces. Accordingly, the majority carrier electrons of the n-MOSFET end up forming leakage current paths at the interfaces [26]. A 3D radiation-induced damage model was designed based on this damage mechanism, i.e., by injecting electrons into the interface region. Since the radiation-induced charge distribution in the SiO₂ and Si interface regions is non-uniform due to the electric field and depends on the depth of the insulation oxide film, interface charges were injected with a Gaussian distribution.

This pattern-specific n-MOSFET damage model was used to improve radiation tolerance. The performance degradation of devices was simulated as the number of interface charges increased, by plotting I-V characteristic curves. When the gate voltage was 0 V or less, i.e., when the device remained turned off, the drain current was measured to determine whether the leakage current increased with increasing radiation doses.

Figure 4 shows the respective radiation damage models when radiation-induced interface charges were injected into (a) the standard structure; (b) the extended gate poly structure; (c) the structure to which the p-active and p+ doping regions are added; and (d) the combined structure of (b) and (c). The result from Structure (e) is not presented here because it had the same cross-sectional view as Structure (b) near the corresponding channel.

In the case of Model (c), however, the addition of the p-active and p+ doping regions allowed a gap to be formed between the isolation oxide films and the n+ region. Therefore, even though charges were trapped in the oxide films, the intrinsic electrical characteristics of the structure remained the same as they were before radiation-induced damage. The radiation tolerance properties of Model (c) were confirmed through M&S, but not entirely. The current semiconductor manufacturing process involves a silicide process to reduce the contact resistance of the electrodes. In the case of Model (c), the boundary between the p+ and n+ regions is not clear, and thus there is a risk of short-circuiting through the silicide layers. This may lead to the device malfunction. This risk will be examined in the next chapter with a device that was built and then subjected to measurements.

The drain current was simulated with respect to the gate voltage while increasing the degree of radiation-induced damage using the (a), (b), (c), and (d) models described in Figure 4. The results are shown in Figure 5. When Model (a) (standard structure) was applied, an unexpected channel distribution was induced by radiation at the isolation oxide film-silicon interfaces, thereby causing the formation of leakage current paths. As a result, the leakage current continued to increase as the concentration of injected charges increased, even when the gate voltage was lower than the threshold voltage. This meant that performance degradation occurred. In the case of Model (b), even though the gate poly was added, the isolation oxide films, which were the most prone to damage, were still in contact with the silicon n+ region. Thus, leakage currents were induced by radiation, thereby causing damage to the device, similar to that observed in Model (a). Model (e)’s radiation damage simulation results were also predictable because the model shared the same cross-sectional view as Model (b).

In the case of Model (d), the gate poly of Model (b) was applied to improve the limitations of Model (c). As shown in the simulation results, this structure provided radiation tolerance, and, at the same time, the applied gate poly allowed the p+ region to be separated from the n+ region.

2.4. Radiation Exposure Tests

Pattern-specific damage characteristics of the n-MOSFETs were predicted in advance by the radiation effect M&S analyses. Each layout was then actually designed, reflecting the conditions of the actual 0.18-um CMOS process, and test chips were fabricated accordingly [27,28]. Radiation tests were conducted at the high-level gamma-ray irradiation facility of the Advanced Radiation Technology Institute in Jeongeup, Korea. Cobalt-60 was used as the radiation source, and the dose rate was set to 1Mrad(Si)/h. The total cumulative radiation dose was 2Mrad(Si). The leakage current of the n-MOSFET was measured real-time while increasing the radiation dose. The applied test conditions are summarized in

Table 1. Radiation test conditions for semiconductor devices.

Category	Measurement Condition
Facility	Advanced Radiation Technology Institute
Radiation source	Cobalt-60
Dose Rate	0.5 Mrad/h(Si)
Total Dose	2 Mrad(Si)
Test sample	pattern-specific n-MOSFETs (4-type)
Characteristic	Leakage current
Method	Real-time using 25 m cable
Input Bias	Supply voltage: 1.8 V, Gate voltage: 0 V–1.8 V

. The tests were conducted mutatis mutandis in accordance with the test procedures provided in the US Pentagon’s MIL-STD-883H 1019.8 [29].

Figure 6 shows changes in the leakage current with respect to the cumulative radiation dose. In n-MOSFETs (a), (b), and (e), damage patterns similar to the M&S results were observed, i.e., the leakage current increased with increasing radiation doses, and it started to saturate when the cumulative radiation dose reached about 1Mrad. The radiation tolerance characteristics of Model (c) were already examined through the M&S analysis. In practice, however, n-MOSFET (c) was found to malfunction before being subjected to the radiation exposure test, and this was attributed to a short circuit occurring during the silicide process. Based on the M&S results and the actual measurement results, it was confirmed that RH n-MOSFET structure (d) functioned properly, and its radiation tolerance characteristics were determined.

3. Optimization of Radiation-Hardened n-MOSFET Design

3.1. Design of Radiation-Hardened Variable-Gate n-MOSFET

The performance of RH n-MOSFET (d) was previously verified through the radiation damage M&S analysis, and the actual radiation exposure tests. An RH variable-gate (V-gate) n-MOSFET was proposed and designed by improving the features of the RH n-MOSFET (d). The layout structure of the RH V-gate n-MOSFET included an RH variable layer set on both sides perpendicular to the gate of the standard structure (a). This RH layer set was composed of the poly gate, p+, and P-active layers, and its basic configuration is shown in Figure 7. The poly gate was located within the range where it could be in contact with the existing gate. The p+ layer was formed in the added poly gate on the other side of the existing gate so that it could meet the edge part of the added poly gate, or part of it could be included in the poly gate.

Unlike RH n-MOSFET (d) with a completely shut structure, the RH V-gate n-MOSFET included an RH variable layer set on both sides perpendicular to the existing gate, which allowed only part of the sources or drains to be shut down. In this way, the area where the gate meets the drains or sources could be minimized, and this made it possible to reduce the gate capacitance. The increase in radiation-induced leakage current in the MOSFET and an increase in its capacitance due to structural modifications all result in the same consequence, i.e., a reduction in the operating speed of the device. In this respect, the RH V-gate structure was designed to reduce leakage current-induced damage compared to the existing RH (d) structure.

Additionally, this modified structure was more advantageous than the existing RH structure in that the area could be reduced. As shown in Figure 8, this structure allows the RH layer set to locate in a variable way on both sides, and thus the saved area can be used as connecting paths for sources or drains. To sum up, this RH VG n-MOSFET provides various structural benefits in the RH circuit design by not only minimizing degradation in speed and area but also allowing the electrodes of each device to be connected in a more efficient manner. In addition, the RH layer set can be applied flexibly. This advantage can be applied by changing the size of the RH layer set even if the channel size (width/length) of the device changes. Therefore, irrespective of the device size, radiation damage can be prevented.

Figure 9 shows a cross-sectional view of the RH V-gate n-MOSFET. Here, the RH layer set blocks part of the leakage current paths in the isolation oxide films. As part of the RH layer set, the poly gate not only acts as a silicide blocking layer against short circuits in the p+ and n+ regions but also isolates the isolation oxides from the sources or drains. The P-active layer was formed to be in contact with the edge part of the N-active layer so that the formation of isolation oxides between the active regions could be prevented. In the standard n-MOSFET, the radiation-induced leakage current path is formed by meeting the n+ regions of the source and drain along the boundary between the insulation oxide and the N-active region. Since the proposed RH VG structure partially applies the RH layer set between the drain and the source, the P-active region of the RH layer set partially separates the insulation oxide film from the existing n+ region and blocks the generation of the leakage current path.

The p+ layer serves to prevent the holes trapped in the most outer isolation oxide layer from affecting the n+ region. The RH layer set composed of these layers is capable of selectively blocking the connection between the isolation oxide films and the sources and drains. Therefore, when applied to circuit design, this system ensures efficient area management.

3.2. M&S of the Radiation Effect on RH Variable Gate n-MOSFET

A radiation damage model was designed to assess the radiation tolerance performance of the RH VG n-MOSFET by applying the interface charge injection technique. The basic dimensions of the 3D characteristic model before the injection were as follows: 1 um (length), 2 um (width), 10 nm (gate oxide thickness), and 3 um (body thickness). The doping concentrations for each region were set as follows: 8 × 10¹⁶/cm³ (body), 1 × 10¹⁸/cm³ (channel), and 1 × 10²⁰/cm³ (sources and drains). The gate size and p+ doping concentration of the RH layer set were 0.4 um/1.5 um (width/length) and 1 × 10¹⁹/cm³, respectively. Figure 10 shows the RH VG n-MOSFET characteristic model, and

Table 2. Geometry and doping profiles of the RH V-gate n-MOSFET.

n-MOSFET Geometry				RH Variable Gate
Width/length (um/um)	Body thickness (um)	Gate oxide thickness (nm)	Isolation oxide thickness (um)	width/length (um/um)
2/1	3	10	0.3	0.4/1.5
n-MOSFET doping profile
Region (type)	Doping density (/cm3)		Depth (nm)	Fuction
Drain (n+)	1*1020		80	Gaussian, Error
Source (n+)	1*1020		80	Gaussian, Error
Body (p+)	1*1016		-	Constant
Channel (n+)	2*1017		35	Gaussian, Step
RH layer (p+)	1*1019		80	Gaussian, Error

summarizes its geometry and doping profiles [30].

The radiation-induced charge injection model for radiation damage assessment was employed to perform the radiation tolerance performance M&S. As shown in Figure 11, an increase in the cumulative radiation dose was simulated by controlling the concentration of the charges trapped at the silicon interfaces, and I_Drain-V_Gate characteristic curves were plotted with respect to the increasing charge concentration to analyze the electrical properties of the n-MOSFET and further verify its radiation tolerance. The simulation conditions were V_p-sub = 0 V, V_drain = 0.1 V, V_source = 0 V, and V_gate = −0.4~3 V. The concentration of the silicon interface-trapped charges was increased to up to 5 × 10¹⁸/cm³, and, in the meantime, the electrical characteristics of the device were simulated with respect to the varying charge concentration. The results are shown in Figure 12.

It was found that the RH V-gate n-MOSFET was able to maintain its intrinsic electrical properties as the concentration of radiation-induced interface charges was increased to 5 × 10¹⁸/cm³. These results confirm that the RH V-gate n-MOSFET has a highly efficient, compact structure that inherits the radiation-tolerance characteristics and advantages of the existing (d) structure because all the unnecessary elements have been removed and the parts that may have caused the performance degradation of the device have been modified.

3.3. Radiation Exposure Tests and Results Analysis on RH Variable Gate n-MOSFET

The performance of the optimized RH n-MOSFET structure was verified through the M&S-based radiation tolerance assessment. To experimentally verify its performance, chips were actually fabricated in a commercial 0.18-um CMOS process. Figure 13 shows the optimized drawings to which the layout modifications were applied. Standard n-MOSFET was also fabricated as a control group.

Radiation tests were conducted on the optimized structure under the same conditions as in the pattern-specific n-MOSFET tests described earlier in Section 2.4, i.e., by increasing the cumulative radiation dose up to 2 Mrad.

As shown in Figure 14, the drain currents of both the standard structure and the RH V-gate n-MOSFET structure were experimentally measured with respect to the gate voltage. While the gate voltage was lower than the threshold voltage, i.e., the device remained turned off, a leakage current was measured with increasing cumulative radiation doses. In the case of the standard structure, even though it remained turned off, the leakage current rapidly increased to about 10 uA until the cumulative radiation dose reached 1Mard, and then it started to saturate. This indicates that, when exposed to radiation environments, standard n-MOSFET-based ICs may experience malfunctions or data errors as the cumulative radiation dose increases. In contrast, the leakage current in the RH V-gate n-MOSFET structure was kept below nA levels regardless of the cumulative radiation dose. These results confirmed the improved radiation tolerance performance of the modified structure, and the predicted results obtained with the M&S techniques were experimentally verified to be valid.

4. Conclusions

In the present study, a radiation-tolerant MOSFET structure was optimized in an attempt to ensure electronic devices will maintain their original performance when exposed to radiation environments. M&S techniques were employed to conduct a radiation effect assessment and allowed us to attempt to modify the layout structure using various patterns as desired. This approach helped us to determine reliable estimates of the radiation-tolerance characteristics of the designed structures before starting the actual manufacturing of the semiconductor chips, thereby minimizing research and development costs and time. We compared and analyzed the damage and tolerance characteristics of n-MOSFETs through the radiation injection M&S and proposed a radiation-hardened variable-gate n-MOSFET. The proposed RH VG n-MOSFET was designed and fabricated in the 0.18-um CMOS process, and radiation exposure tests were performed together with the standard n-MOSFET. As a result of the radiation measurement, the radiation damage occurred in the standard n-MOSFET, but the proposed RH VG structure was confirmed to be radiation-tolerant up to a total cumulative dose of 2 Mrad.

Finally, an optimized RH VG n-MOSFET structure was developed and subjected to M&S-based verification, actual fabrication, and experimental verification through radiation exposure tests. The major findings of the present study are expected to significantly contribute to implementation of the radiation-tolerant design in a wide range of applications, from electronic circuits to systems.