# Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication

^{*}

^{†}

## Abstract

**:**

## 1. Introduction

## 2. 5G New Radio LDPC Codes

#### 2.1. Introduction

#### 2.2. Quasi-Cyclic LDPC Codes

#### 2.3. 5G New Radio QC-LDPC Characteristics

**Step 1:**Consider the base graph BG1 or BG2 and select the value of ${k}_{b}$ for the corresponding K and R.- –
- For BG1: ${k}_{b}=22$.
- –
- For BG2: ${k}_{b}=10$ if $K>640$; ${k}_{b}=9$ if $560<K\le 640$; ${k}_{b}=8$ if $192<K\le 560$; and ${k}_{b}=6\phantom{\rule{3.33333pt}{0ex}}\mathrm{elsewhere}.$

**Step 3:**After the lifting size Z is determined, the corresponding shift coefficient matrix is then picked up from Table 1 {Set 1, Set 2,⋯, Set 8} according to Z.**Step 4:**Calculate the shifting coefficient value ${P}_{i,j}$ by the modular Z operation, as defined in Equation (4).**Step 5:**Substitute each entry in the final exponent matrix by the corresponding circulant permutation matrix or zero matrix of size $Z\times Z$. The QC-LDPC code construction is accomplished, and a parity-check matrix H of size ${m}_{b}Z\times {n}_{b}Z$ is achieved.

## 3. Combined Min-Sum Algorithm

Algorithm 1 Combined Min-Sum Algorithm |

## 4. Proposed LDPC Decoder Architecture

#### 4.1. Overall Decoder Architecture

#### 4.2. Memory Blocks

#### 4.3. Switch Network

#### 4.4. Variable Node Units

#### 4.5. Check Node Units

#### 4.6. A Posteriori Information Update Units

#### 4.7. Controller Block

## 5. Implementation Results and Comparisons

Design | Proposed | [37] | [38] | [36] |
---|---|---|---|---|

Standard | 5G-NR | 802.15.3c | 802.11n | 802.16e |

CMOS technology | 65-nm | 90-nm | 90-nm | 90-nm |

LDPC code | irregular | regular | irregular | irregular |

Scheduling | layered | layered | layered | layered |

Decoding algorithm | CMS | NMS | MS | NMS |

Submatrix size | 56 | 21 | 81 | 96 |

Code length | 3808 | 672 | 1944 | 2304 |

Code rate | 1/3 | 1/2 | 1/2 | 1/2 |

Bit-width (bits) | 4 | 4 | 4 | 6 |

Max. iterations | 10 | 5 | 10 | 10 |

Frequency (MHz) | 750 | 157 | 555 | 950 |

Memory (Kb) | 92.512 | 6.93 | - | 87.752 |

Area (mm${}^{2}$) | 1.49 | 2.25 | 4.88 | 2.90 |

Norm. Area (mm${}^{2}$) | 1.49 | 6.65 | 4.99 | 1.67 |

Throughput (Gbps) | 3.04 | 5.28 | 4.5 | 2.20 |

Norm. Throughput (Gbps) | 3.04 | 7.31 | 6.23 | 3.05 |

Power (mW) | 259 | 182 | 523 | 870 |

Energy effic. (pJ/bit) | 85.20 | 34.47 | 116.22 | 395.45 |

Norm. Energy effic. (pJ/bit) | 85.20 | 24.90 | 83.95 | 285.25 |

TAR (Gbps/mm${}^{2}$) | 2.04 | 2.35 | 0.92 | 0.76 |

NTAR ${}^{\u2020}$ (Gbps/mm${}^{2}$) | 2.04 | 1.10 | 1.25 | 1.83 |

^{†}NTAR = Norm. Throughput/Norm. Area.

## 6. Conclusions

## Author Contributions

## Funding

## Acknowledgments

## Conflicts of Interest

## References

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**Figure 1.**Sketch of base parity-check structure for the 5G new radio (NR) quasi-cyclic low-density parity-check (QC-LDPC) codes.

**Figure 3.**Schematic representation of base matrix base graph (BG)1 defined by 5G NR standard for generating a QC-LDPC code of code length N = 3808 bits, code rate $R=1/3$, and $Z=56$.

**Figure 4.**Proposed overall low-complexity high-throughput pipelined layered QC-LDPC decoder architecture.

**Figure 8.**Architecture of ${2}^{k}$-first minimum value generator (FMVG) unit using the TS approach [34].

**Figure 10.**Decoding performance of the QC-LDPC decoders on the $N=3808$, $R=1/3$ for base matrix BG1 of 5G NR.

Exponent Matrix | Lifting Size Set |
---|---|

Set 1 | $Z=2\times {2}^{j},j=0,1,2,3,4,5,6,7$ |

Set 2 | $Z=3\times {2}^{j},j=0,1,2,3,4,5,6,7$ |

Set 3 | $Z=5\times {2}^{j},j=0,1,2,3,4,5,6$ |

Set 4 | $Z=7\times {2}^{j},j=0,1,2,3,4,5$ |

Set 5 | $Z=9\times {2}^{j},j=0,1,2,3,4,5$ |

Set 6 | $Z=11\times {2}^{j},j=0,1,2,3,4,5$ |

Set 7 | $Z=13\times {2}^{j},j=0,1,2,3,4$ |

Set 8 | $Z=15\times {2}^{j},j=0,1,2,3,4$ |

$\mathit{Z}$ | $\mathit{a}$ | ||||||||

2 | 3 | 5 | 7 | 9 | 11 | 13 | 15 | ||

$\mathit{j}$ | 0 | 2 | 3 | 5 | 7 | 9 | 11 | 13 | 15 |

1 | 4 | 6 | 10 | 14 | 18 | 22 | 26 | 30 | |

2 | 8 | 12 | 20 | 28 | 36 | 44 | 52 | 60 | |

3 | 16 | 24 | 40 | 56 | 72 | 88 | 104 | 120 | |

4 | 32 | 48 | 80 | 112 | 144 | 176 | 208 | 240 | |

5 | 64 | 96 | 160 | 224 | 288 | 352 | |||

6 | 128 | 192 | 320 | ||||||

7 | 256 | 384 |

No. of Rows | Check Node Degree ${\mathit{d}}_{\mathit{c}}$ | ||||||||
---|---|---|---|---|---|---|---|---|---|

3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 19 | |

in BG1 | 1 | 5 | 18 | 8 | 5 | 2 | 2 | 1 | 4 |

in BG2 | 6 | 20 | 9 | 3 | 0 | 2 | 0 | 2 | 0 |

19-FMVG | 19-TMVG | |
---|---|---|

No. of Comparators | 18 | 35 |

No. of MUX${}_{w-1}$ | 27 | 53 |

No. of MUX | 0 | 11 |

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**MDPI and ACS Style**

Thi Bao Nguyen, T.; Nguyen Tan, T.; Lee, H.
Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication. *Electronics* **2021**, *10*, 516.
https://doi.org/10.3390/electronics10040516

**AMA Style**

Thi Bao Nguyen T, Nguyen Tan T, Lee H.
Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication. *Electronics*. 2021; 10(4):516.
https://doi.org/10.3390/electronics10040516

**Chicago/Turabian Style**

Thi Bao Nguyen, Tram, Tuy Nguyen Tan, and Hanho Lee.
2021. "Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication" *Electronics* 10, no. 4: 516.
https://doi.org/10.3390/electronics10040516