A Novel DC Bias Suppression Strategy for Single-Phase Full-Bridge DC-DC Arc Welding Converter

Abstract

The high frequency transformer in single-phase full-bridge DC-DC converter is prone to saturation because of the asymmetry of circuit parameters. Transformer saturation will increase power consumption, accelerate the aging of winding insulation, and even damage power switches. In order to prevent this risk, a DC bias suppression strategy is presented in this article, and the main advantage of this strategy is that the problem of transformer saturation can be completely eliminated. In this article, firstly, the DC bias and saturation mechanism of single-phase full-bridge DC-DC converter are analyzed in detail, and the Maximum Integral Value of Volt-Second Product error (MIVVSPE) is derived. Secondly, aiming at the saturation problem of single-phase full bridge DC-DC converter, a new digital integral circuit is designed to evaluate the DC bias state of transformer, and a DC bias suppression strategy is constructed to suppress the saturation of transformer. Furthermore, different from the traditional current feedback control strategy, the DC bias suppression strategy based on volt-second product error integral can be triggered before the transformer enters the saturation state, and the transformer saturation can be completely suppressed. Finally, a 30 kW single-phase full-bridge DC-DC converter for arc welding is established in lab. The experimental results show that the new DC bias suppression strategy can effectively prevent the transformer from entering the saturation state and improve the operation stability of single-phase full-bridge DC-DC arc welding inverter.

1. Introduction

With the rapid development of power electronic technology, high efficiency low voltage and high current arc welding inverter have been widely used in industrial production [1,2]. The single-phase full-bridge DC-DC converter topology has higher power processing capacity and makes better use of transformer core and power switch, which fully meets the requirements of modern arc welding machine, and it has become a research hotspot in the field of welding power supply [3,4,5].

The asymmetry of circuit parameters is one of the main reasons for DC bias of single-phase full-bridge DC-DC converter. For example, the non-synchronization of the driving signals and the difference of the turn on/off delay of IGBT will lead to unequal pulse width in the transformer input voltage. Moreover, the difference in the on-state resistance of IGBT will cause the asymmetry of the input voltage amplitude of the transformer. When the input voltage of the transformer is asymmetrical in amplitude and pulse width, the volt-second product on the primary side will enter an unbalanced state, and then the transformer will operate in the DC bias state [6,7,8]. In most arc welding applications, the frequent short circuit and no-load makes the DC bias more serious, which increases the risk of transformer saturation and reduces the reliability of arc welding inverter [9].

In order to solve this problem, various methods have been proposed, which can be divided into hardware topology optimization method [10,11,12,13,14] and software optimization method [15,16,17,18,19,20,21,22,23,24]. The hardware topology optimization method is to improve the anti-DC bias ability by adjusting the structure and parameters of the hardware topology, which belongs to the active suppression method. The “DC blocking capacitor” is usually connected in series with the primary winding of the transformer to prevent DC bias. However, the DC bias suppression ability of the DC-blocking capacitor is proportional to the capacity of the selected capacitor. When the capacity is small, the DC bias suppression ability is stronger, but the partial voltage on the capacitor is also larger, which will reduce the energy conversion efficiency of the inverter. When the capacity is large, it can only restrain the DC bias caused by the slowly changing volt-second product imbalance, but has little inhibitory effect on the DC bias caused by the fast-changing volt-second product imbalance. In addition, It is also feasible to introduce an air-gap into the $B-H$ circuit. Because the permeability of the non-magnetic material is lower, it needs a higher H to obtain the same B compared with the soft magnetic material. Therefore, the air-gap increases the value of magnetization current and lowers the achievable flux density. However, due to increased reluctance of an air gap the flux spreads into the surrounding medium causing the flux fringing effect. It is generally an unwanted phenomenon which usually increases proximity and eddy current loss in conductors located in the vicinity of the air gap. The essence of the software optimization method is a closed-loop optimization control strategy, where the control variable is the duty cycle of the full-bridge drive pulse, and the feedback variable is the primary current of the transformer. When the transformer enters the saturation state, a large current pulse will be generated in the primary current, and, if the current pulse exceeds the reference current, the DC bias suppression strategy will be triggered. Therefore, this method belongs to passive suppression method. In addition, in the suppression strategy, the adjustment mode and depth of duty cycle do not depend on the degree of saturation, and the feedback current is only used to trigger the adjustment strategy; therefore, the software optimization method is blind and has poor reliability in the treatment of transformer saturation.

The main contribution of this article is to analyze the saturation mechanism of transformer in detail, and the mathematical expression of the Maximum Integral Value of Volt-Second Product Error (MIVVSPE) is derived. Then, on the basis of theoretical analysis and mathematical derivation, a DC bias suppression method to prevent transformer saturation is proposed. In the rest of the paper, the mechanism of transformer saturation is analyzed, and the MIVVSPE expression is derived in Section 2. The proposed DC bias suppression strategy, including the circuit design method, is presented in Section 3. Then, in Section 4, a 30 kW single-phase full-bridge DC-DC converter for arc welding is established to verify the effectiveness of the suppression strategy. Finally, the conclusion of the paper is drawn in Section 5.

2. Generation Mechanism of MIVVSPE

A circuit of the single-phase full-bridge DC-DC converter is depicted in Figure 1 [25]. It is composed of an inverter and a rectifier. The inverter consists of a high frequency transformer $TR$ and four IGBTs used as controllable switches $Q1$, $Q2$, $Q3$, and $Q4$, where, in order to simplify the analysis process, the transformer is modeled by an ideal transformer, and its magnetizing inductance $Lm$, the leakage inductances, and stray capacitances are neglected. The transistors in each switching leg are driven by nonoverlapping voltages that are out of phase by ${180}^{\circ }$. The maximum duty cycle of the gate-to-source voltages is slightly less than $44\%$. The waveforms of the gate-to-source voltages should not overlap each other to avoid cross conduction [26]. When $Q1$ and $Q4$ are on, $Q2$ and $Q3$ are turned off, and the current path is A (+) → Q1 → the primary side of transformer → Q4 → B (−), and the voltage at the primary side is $v_1$, $Q2$ and $Q3$ turn off, and bears forward voltage. When $Q1$ and $Q4$ are turned off, the voltage polarity at the primary side is reversed, and the stored energy of the transformer is released through the freewheeling diode $D3$, capacitor $Cin$ and diode $D2$. At this moment, there is no voltage drop in $Q2$ and $Q3$, and $Q1$ and $Q4$ bear forward voltage. In this process, the energy release is faster, and the voltage amplitude of $Q1$ and $Q4$ will decay quickly. When the current on the primary side is zero, $Q2$ and $Q3$ are turned on, and the current is reversed. When $Q2$ and $Q3$ are turned off again, the above process will be repeated.

Figure 1. The single-phase full-bridge DC-DC converter with a transformer center-tapped rectifier.

2.1. Saturation Mechanism Analysis

Figure 2 shows the key waveforms in the single-phase full-bridge DC-DC converter with a transformer center-tapped rectifier for continuous conduction mode.

Figure 2. The key waveforms in the single-phase full-bridge DC-DC converter: (a,b) represent the gating signals for $Q1$ and $Q4$, $Q2$, and $Q3$, respectively. (c,d) represent the across voltages of $Q1$ and $Q4$, $Q2$, and $Q3$, respectively. (e) The voltage across the primary winding $v_1$.

During the time interval $0<t\le t_{on1}$, the switches $Q1$ and $Q4$, as well as the diode $D5$, are on, whereas the switches $Q2$ and $Q3$, as well as the diode $D6$, are off, and the voltage across the primary winding is:

$$v_1=v_{in}-v_{Q1}-v_{Q4}.$$

(1)

Similarly, within time interval $T/\phantom{T2}2<t\le T/\phantom{T2}2+t_{on2}$, the voltage across the primary winding can be expressed as:

$$v_1=-\left(v_{in}-v_{Q2}-v_{Q3}\right),$$

(2)

where $v_{Q1}$, $v_{Q2}$, $v_{Q3}$, and $v_{Q4}$ represents the voltages across $Q1$, $Q2$, $Q3$, and $Q4$, respectively.

Assume that the IGBTs are ideal switches. Then, the on-resistance of IGBTs are equal, such that $v_{Q1}=v_{Q2}=v_{Q3}=v_{Q4}$; therefore, the amplitudes of $v_1$ are equal during the positive half-wave (Equation (1)) and the negative half-wave (Equation (2)). At the same time, the turn on/off delay are the same, and there is no difference between gate drive signals, so that the pulse width is also equal $t_{on1}=t_{on2}=D_{0}T$, where $D_0=T/\phantom{T{t}_{on1}}{t}_{on1}=T/\phantom{T{t}_{on2}}{t}_{on2}$ represents the duty cycle of $v_1$. Therefore, the volt-second product can be expressed as:

$$\overline{v}={\int }_0^T{v}_{1}dt={\int }_0^{D_{0}T}{v}_{1}dt+{\int }_{T/2}^{\left(T/2+D_{0}T\right)}{v}_{1}dt=0.$$

(3)

According to Equation (3), the magnetic induction can be expressed as:

$$B={\int }_0^T\frac{v_1}{N_1{A}_E}dt={\int }_0^{D_{0}T}\frac{v_1}{N_1{A}_E}dt+{\int }_{T/2}^{\left(T/2+D_{0}T\right)}\frac{v_1}{N_1{A}_E}dt=0,$$

(4)

where $A_E$ represents the cross-sectional area of the transformer core, and $N_1$ represents the number of turns of the primary side of the transformer.

However, in most applications, the circuit parameters of single-phase full-bridge DC-DC converter are often asymmetric, such as the slight difference in gate drive signals, turn-on/turn-off delay, and on-resistance of IGBTs. The asymmetry of the gate drive signals or the difference in turn on/off delay of IGBTs will result in pulse width imbalance. As shown in Figure 3a, the turn-off delay of $Q1$ and $Q4$ is greater than that of $Q2$ and $Q3$, so that the positive pulse width is increased to $t_{on1}=\left(D_0+\Delta D\right)T$. And the non-uniformity in on-resistance of IGBTs will lead to the across voltages $v_{Q1}$∼$v_{Q4}$ to be unequal, according to Equations (1) and (2), and it will result in amplitude unbalance. As shown in Figure 3b, the on-resistance of $Q1$ and $Q4$ is less than that of $Q2$ and $Q3$, so that the positive amplitude of $v_1$ is increased to $V_1+\Delta V$. If the above two unbalance conditions exist at the same time, the voltage across the primary winding is shown in Figure 3c. Furthermore, when the negative imbalance occurs, the change of the amplitude and pulse width of $v_1$ in the negative half wave is the same as that in the positive half wave of $v_1$ in Figure 3.

Figure 3. The voltage across the primary winding under positive unbalanced conditions: (a) The pulse width imbalance. (b) The amplitude unbalance. (c) Both pulse width and amplitude are unbalanced.

If the inverter meets the unbalance condition shown in Figure 3, the volt-second product will produce an error in the switching period $T_i$:

$$\left\{\begin{array}{c}{\overline{v}}_i={\int }_0^{\left(D_0+\Delta D\right)T}{V}_{1}dt+{\int }_{T/2}^{\left(T/2+D_{0}T\right)}\left(-V_1\right)dt=V_1·\Delta DT,Figure3a\hfill \\ {\overline{v}}_i={\int }_0^{D_{0}T}\left(V_1+\Delta V\right)dt+{\int }_{T/2}^{\left(T/2+D_{0}T\right)}\left(-V_1\right)dt=\Delta V·D_{0}T,Figure3b\hfill \\ {\overline{v}}_i={\int }_0^{\left(D_0+\Delta D\right)T}\left(V_1+\Delta V\right)dt+{\int }_{T/2}^{\left(T/2+D_{0}T\right)}\left(-V_1\right)dt=\left(V_1+\Delta V\right)\Delta DT+\Delta V·D_{0}T,Figure3c\hfill \end{array}.\right.$$

(5)

Therefore, the magnetic induction error in the switching period $T_i$ can be expressed as:

$$B_i={\int }_0^T\frac{v_1}{N_1{A}_E}dt=\frac{1}{N_1{A}_E}{\overline{v}}_i>0.$$

(6)

When $B_i>0$, the $B-t$ curve is no longer symmetrical about zero axis and shift to the positive direction, and the transformer enters positive DC bias state. Moreover, as the volt-second product error $\Delta {\overline{v}}_i$ in Equation (5) continues to accumulate in the positive direction, the deviation degree of the $B-t$ curve becomes larger and larger, and the DC bias degree of transformer is also getting deeper and deeper. As shown in Figure 4b, the positive maximum $+B_m$ and negative maximum $-B_m$ increase with the deviation of $B-t$ curve, where $+B_m<+B_m^{\prime }<+B_m^{″}$, $-B_m<-B_m^{\prime }<-B_m^{″}$.

Figure 4. The $B-t$ curves: (a) $\Delta {\overline{v}}_i=0$, $\Delta B_i=0$. (b) $\Delta {\overline{v}}_i>0$, $\Delta B_i>0$.

According to the definition of magnetic permeability $\mu$:

$$\mu =B/\phantom{BH}H,$$

(7)

where H represents the magnetic field intensity in the magnetic medium.

The current through the primary winding $i_Q$ is the sum of secondary current $i_2$ converted to primary side $N_2·i_2/\phantom{N_2·i_2{N}_1}{N}_1$ and the magnetizing current $i_{Lm}$:

$$i_Q=\frac{N_2·i_2}{N_1}+i_{Lm},$$

(8)

where $N_2$ is the number of turns in the secondary winding.

The excitation current $i_{Lm}$ is measured under the no-load; therefore, $i_{Lm}$ is a relatively small current [26]. When $i_{Lm}$ is small, B increases with the increase of $i_{Lm}$, and H is proportional to $i_{Lm}$. However, when B increases to the saturation magnetic induction $B_m$, it will not continue to increase, while H will continue to increase, according to Equation (7), and $\mu$ will decrease. Because $i_{Lm}$ is inversely proportional to $\mu$, when $\mu$ begins to decrease, $i_{Lm}$ will begin to increase sharply. According to Equation (8), a large current pulse $i_{peak}$ will be generated in $i_Q$ due to the sharp increase of $i_{Lm}$. When $i_{peak}$ is greater than the rated current of the IGBT, IGBT may be damaged due to over current. The corresponding $B-i_{Lm}$ curves is shown in Figure 5.

Figure 5. The $B-i_{Lm}$ curves: (a) No DC Bias. (b) Positive DC Bias. (c) Positive Saturation. (d) Negative DC Bias. (e) Negative Saturation.

When the transformer is in steady state, the corresponding $B-i_{Lm}$ curve is symmetrical about the zero point $\left(0,0\right)$, as shown in Figure 5a. However, if the transformer enters the positive DC bias state, the symmetry center will move up from the zero point, as shown in Figure 5b. And then, if the transformer enters the negative DC bias, the symmetry center will move downward from the zero point, as shown in Figure 5d. When the transformer enters the saturation state, the $B-i_{Lm}$ curve is distorted and no longer symmetrical, such as in Figure 5c, where the transformer enters the positive saturation state, and the $B-i_{Lm}$ curve is distorted in the first quadrant. Similarly, in Figure 5e, the transformer enters the negative saturation state, and the $B-i_{Lm}$ curve is distorted in the third quadrant.

2.2. Derivation of MIVVSPE

According to the above analysis, the current pulse $i_{peak}$ produced in the primary winding is the result of transformer saturation, not the cause. In fact, the root cause of the transformer saturation is that the Integral Value of Volt-Second Product Error (IVVSPE) $e_{IVVSPE}$ reaches and exceeds the Maximum Integral Value of Volt-Second Product Error (MIVVSPE).

Therefore, when the transformer enters the DC bias state, after N consecutive switching cycles, the Integral Value of Volt-Second Product Error $e_{IVVSPE}$ can be expressed as:

$${\left(e_{IVVSPE}\right)}_N={\overline{v}}_1+{\overline{v}}_2+\cdots +{\overline{v}}_N={\sum }_{i=1}^N{\overline{v}}_i.$$

(9)

When the transformer enters the positive critical saturation state, $e_{IVVSPE}=MIVVSP{E}_{+}$, if ${\left(e_{IVVSPE}\right)}_N>MIVVSP{E}_{+}$ indicates that the transformer will enter the positive saturation state. On the contrary, when the transformer will enter the negative critical saturation state, $e_{IVVSPE}=MIVVSP{E}_{-}$, and, if ${\left(e_{IVVSPE}\right)}_N<MIVVSP{E}_{-}$, means that the transformer will enter the negative saturation state.

3. Proposed Suppression Strategy

To suppress the DC bias and prevent transformer from entering saturation state, a volt-second product error integral feedback control mode is proposed in this paper. Different from the traditional current feedback control mode in References [15,16,17,18,19,20,21,22,23,24], the trigger condition of this feedback control mode is the Integral Value of Volt-Second Product Error $e_{IVVSPE}$, and the DC bias suppression strategy can be triggered before transformer enters the saturation state. When ${\left(e_{IVVSPE}\right)}_N\ge MIVVSP{E}_{+}$, the positive DC bias suppression strategy will be triggered. When ${\left(e_{IVVSPE}\right)}_N\le MIVVSP{E}_{-}$, the negative DC bias suppression strategy will be triggered. Therefore, the volt-second product error integral feedback control method proposed in this paper belongs to a active suppression method.

3.1. Construction of Closed-Loop Controller

According to the previous analysis, a closed-loop control structure from control variable (The duty cycle $D_0$) to feedback variable (The Integral Value of Volt-Second Product Error $e_{IVVSPE}$) is constructed as shown in Figure 6.

Figure 6. The block diagram of closed-loop control structure with DC bias suppression strategy.

3.2. Synchronous Sampling and Integrator Circuit

In this control diagram, the key of the DC bias suppression strategy is the integral calculation of volt-second product error. Therefore, it is necessary to design an efficient and reliable long-time no zero drift integrator to measure the DC bias degree. The analog integrator has good dynamic response characteristics, but the zero drift of the integrated operational amplifier seriously restricts the application of the analog integrator in the long-time integration operation.

To solve this problem, a new long-time no zero drift integrator circuit is proposed in Figure 7. In the signal sampling part, the transformer in arc welding inverter is used to convert the high-frequency and high-voltage signal $v_1$ into a low-voltage small signal $v_3$. In the part of integral operation circuit, the multi-thread parallel integral operation logic is constructed in the Field-Programmable Gate Array (FPGA) to improve the calculation speed of the $e_{IVVSPE}$, so as to ensure the real-time performance of the DC bias suppression strategy.

Figure 7. Long-time no zero drift digital integrator circuit block diagram.

The long-time no zero drift digital integrator circuit is mainly composed of (1) Signal Acquisition Circuit, (2) Signal Pre-processing Circuit, and (3) Integral Operation Circuit. The main functions of each part are as follows:

• Signal Acquisition Circuit:
  The main function of this part is to sample the input voltage $v_1$, where $f_1=20$ kHz, $V_1=537$ V. Considering that the main transformer in the arc welding inverter can be approximated to an ideal high precision voltage sensor. Therefore, a simple voltage detection method is proposed to realize the accurate synchronous sampling for the $v_1$, in which an additional winding $N_3$ is wound on the main transformer core to convert $v_1$ into a low-voltage small signal $v_3$, where $V_3=12$ V, $N_3:N_1=1:50$. The actual waveforms are shown in Figure 8.
  

  Figure 8. The waveforms of $v_1\left(CH1\right)$ and $v_3\left(CH3\right)$.
  CH1 represents the input voltage waveform $v_1$ of the transformer, and the parameters of $v_1$ are: $T=50$ us, $D_{+}=D_{-}=D_0=10\%$, $V_1=537$ V. CH3 represents the output voltage waveform $v_3$ of the additional winding, the parameters are: $T=50$ us, $D_{+}=D_{-}=D_0=10\%$, $V_3=12$ V. Therefore, there is a very good relationship between the waveform $v_1$ and $v_3$, so that the DC bias state, including the direction and depth, can be evaluated according to the change of $v_3$.
• Signal Pre-processing Circuit:
  The main function of this circuit is to preprocess the sampled signal $v_3$ to obtain the DC pulse square wave signals $V_{d1}$, $V_{d2}$ and the 16-bit parallel signal $DB [15:0]$.
  The Zero Cross Detection Circuit (a) is used to convert $v_3$ in the positive half-wave, and the duty cycle of the output voltage signal $V_{d1}$ is equal to the positive half-wave of $v_3$. Similarly, the Zero Cross Detection Circuit (b) is used to convert $v_3$ in the negative half-wave, and the duty cycle of the output voltage signal $V_{d2}$ is equal to the negative half-wave of $v_3$.
  Finally, the Analog-to-Digital Conversion (ADC) Circuit is to perform the analog-to-digital conversion on the amplitude of $v_3$, the key parameters of the ADC module are shown in Table 1. Considering that the analog input range of the ADC module is 0∼$2.7$ V p-p, it is necessary to rectify and step-down the input signal $v_3$ to get the DC pulse voltage waveform ${v^{\prime }}_3$, and then perform the analog-to-digital conversion, where the output of the ADC module is a set of 16-bit parallel pulse sequences $DB0,\dots ,DB15$. The key waveforms are shown in Figure 9.
  Table 1. The main parameters of the high-speed parallel analog-to-digital converter (ADC).

  Channels	Sampling Rate	Sampling Bits	Input Voltage Range
  1	105 MSPS	16 bit	0∼$2.7$ V p-p

  

  Figure 9. The key waveforms of the Signal Pre-processing Circuit.
  In Figure 9, CH1 is the waveform of the input voltage waveform $v_3$, CH2 and CH3 represent the output voltage waveform $V_{d1}$ and $V_{d2}$ of the Zero Cross Detection Circuit (a) and (b), respectively, and CH4 represent the output voltage waveform ${v^{\prime }}_3$ of the Rectifier and Step-Down Circuit.
• Integral Operation Circuit:
  The main function of this part is to calculate the integral value of volt-second product error. $V_{d1}$ and $V_{d2}$ is the output voltage of the Zero Cross Detection Circuit (a) and (b), respectively. While the 16-bit parallel input ports $I{O}_1$∼$I{O}_{16}$ accepts the output of the ADC module. In order to improve the computing speed of $e_{IVVSPE}$, a parallel operation logic is constructed in FPGA, and the parallel thread structure diagram is shown in Figure 10.
  

  Figure 10. The structure diagram of the parallel operation for integral operation.
  The parallel operation logic is composed of 4 threads:
  • Thread 1. Duty cycle counter:
    When the input variable $V_{d1}$ or $V_{d2}$ changes from Low to High, the 50 MHz counter $CLK$ starts counting, and then, if $V_{d1}$ or $V_{d2}$ changes from High to Low, the count result is assigned to $n_P$ or $n_N$, the Thread 1 termination. Considering that the frequency of the counter is 50 MHz and the switching frequency is 20 kHz, so that $n_P$ and $n_N$ are a certain value, ranging from 0 to 2500. For example, in Figure 10, the duty cycle of positive and negative half-wave is $D_{+}=D_{-}=D_0$; therefore, the counting results of $V_{d1}$ and $V_{d2}$ is:

    $$\left\{\begin{array}{c}{n}_P=2500·D_{+}=2500·D_0\hfill \\ n_N=2500·D_{-}=2500·D_0\hfill \end{array}.\right.$$

    (10)
  • Thread 2. Amplitude calculation:
    When $V_{d1}$ or $V_{d2}$ changes from Low to High, the Amplitude Calculation Thread begins to work, the amplitude of $v_1$ is calculated according to the output signals $DB0$∼$DB15$ of ADC module. In the positive half-wave, the amplitude calculation result is stored in register $P\left(P_{n_1},\dots ,P_{n_P}\right)$, and then, in the negative half-wave, the amplitude calculation result is stored in register $N\left(N_{n_1},\dots ,N_{n_N}\right)$,
    In addition, in the full-bridge DC-DC converter, when the IGBT switches from on state to off state, a Ringing Waveform will be generated in the output voltage waveform, as shown in Figure 9. However, the amplitude of the Ringing Waveform is relatively small and symmetrical about the zero axis; therefore, its influence on the calculation of the volt-second product error can be ignored. In Figure 7, the input threshold voltage of the Photocoupler in Figure 7 is about $0.7V$. Therefore, when $v_3<0.7V$, the output of the photocoupler is in the cut-off state, so that the Ringing Waveform in $v_3$ is filtered out. As shown in Figure 9, when IGBT is turned off, $V_{d1}$ or $V_{d2}$ will change from High to Low ($A\to B$ or $C\to D$), at this point, both Thread 1 and Thread 2 are terminated.
  • Thread 3. Volt-second product error calculation:
    When Thread 1 and Thread 2 are terminated, according to the definition of volt-second product error in Equation (3), the volt-second product error in the switching period $T_i$ can be calculated:

    $${\overline{v}}_i=\sum _{j=1}^{n_P}{P}_j-\sum _{j=1}^{n_N}{N}_j.$$

    (11)
    Assume that the amplitude of $v_1$ in the positive and negative half waves is $V_1$, then Equation (11) can be further written as:

    $${\overline{v}}_i=\sum _{j=1}^{n_P}{V}_1-\sum _{j=1}^{n_N}{V}_1=2500·\left(D_{+}-D_1\right)V_1.$$

    (12)
  • Thread 4. Integral of volt-second product error:
    According to the calculation result of volt-second product error in Thread 3 and the definition of integral of volt-second product error in Equation (9), the ${\left(e_{IVVSPE}\right)}_i$ can be calculated:

    $$\begin{array}{c}{\left(e_{IVVSPE}\right)}_i={\left(e_{IVVSPE}\right)}_{i-1}+{\overline{v}}_i\hfill \end{array}.$$

    (13)

3.3. Control Strategy

The block diagram of the control strategy for DC bias suppression strategy is shown in Figure 11.

Figure 11. The block diagram of the DC bias suppression strategy.

In Figure 11, the integral value of volt-second product error $e_{IVVSPE}$ is used to evaluate the degree of DC bias, and the relationship between $e_{IVVSPE}$ and DC bias degree can be defined as:

$$\begin{array}{c}{e}_{IVVSPE}\in \left(MIVVSP{E}_{+},+\infty \right):DCbias,Positive,Saturation\hfill \\ e_{IVVSPE}\in \left(0,MIVVSP{E}_{+}\right):DCbias,Positive\hfill \\ e_{IVVSPE}=0:NoDCbias\hfill \\ e_{IVVSPE}\in \left(MIVVSP{E}_{-},0\right):DCbias,Negative\hfill \\ e_{IVVSPE}\in \left(-\infty ,MIVVSP{E}_{-}\right):DCbias,Negative,Saturation\hfill \end{array}.$$

(14)

According to Equation (14), when the integral value of volt-second product error $e_{IVVSPE}$ reaches and exceeds the Maximum Integral Value of Volt-Second Product Error $MIVVSP{E}_{+}$ or $MIVVSP{E}_{-}$, the transformer enters the critical saturation state. In order to prevent transformer from entering the saturation state, the DC bias suppression strategy proposed in this paper will be triggered. The details are as follows:

• The positive DC bias suppression strategy.
  When ${\left(e_{IVVSPE}\right)}_i\ge MIVVSP{E}_{+}$, the transformer will enter the positive critical saturation state, in order to prevent the transformer from entering the positive saturation state, the positive DC bias suppression strategy is triggered, and the corresponding parallel thread sequence block diagram is shown in Figure 12.
  

  Figure 12. The block diagram of the parallel operation for positive DC bias suppression strategy.
  In Figure 12, the integral value of volt-second product error increases positively, due to the asymmetry of the circuit parameters in the full-bridge DC-DC converter, such as the gate drive signal, the turn-on/turn-off delay, and the on-resistance in of the IGBTs, so that ${\left(e_{IVVSPE}\right)}_i\ge MIVVSP{E}_{+}$. In order to reset ${\left(e_{IVVSPE}\right)}_i$ quickly, and prevent the transformer from entering the positive saturation state, the duty cycle of $v_1$ in the switching period $T_{i+1}$ is adjusted, where the positive duty cycle decreases by $D_{+}-\Delta D$, and the negative duty cycle increases by $D_{-}+\Delta D$, $D_{+}=D_{-}=D_0$; therefore, $n_P=2500\left(D_0-\Delta D\right)$, $n_N=2500\left(D_0+\Delta D\right)$, so that the integral value of volt-second product error will be reset in the switching period $T_{i+1}$:

  $${\left(e_{IVVSPE}\right)}_{i+1}={\left(e_{IVVSPE}\right)}_i+\sum _{j=1}^{2500\left(D_0-\Delta D\right)}{P}_j-\sum _{j=1}^{2500\left(D_0+\Delta D\right)}{N}_j=0.$$

  (15)
  It should be noted that, when using duty cycle modulation technology to achieve DC bias suppression, large range step change of duty cycle within a switching period should be avoided, especially in one direction; otherwise, the transient dc bias will occur [23]. Therefore, in order to avoid this problem, the positive and negative half-wave duty cycle is adjusted by equal amplitude in reverse direction, as shown in Figure 12.
• The negative DC bias suppression strategy.
  When ${\left(e_{IVVSPE}\right)}_i\le MIVVSP{E}_{-}$, the transformer will enter the negative saturation state, in order to prevent the transformer from entering the negative saturation state, the negative DC bias suppression strategy is triggered, and the corresponding parallel thread sequence block diagram is shown in Figure 13.
  

  Figure 13. The block diagram of the parallel operation for negative DC bias suppression strategy.
  In Figure 13, the integral value of volt-second product error increases negatively, and ${\left(e_{IVVSPE}\right)}_i\le MIVVSP{E}_{-}$. In order to reset ${\left(e_{IVVSPE}\right)}_i$ quickly, and prevent transformer from entering the negative saturation state, the duty cycle of $v_1$ in the switching period $T_{i+1}$ is adjusted, where the positive duty cycle increases by $D_{+}+\Delta D$, and the negative duty cycle decreases by $D_{-}-\Delta D$, $D_{+}=D_{-}=D_0$; therefore, $n_P=2500\left(D_0+\Delta D\right)$, $n_N=2500\left(D_0-\Delta D\right)$, so that the integral value of volt-second product error is reset in the switching period $T_{i+1}$:

  $${\left(e_{IVVSPE}\right)}_{i+1}={\left(e_{IVVSPE}\right)}_i+\sum _{j=1}^{2500\left(D_0+\Delta D\right)}{P}_j-\sum _{j=1}^{2500\left(D_0-\Delta D\right)}{N}_j=0.$$

  (16)

3.4. Innovation and Advantages

The innovation is that the main transformer in the full-bridge DC-DC converter is used to measure high frequency and high voltage signal $v_1$. Compared with the traditional Hall sensor measurement method, due to the magnetic core of the main transformer is large enough, the sampling method in Figure 7 has almost no signal distortion problem. Therefore, the signal sampling method proposed in this paper simplifies the circuit structure and improves the feedback accuracy.

The advantage is mainly reflected in the ability of the suppression strategy to restrain the saturation problem. Compared with the traditional current feedback control method, the suppression strategy can only be triggered after the transformer enters the saturation state. However, the volt-second product error integral feedback control method proposed in this paper will be triggered before saturation, which can completely eliminate the saturation problem.

4. Experimental Verification

In order to verify the DC bias suppression strategy proposed in this article, a 30 kW single-phase full-bridge DC-DC converter for the arc welding platform is established, as shown in Figure 14.

Figure 14. Experiment platform.

The relevant parameters of the experiment platform are shown in Table 2. And three comparative experiments are given below, to illustrate the advantages of the proposed DC bias suppression strategy.

Table 2. The main parameters of the arc welding platform.

Symbol	Quantity	Value
$V_1$	Full-bridge converter input voltage	$380\sqrt{2}\approx 537$ V
$V_o$	Rated output voltage	60 V
$I_o$	Rated output current	500 A
$P_o$	Rated power	30 kW
$N_1:N_2$	Transformer turns ratio	3:1
$f_s$	Switching frequency	20 kHz
$\left(0,MIVVSP{E}_{+}\right)$	Positive DC bias correction region	$+400V_1$
$\left(MIVVSP{E}_{-},0\right)$	Negative DC bias correction region	$-400V_1$

4.1. No DC Bias Experiment

In this experiment, the full-bridge DC-DC converter is running in a steady state, and the primary input voltage $v_1$ is in a standard AC square wave, where $D_{+}=D_{-}=D_0=10\%$, $V_1=537$ V. The key waveforms are shown in Figure 15.

Figure 15. The key waveform of inverter without DC bias.

CH1 represents the primary input voltage $v_1$, CH2 and CH3 represents the output signals $V_{d1}$ and $V_{d2}$, and CH4 is the current through the primary winding $i_Q$.

4.2. DC Bias Experiment

In practical application, the duty cycle asymmetry is one of the main reasons for the saturation fault of arc welding inverter. Therefore, to simulate this case, a duty cycle disturbance variable $\widehat{D}=4\%$ is introduced into the negative half-wave from the switching period $T_1$, so that the negative half-wave duty cycle is increased to $D_{-}=16\%$. The key waveforms are shown in Figure 16.

Figure 16. The key waveform of negative DC bias.

In Figure 16, due to the introduction of $\widehat{D}$, the volt-second product error accumulates in the negative direction, the transformer enters negative DC bias state, according to Equation (10):

$$\left\{\begin{array}{c}{n}_P=2500·D_{+}=2500·12\%=300\hfill \\ n_N=2500·D_{-}=2500·16\%=400\hfill \end{array}.\right.$$

(17)

Furthermore, according to Equations (12) and (17), the volt-second product error in the switching period $T_i$ can be calculated:

$${\overline{v}}_i=\sum _{j=1}^{300}{V}_1-\sum _{j=1}^{400}{V}_1=-100V_1,i=1,2,\dots .$$

(18)

And then, according to Equations (9) and (18), the integral value of volt-second product error in the switching period $T_4$ is:

$${\left(e_{IVVSPE}\right)}_4={\sum }_{i=1}^4{\overline{v}}_i=4·\left(-100V_1\right)=-400V_1.$$

(19)

Since $MIVVSP{E}_{-}=-400V_1$, ${\left(e_{IVVSPE}\right)}_4\le MIVVSP{E}_{-}$. According to Equation (13) and the proposed DC bias suppression strategy, we can predict that the transformer will enter negative saturation state in $T_5$, and a current pulse will be generated in the negative half-wave of $i_Q$ and reach the maximum value $I_{peak5}$ at the moment $t=T/\phantom{T2}2+D_{-}$. When $T/\phantom{T2}2+D_{-}<t<T$, the switching period enters the negative half-wave continuous flow stage, with the rapid attenuation of $I_{peak5}$, a reverse induction electromotive force with an equivalent duty cycle of $\Delta d\approx 3\%$ will be induced in the transformer, where the induced electromotive force belongs to the positive pulse width. Therefore, the counting results of $V_{d1}$ and $V_{d2}$ in $T_5$ is:

$$\left\{\begin{array}{c}{n}_P=2500·\left(D_{+}+\Delta d\right)=2500·\left(12\%+3\%\right)=2500·15\%=375\hfill \\ n_N=2500·D_{-}=2500·16\%=400\hfill \end{array}.\right.$$

(20)

Then, the volt-second product error in the switching period $T_5$ can be calculated:

$${\overline{v}}_5=\sum _{j=1}^{n_P}{P}_j-\sum _{j=1}^{n_N}{N}_j=\sum _{j=1}^{375}{V}_1-\sum _{j=1}^{400}{V}_1=-25V_1.$$

(21)

Therefore, the actual integral value of volt-second product error in the switching period $T_5$ is:

$${\left(e_{IVVSPE}\right)}_5={\sum }_{i=1}^4{\overline{v}}_i+{\overline{v}}_5=4·\left(-100V_1\right)-25V_1=-425V_1.$$

(22)

According to the calculation results of Equation (22), ${\left(e_{IVVSPE}\right)}_5\le MIVVSP{E}_{-}$. Moreover, in Figure 16, after the switching period $T_4$, there is a spike current in the negative half-wave of $i_Q$. Therefore, the prediction for transformer saturation is valid.

4.3. DC Bias Suppression Experiment

In this experiment, compared with the traditional current feedback control mode, the volt-second product error integral feedback control mode is better in suppressing the DC bias and can completely eliminate the problem of transformer saturation.

• The traditional current feedback control mode.
  In the traditional current feedback control strategy, if the current peak $I_{peak}$ caused by transformer saturation is greater than the preset reference current $I_{ref}$, the traditional DC bias suppression strategy is triggered, and then the duty cycle modulation method is used to correct the saturation state. The experimental results are shown in Figure 17.
  

  Figure 17. The experimental results of the traditional current feedback control method.
  In Figure 17, in order to compare the experimental results conveniently, the DC bias condition is the same as experiment 2, the transformer enters negative DC bias state, and when $I_{peak9}$ is greater than $I_{\mathrm{ref}}$, the traditional DC bias suppression strategy is triggered, and then, in the next two switching cycles, the positive half-wave duty cycle increases to $30\%$, while the negative duty cycle decreases to $0\%$; thus, the DC bias state is corrected.
• The volt-second product error integral feedback control mode.
  Under the same DC bias condition as experiment 2, if the transformer enters the critical saturation state, the DC bias suppression strategy proposed in this paper is applied, and the experimental results are shown in Figure 18.
  

  Figure 18. The experimental results of the volt-second product error integral feedback control mode.
  According to Equation (19), ${\left(e_{IVVSPE}\right)}_4=-400V1=MIVVSPE\_$, the transformer enters the negative critical saturation state. In order to prevent the transformer from entering the saturation state, the negative DC bias suppression strategy proposed in this paper is implemented. Therefore, in the switching cycle $T_5$, the duty cycle increment is:

  $$\Delta D=\left|\frac{{\left(e_{IVVSPE}\right)}_4}{2·2500V1}\right|=\left|\frac{-400V1}{2·2500V1}\right|=8\%,$$

  (23)

  and then, in the switching period $T_5$, the positive duty cycle increases to $D_{+}+\Delta D=20\%$, while the negative duty cycle decreases to $D_{-}-\Delta D=4\%$. According to the Figure 18, there is no pulse current in the $i_Q$ waveform.

According to the experimental results in Figure 16, Figure 17 and Figure 18, under the same DC bias condition, the DC bias suppression strategy proposed in this paper can completely eliminate transformer saturation. Furthermore, when the DC bias suppression strategy is triggered, the adjustment mode and depth in duty cycle is based on the preset of $MIVVSP{E}_{-}$ or $MIVVSP{E}_{+}$, while the size of $MIVVSP{E}_{-}$ and $MIVVSP{E}_{+}$ is determined by balancing the saturation risk and adjustment frequency. Therefore, the DC bias suppression strategy proposed in this paper has very good robustness in suppressing transformer saturation and can improve the anti-saturation ability of the single-phase full-bridge DC-DC converter.

5. Conclusions

A duty cycle modulation method for eliminating DC bias of single-phase full-bridge DC-DC converter is proposed in this paper. The magnetic saturation problem of transformer is effectively eliminated, and the operation stability of arc welding inverter is improved. Based on the detailed analysis of the saturation mechanism of transformer, the conditions for realizing zero DC bias and the closed-loop control model for adjusting the Maximum Integral Value of Volt-Second Product Error are given. In order to realize the integral operation of volt-second product error of transformer input voltage signal, a novel digital integration circuit with long-time no zero drift is proposed. When the Maximum Integral Value of Volt-Second Product Error reaches the trigger condition of the DC bias suppression strategy, the DC bias can be quickly corrected by adjusting the duty cycle of the H-bridge power switch drive signal. The experimental results verify the effectiveness of the method in preventing transformer saturation.