A Novel DC Bias Suppression Strategy for Single-Phase Full-Bridge DC-DC Arc Welding Converter
Abstract
:1. Introduction
2. Generation Mechanism of MIVVSPE
2.1. Saturation Mechanism Analysis
2.2. Derivation of MIVVSPE
3. Proposed Suppression Strategy
3.1. Construction of Closed-Loop Controller
3.2. Synchronous Sampling and Integrator Circuit
- Signal Acquisition Circuit:The main function of this part is to sample the input voltage , where kHz, V. Considering that the main transformer in the arc welding inverter can be approximated to an ideal high precision voltage sensor. Therefore, a simple voltage detection method is proposed to realize the accurate synchronous sampling for the , in which an additional winding is wound on the main transformer core to convert into a low-voltage small signal , where V, . The actual waveforms are shown in Figure 8.CH1 represents the input voltage waveform of the transformer, and the parameters of are: us, , V. CH3 represents the output voltage waveform of the additional winding, the parameters are: us, , V. Therefore, there is a very good relationship between the waveform and , so that the DC bias state, including the direction and depth, can be evaluated according to the change of .
- Signal Pre-processing Circuit:The main function of this circuit is to preprocess the sampled signal to obtain the DC pulse square wave signals , and the 16-bit parallel signal .The Zero Cross Detection Circuit (a) is used to convert in the positive half-wave, and the duty cycle of the output voltage signal is equal to the positive half-wave of . Similarly, the Zero Cross Detection Circuit (b) is used to convert in the negative half-wave, and the duty cycle of the output voltage signal is equal to the negative half-wave of .Finally, the Analog-to-Digital Conversion (ADC) Circuit is to perform the analog-to-digital conversion on the amplitude of , the key parameters of the ADC module are shown in Table 1. Considering that the analog input range of the ADC module is 0∼ V p-p, it is necessary to rectify and step-down the input signal to get the DC pulse voltage waveform , and then perform the analog-to-digital conversion, where the output of the ADC module is a set of 16-bit parallel pulse sequences . The key waveforms are shown in Figure 9.In Figure 9, CH1 is the waveform of the input voltage waveform , CH2 and CH3 represent the output voltage waveform and of the Zero Cross Detection Circuit (a) and (b), respectively, and CH4 represent the output voltage waveform of the Rectifier and Step-Down Circuit.
- Integral Operation Circuit:The main function of this part is to calculate the integral value of volt-second product error. and is the output voltage of the Zero Cross Detection Circuit (a) and (b), respectively. While the 16-bit parallel input ports ∼ accepts the output of the ADC module. In order to improve the computing speed of , a parallel operation logic is constructed in FPGA, and the parallel thread structure diagram is shown in Figure 10.The parallel operation logic is composed of 4 threads:
- Thread 1. Duty cycle counter:When the input variable or changes from Low to High, the 50 MHz counter starts counting, and then, if or changes from High to Low, the count result is assigned to or , the Thread 1 termination. Considering that the frequency of the counter is 50 MHz and the switching frequency is 20 kHz, so that and are a certain value, ranging from 0 to 2500. For example, in Figure 10, the duty cycle of positive and negative half-wave is ; therefore, the counting results of and is:
- Thread 2. Amplitude calculation:When or changes from Low to High, the Amplitude Calculation Thread begins to work, the amplitude of is calculated according to the output signals ∼ of ADC module. In the positive half-wave, the amplitude calculation result is stored in register , and then, in the negative half-wave, the amplitude calculation result is stored in register ,In addition, in the full-bridge DC-DC converter, when the IGBT switches from on state to off state, a Ringing Waveform will be generated in the output voltage waveform, as shown in Figure 9. However, the amplitude of the Ringing Waveform is relatively small and symmetrical about the zero axis; therefore, its influence on the calculation of the volt-second product error can be ignored. In Figure 7, the input threshold voltage of the Photocoupler in Figure 7 is about . Therefore, when , the output of the photocoupler is in the cut-off state, so that the Ringing Waveform in is filtered out. As shown in Figure 9, when IGBT is turned off, or will change from High to Low ( or ), at this point, both Thread 1 and Thread 2 are terminated.
- Thread 3. Volt-second product error calculation:When Thread 1 and Thread 2 are terminated, according to the definition of volt-second product error in Equation (3), the volt-second product error in the switching period can be calculated:Assume that the amplitude of in the positive and negative half waves is , then Equation (11) can be further written as:
- Thread 4. Integral of volt-second product error:According to the calculation result of volt-second product error in Thread 3 and the definition of integral of volt-second product error in Equation (9), the can be calculated:
3.3. Control Strategy
- The positive DC bias suppression strategy.When , the transformer will enter the positive critical saturation state, in order to prevent the transformer from entering the positive saturation state, the positive DC bias suppression strategy is triggered, and the corresponding parallel thread sequence block diagram is shown in Figure 12.In Figure 12, the integral value of volt-second product error increases positively, due to the asymmetry of the circuit parameters in the full-bridge DC-DC converter, such as the gate drive signal, the turn-on/turn-off delay, and the on-resistance in of the IGBTs, so that . In order to reset quickly, and prevent the transformer from entering the positive saturation state, the duty cycle of in the switching period is adjusted, where the positive duty cycle decreases by , and the negative duty cycle increases by , ; therefore, , , so that the integral value of volt-second product error will be reset in the switching period :It should be noted that, when using duty cycle modulation technology to achieve DC bias suppression, large range step change of duty cycle within a switching period should be avoided, especially in one direction; otherwise, the transient dc bias will occur [23]. Therefore, in order to avoid this problem, the positive and negative half-wave duty cycle is adjusted by equal amplitude in reverse direction, as shown in Figure 12.
- The negative DC bias suppression strategy.When , the transformer will enter the negative saturation state, in order to prevent the transformer from entering the negative saturation state, the negative DC bias suppression strategy is triggered, and the corresponding parallel thread sequence block diagram is shown in Figure 13.In Figure 13, the integral value of volt-second product error increases negatively, and . In order to reset quickly, and prevent transformer from entering the negative saturation state, the duty cycle of in the switching period is adjusted, where the positive duty cycle increases by , and the negative duty cycle decreases by , ; therefore, , , so that the integral value of volt-second product error is reset in the switching period :
3.4. Innovation and Advantages
4. Experimental Verification
4.1. No DC Bias Experiment
4.2. DC Bias Experiment
4.3. DC Bias Suppression Experiment
- The traditional current feedback control mode.In the traditional current feedback control strategy, if the current peak caused by transformer saturation is greater than the preset reference current , the traditional DC bias suppression strategy is triggered, and then the duty cycle modulation method is used to correct the saturation state. The experimental results are shown in Figure 17.In Figure 17, in order to compare the experimental results conveniently, the DC bias condition is the same as experiment 2, the transformer enters negative DC bias state, and when is greater than , the traditional DC bias suppression strategy is triggered, and then, in the next two switching cycles, the positive half-wave duty cycle increases to , while the negative duty cycle decreases to ; thus, the DC bias state is corrected.
- The volt-second product error integral feedback control mode.Under the same DC bias condition as experiment 2, if the transformer enters the critical saturation state, the DC bias suppression strategy proposed in this paper is applied, and the experimental results are shown in Figure 18.According to Equation (19), , the transformer enters the negative critical saturation state. In order to prevent the transformer from entering the saturation state, the negative DC bias suppression strategy proposed in this paper is implemented. Therefore, in the switching cycle , the duty cycle increment is:
5. Conclusions
Author Contributions
Funding
Institutional Review Board Statement
Informed Consent Statement
Data Availability Statement
Conflicts of Interest
Abbreviations
MIVVSPE | Maximum Integral Value of Volt-Second Product Error |
IGBT | Insulated Gate Bipolar Transistor |
FPGA | Field-Programmable Gate Array |
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Channels | Sampling Rate | Sampling Bits | Input Voltage Range |
---|---|---|---|
1 | 105 MSPS | 16 bit | 0∼ V p-p |
Symbol | Quantity | Value |
---|---|---|
Full-bridge converter input voltage | V | |
Rated output voltage | 60 V | |
Rated output current | 500 A | |
Rated power | 30 kW | |
Transformer turns ratio | 3:1 | |
Switching frequency | 20 kHz | |
Positive DC bias correction region | ||
Negative DC bias correction region |
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Zhou, Y.; Qi, B.; Zheng, M.; Cong, B. A Novel DC Bias Suppression Strategy for Single-Phase Full-Bridge DC-DC Arc Welding Converter. Electronics 2021, 10, 428. https://doi.org/10.3390/electronics10040428
Zhou Y, Qi B, Zheng M, Cong B. A Novel DC Bias Suppression Strategy for Single-Phase Full-Bridge DC-DC Arc Welding Converter. Electronics. 2021; 10(4):428. https://doi.org/10.3390/electronics10040428
Chicago/Turabian StyleZhou, Yang, Bojin Qi, Minxin Zheng, and Baoqiang Cong. 2021. "A Novel DC Bias Suppression Strategy for Single-Phase Full-Bridge DC-DC Arc Welding Converter" Electronics 10, no. 4: 428. https://doi.org/10.3390/electronics10040428
APA StyleZhou, Y., Qi, B., Zheng, M., & Cong, B. (2021). A Novel DC Bias Suppression Strategy for Single-Phase Full-Bridge DC-DC Arc Welding Converter. Electronics, 10(4), 428. https://doi.org/10.3390/electronics10040428