A Low Power 1024-Channels Spike Detector Using Latch-Based RAM for Real-Time Brain Silicon Interfaces
Abstract
:1. Introduction
2. Materials and Methods
2.1. Evaluation Metrics
2.2. Dataset
2.3. Algorithm Design
2.3.1. Band-Pass Filter
2.3.2. Enhancing Block: ASO
2.3.3. Threshold: WA
- a preliminary evaluation of standard deviation is performed. It can be done by using average or root mean square. We used the one referred as AA in [19].
- the clipping procedure consists of comparing the previous calculated standard deviation with the absolute value of the new incoming sample and replacing this latter if it is higher than the standard deviation.
- finally, the clipped signal is used to update the threshold. The new estimate is then used for the clipping. The evaluation of the threshold is described in Equation (7).
2.4. Algortihm Implementation
2.4.1. Filters: BPF and Smoothing
2.4.2. Latch-Based RAM
2.4.3. Others
3. Results
3.1. Software Evaluation
3.2. Hardware Evalution
- proposed1: an architecture based on flip-flops as storage elements (without latch-based RAM) and with Hamming smoothing windows.
- proposed2: like proposed1 but using latch-based RAM as a storage element.
- proposed3: like proposed2, replacing the Hamming window with the equivalent IIR filter.
4. Discussion
5. Conclusions
Author Contributions
Funding
Data Availability Statement
Acknowledgments
Conflicts of Interest
References
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Coefficients | Rounding Error (%) | |||||
---|---|---|---|---|---|---|
0 | 1 | 2 | 0 | 1 | 2 | |
a | 1 | −0.720 | −0.125 | 0 | 0.061 | 0.414 |
b | 0.291 | 0 | −0.291 | 0.027 | 0 | 0.027 |
Coefficients | Rounding Error (%) | |||||||||
---|---|---|---|---|---|---|---|---|---|---|
0 | 1 | 2 | 3 | 4 | 0 | 1 | 2 | 3 | 4 | |
a | 1 | −1.839 | 0.492 | 0.812 | −0.437 | 0 | 0.195 | 0.013 | −0.189 | −0.049 |
b | 0.007 | −0.003 | −0.003 | 0.001 | 0.003 | 0.172 | 0.008 | 0.118 | −0.089 | 0.026 |
Consumption | Proposed1 | Proposed2 | Proposed3 |
---|---|---|---|
Power (mW) | 8.3 | 6.4 | 3.6 |
Area (mm2) | 7.5 | 5.4 | 2.3 |
This Work | [35] | [20] | [8] | |
---|---|---|---|---|
N. of channels | 1024 | 1 | 1 | 1 |
Sensibility (TPR %) 1 | >80% | 70–95% | >80% | >80% |
Adaptive Threshold | Y | N | Y | Y |
Feature | ASO | NEO-ED/CM 2 | ASO | ED |
Domain | Digital | Digital | Digital | Analog |
Technology | CMOS 28 nm | FPGA-28 nm | Embedded | CMOS 180 nm |
Power Density (µW/channel) | 3.6 | 460 × 103 | 120 | 5.1 |
Area Density (mm2/channel) | 0.0022 | N. A | N. A | 0.0018 |
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Saggese, G.; Strollo, A.G.M. A Low Power 1024-Channels Spike Detector Using Latch-Based RAM for Real-Time Brain Silicon Interfaces. Electronics 2021, 10, 3068. https://doi.org/10.3390/electronics10243068
Saggese G, Strollo AGM. A Low Power 1024-Channels Spike Detector Using Latch-Based RAM for Real-Time Brain Silicon Interfaces. Electronics. 2021; 10(24):3068. https://doi.org/10.3390/electronics10243068
Chicago/Turabian StyleSaggese, Gerardo, and Antonio Giuseppe Maria Strollo. 2021. "A Low Power 1024-Channels Spike Detector Using Latch-Based RAM for Real-Time Brain Silicon Interfaces" Electronics 10, no. 24: 3068. https://doi.org/10.3390/electronics10243068
APA StyleSaggese, G., & Strollo, A. G. M. (2021). A Low Power 1024-Channels Spike Detector Using Latch-Based RAM for Real-Time Brain Silicon Interfaces. Electronics, 10(24), 3068. https://doi.org/10.3390/electronics10243068