Conception and Simulation of a 2-Then-1-Bit/Cycle Noise-Shaping SAR ADC
Round 1
Reviewer 1 Report
The symbol for the ADC in Fig. 2 is not very clear and should be changed.
Vsigp and Vsign on page 3 are not defined.
Fig. 3b and Fig.3c are not readable in black and white.
Can you comment on the PSRR for the case you short the tail nodes? Page 7, last paragraph?
Comparison with state-of-the-art is too short, as only two other publications are listed. Please, provide a better, more comprehensive list of SAR ADCs.
Please comment, why it is enough to include only 1% mismatch for the CDAC? Is this really enough?
Author Response
Point1: The symbol for the ADC in Fig 2 is not clear and should be changed.
Response 1
=> Thank you for pointing it out. For better explanation, we modified Fig.2 representing the proposed ADC. The modified Fig. 2 is as follows.
Point 2: Vsigp and Vsign on page 3 are not defined.
Response 2
=> Vsigp and Vsign represent the top-plate voltage of the signal CDAC that are connected to the comparator input. These values have information about the sampled input signal and they are changed according to the binary search algorithm as in the conventional SAR ADC. The definition is added to the manuscript Section 2.1 line 71-72.
Point 3: Fig. 3b and Fig.3c are not readable in black and white.
Response 3
=> We re-mastered Fig 3 to make them readable even in black and white version. The modified Fig. 3 is as follows.
Point 4: Can you comment on the PSRR for the case you short the tail nodes? Page 7, last paragraph?
Response 4
=>First, both the signal part and the reference part are implemented in a differential manner in a tail-current-sharing comparator, so the performance will be barely affected by the supply voltage change. In addition, the signal part and the reference part share the same supply voltage, which means they will have the same PSRR. Therefore, the proposed ADC is robust to the effect of PSRR. This explanation is added to the manuscript Section 3.4 line 212-214.
Point 5: Comparison with state-of-the-art is too short, as only two other publications are listed. Please, provide a better, more comprehensive list of SAR ADCs.
Response 5
=> We added three prior works to compare the performance of the proposed ADC and the existing ADCs based on SAR architecture. These works used 1-bit/cycle, 1-then-2-bit/cycle and 1-bit/cycle noise-shaping architectures, respectively.
Point 6: Please comment, why it is enough to include only 1% mismatch for the CDAC? Is this really enough?
Response 6
=> We implemented the layout of the unit capacitor in various shapes, and measured systematic mismatch due to the imbalance of the surrounding environment of the unit capacitor through post layout simulation. As a result of post layout simulation, it was confirmed that the least mismatch of about 0.6% to 0.7% occurred when the CDAC layout used in [paper 1] was used. Since this does not account for random mismatch caused by the process, this article includes a 1% mismatch with a margin of about 0.3%. In addition, most SAR ADCs in low scale CMOS technology show mismatch much less than 1% these days. This explanation is added to the manuscript Section 4 line 223-225.
[paper 1] H. Zhuang et al., "A Fully Dynamic Low-Power Wideband Time-Interleaved Noise-Shaping SAR ADC," in IEEE Journal of Solid-State Circuits, vol. 56, no. 9, pp. 2680-2690, Feb. 2021, doi: 10.1109/JSSC.2021.3072034.
Author Response File: 
Author Response.pdf
Reviewer 2 Report
The topic of the paper seems to be okay. I agree with author’s point and approach that there needs to be some alternative that meets both bandwidth and noise.
However, the major issue is that the result is solely based on schematic simulation. Author probably already know that there will be a significant difference between schematic and actual measurement result from ASIC (due to process and mismatch variation). So, any result from schematic simulation is meaningless unless you do through investigation on those effects. Frankly speaking, I am amazed that you compared the simulation result with measurement result from chip!
1. I still think author should present actual measurement result, not simulation result. Especially because you are presenting SAR ADC (difference btw sim and measurement is significant). But at the same time, I am aware that tape-out cost can be very high. So I recommend to provide extensive results to make up for the lack of measurement data.
2. On page 9, author claim that “all simulations are performed with transistor level parasitic capacitance and resistance added”. This is very confusing. It looks like author didn’t do a layout and only presenting schematic simulations. How can you get parasitic information without layout?
In circuit-industry, the parasitic capacitance or resistance usually means that the parasitic came from actual layout. Did the author finished the layout for their design and ran a post-layout simulation to capture all possible parasitic? I am assuming “No” because author did not present any layout images, nor say they done a layout.
If author did do a layout, please mention that simulations are post-layout simulation in the first place. Also add supplemental materials.
3.What is the unit capacitance value of your CDAC? On page 9, author wrote as if they are using 1.2fF. But is it true? That seems very low to me. I would prefer have actual measurement result, but can you at least show the post-layout simulation?
4. When you were running Monte-carlo simulations, how many runs have you used? And what’s the sigma value you are getting? Please present the present gaussian distribution result that they got. If you just say “though a Monte-Carlo simulation”, there is no way for me to check if it is really true.
5. Please present INL and DNL result.
6. VrefP, VrefN are critical signals. ADC performance would vary depending on their variations. How are you generating those from your simulations?
7. Please measure SNDR with different input frequency
8. Please add more information on your process. Which foundry did you used? What’s the # of poly and metal layers?
Author Response
Point1: I still think author should present actual measurement result, not simulation result. Especially because you are presenting SAR ADC (difference btw sim and measurement is significant). But at the same time, I am aware that tape-out cost can be very high. So I recommend to provide extensive results to make up for the lack of measurement data.
Response 1
=> Thanks for pointing it out. As you said, we know that there can be a significant difference between actual measurement results and simulation results. The purpose of this article is to suggest a solution overcoming the shortcomings of SAR ADC through the combination of the existing architecture [reference 5] and [reference 7] and to prove it.
Regardless of the difference in the result between measurement and simulation, there is strong correlation between them. Therefore, even simulation result can demonstrate effectiveness of the proposed solution if there is a reference for comparison.
In table 1, we put simulation result from 1-bit/cycle noise-shaping and 2-then-1-bit/cycle noise-shaping SAR ADCs. They are implemented in the same CMOS process and they are targeting the same resolution for fair comparison. The proposed ADC shows faster conversion speed (60MHz BW vs 45MHz BW). The improvement might be less than it, but the speed improvement will be observed in measurement due to the correlation between measurement and simulation. So we believe this comparison by simulation is reasonable and put every key performance metric including power, BW and SNDR in Table 1.
[reference 5] Luo, J.; Liu, Y.; Li, J.; Ning, N.; Wu, K.; Liu, Z.; Yu, Q. A Low Voltage and Low Power 10-bit Non-Binary 2b/Cycle Time and Voltage Based SAR. IEEE Trans. Circuits Syst. I Regular Papers 2020, 67, 1136–1148.)
[reference 7] Lin, Y.; Lin, C.; Tsai, S.; Lu, C. 20.2 A 40MHz-BW 320MS/s passive Noise-Shaping SAR ADC With Passive Signal-Residue Summation in 14nm FinFET. In Proceedings of the IEEE International Solid-State Circuits Conference, San Francisco, USA, 17–21 February 2019.
Point 2: On page 9, author claim that “all simulations are performed with transistor level parasitic capacitance and resistance added”. This is very confusing. It looks like author didn’t do a layout and only presenting schematic simulations. How can you get parasitic information without layout?
Response 2
=> We used 28nm CMOS process from Samsung Foundry whose PDK provides an option enabling transistor level simulation including parasitic capacitance and resistance around the transistor. It does not count parasitics from metal routing that needs to be drawn by designers, but it still provides more accurate pre-layout simulation result based on P-Cell layout regression. If this option that is provided in recent low-scale CMOS processes is used, the error between pre-layout simulation and post-layout simulation is dramatically reduced. This explanation is added to the manuscript Section 3.4 line 220-222.
Point 3: What is the unit capacitance value of your CDAC? On page 9, author wrote as if they are using 1.2fF. But is it true? That seems very low to me. I would prefer have actual measurement result, but can you at least show the post-layout simulation?
Response 3
=> The total CDAC size is determined by thermal kT/C noise which should be less than the quantization noise of 2.1 mV2 in this work. To prevent the unit capacitor to become too small and be affected much by parasitics, the CDAC is sized quite large with a big margin, and the resulting CDAC size is 312fF showing kT/C noise of 13.269 nV2. This CDAC will have 1.2fF unit capacitors. ~1fF unit capacitor is very common in recent SAR ADCs and 1.2fF unit capacitors can be easily implemented by fringe capacitors and the layout extraction shows 10% parasitic components that barely affect the overall performance. The unit capacitor might be smaller than 1.2fF in a lower-scaled process (0.2fF possible in 14nm FinFet), but 1.2fF was optimal in 28nm CMOS process we used. This chosen value of CDAC also provides less than 1% mismatch. This explanation is added to the manuscript Section 4 line 223-225.
Point 4: When you were running Monte-Carlo simulations, how many runs have you used? And what’s the sigma value you are getting? Please present the present gaussian distribution result that they got. If you just say “though a Monte-Carlo simulation”, there is no way for me to check if it is really true.
Response 4
=> We performed 1000 Monte-Carlo simulations (using the information provided by PDK) each to measure the offset of the coarse signal comparator, coarse reference comparator and fine comparator. The resulting sigma values from the simulation are about 15 mV for coarse comparators and about 5 mV for fine comparators. The resolution of the offset calibration we used is 5 mV and 1 mV, respectively. Therefore, comparators operate with an offset of 5 mV and 1 mV or less, respectively. The following figure is the result of Monte-Carlo simulation.
Point 5: Please present INL and DNL result.
Point 7: Please measure SNDR with different input frequency
Response 5 & 7
=> INL and DNL errors are usually metrics for Nyquist-rate ADCs but have little significance for oversampling ADCs. For oversampling ADCs, the power spectral density is the most important result that shows most of the performance. Our proposed ADC belongs to oversampling ADCs, so we did not put INL or DNL result and showed only the power spectral density. For better quality as suggested, we added more simulation result that shows the SNDR versus input frequency. The simulation result shows the flat SNDR form 5 MHz to 60 MHz. The following figure is the result of SNDR versus input frequency.
Point 6: VrefP, VrefN are critical signals. ADC performance would vary depending on their variations. How are you generating those from your simulations?
Response 6
=> As you mentioned, I agree that the reference voltages (Vrefp and Vrefn) are important in ADCs. Therefore, a stable supply such as a low dropout (LDO) regulator is required to ensure high performance of the ADC. However, as mentioned earlier, this article aims to suggest and prove the direction of overcoming the shortcomings of SAR ADCs through the combination of existing structures. In the proposed ADC, an ideal voltage source is used without an additional block because the effect of the reference is applied to the proposed ADC in the same way as conventional SAR ADCs.
Point 8: Please add more information on your process. Which foundry did you used? What’s the # of poly and metal layers?
Response 8
=> We used Samsung 28nm CMOS process with 1 poly and 9 metal layers. It would be good to provide this information in the manuscript for readers but we are not sure if it is allowed because of the NDA between Samsung Foundry and our research group. So we will appreciate if you allow us not to put that information in the manuscript.
Reviewer 3 Report
The scientific and practical level of the article is high, corresponding to the level of the journal. The material is presented clearly and logically. The level of presentation of the material provides a complete understanding of the principle of operation of the device. The disadvantage of the described device is its complexity, but the possibility of its practical implementation using existing technologies eliminates this disadvantage. For a more complete demonstration of all the advantages of ADC, the article materials can be supplemented with information about the dependence of the speed of this converter on the bit depth of its output code. I believe that the article can be published in the journal.
Author Response
Point1: The scientific and practical level of the article is high, corresponding to the level of the journal. The material is presented clearly and logically. The level of presentation of the material provides a complete understanding of the principle of operation of the device. The disadvantage of the described device is its complexity, but the possibility of its practical implementation using existing technologies eliminates this disadvantage. For a more complete demonstration of all the advantages of ADC, the article materials can be supplemented with information about the dependence of the speed of this converter on the bit depth of its output code. I believe that the article can be published in the journal.
Response 1
=> We sincerely thank you for participating in the review of this article. As you said, we add the relationship between bit depth and speed of ADC as follows.
In the proposed ADC, the relationship between bit depth and speed is determined by the number of coarse conversion bits and fine conversion bits. Criteria for dividing coarse conversion and fine conversion are set in consideration of the amount of redundancy required to recover the error caused by jitter. As shown in [Reference 5], the error caused by jitter is determined by the difference in comparator input voltage, and the smaller the difference, the smaller the error caused by jitter. Whatever the target resolution is, the first comparison always compares the sampled signal with 1/4Vref, 3/4Vref, and thus the same jitter error occurs. Therefore, the required amount of redundancy is independent of the number of bits, so increasing the number of coarse conversion bits is effective in terms of conversion speed. This explanation is added to the manuscript Section 4 line 130-139
Round 2
Reviewer 2 Report
Thank you for your detailed response and changes into your manuscript. Although, author states that their sole simulation can demonstrate effectiveness of proposed solution, I totally disagree with their opinion.
I will straight go into the conclusion. Please pardon my harsh comments.
I am not going to accept the manuscript based on the current result. If you would like to get your manuscript accepted, please present either measurement or post-layout simulation result. If you are not going to do any of those, I’m not going accept your manuscript in any circumstances.
There are several reasons to this.
- I already mentioned this earlier, but there will be huge difference between your simulation and actual measurement result due to process variation and cross-coupling from the layout. Any brilliant simulation result is meaningless unless you consider all possible worst-case conditions.
Author stated “Regardless of the difference in the result between measurement and simulation, there is strong correlation between them. Therefore, even simulation result can demonstrate effectiveness of the proposed solution if there is a reference for comparison” in response 1, but I am totally alarmed by it.
If you were referring to your own past work, it might be true (although I wouldn’t buy it much). But you are actually referring to others work! Don’t you think they spend tremendous of time (on running PVT sim, careful layout, and post-layout simulation) to make strong correlation? How can you be so sure that you’ll get same measurement result from just running typical-case corners (with ideal voltage source)? Shouldn’t you spend similar effort like others?
Author may argue that their work so similar to other references that it doesn’t need additional work. If that’s the case, you are actually devaluing your work (just tweaking numbers). If your work has such low significance, why it should be accepted in a journal with impact factor of 2.397? - Based on reviewer’s knowledge, almost every circuit-related paper present measurement results from actual ASIC. There are few papers that is based on post-layout simulation (that’s why I am giving you option 2;post-layout simulation). But I never saw any paper based on pure simulation result like you presented.
It is weird to me to see that author is presenting so many references to support their claims, but all of them has measurement result. Don’t you think you should do the same? - How come you are just showing typical case simulation? How come you are not doing any PVT simulations? Are you so certain that your circuit will maintain its SNDR at extreme corners?
It’s common practice in circuit design to run multiple PVT simulation to prove robustness of circuit (At least 5 process corners (tt/ss/ff/sf/fs), 3 supply voltage (-10%,0,+10%), 3 temperature (-40C, RT, 85C) are needed in PVT sims). I am quite certain that other papers that you have reference did the same thing (Please look at reference [5] for instance). Shouldn’t you do similar? - If author was doing some kind of static-circuit (like reference, regulator), then I would lower the bar because the simulation result matches fairly well with measurement. But you are presenting on an ADC, which will have a lot of differences between measurement and simulation result. Actually, it needs very careful PVT sims, layout and through investigation on post-layout sim because 2nd order effect plays major role on ruining the performance.
- Somehow, if your idea is brand new and something that no one have achieved, then I may consider as very special case and lower the bar. But the proposed concept is already well known and does not apply to you.
- Lastly, you shouldn’t compare your simulation result with other measurement works (in Table 1). It can be very misleading. At least, the FOM comparison should be omitted out because it is not fair comparison. How can you compare simulated SNDR with measured SNDR? Also, author was relying on ideal component as peripheral circuitry (voltage references, LDO, etc). This will increase the power (and lower FOM) when it is actually included in the ASIC.
I still have bunch of other comments, but I’m not going to show here because lack of measurement is the most significant issue with current manuscript.
Author Response
If you would like to get your manuscript accepted, please present either measurement or post-layout simulation result. If you are not going to do any of those, I’m not going accept your manuscript in any circumstances.
=> Thank you for your feedback. Only two days are allowed for this revision, so we could not have enough time to run any post-layout simulation. Instead, several corner simulations are performed, and we added the result to the manuscript (Fig. 14).
There are several reasons to this.
- I already mentioned this earlier, but there will be huge difference between your simulation and actual measurement result due to process variation and cross-coupling from the layout. Any brilliant simulation result is meaningless unless you consider all possible worst-case conditions.
=> In our previous experience in 28nm CMOS process, the simulation result including noise and pre-RC provided by PDK showed a similar result to that from measurement. The only difference we observe is the maximum speed. However, our proposed design in this work reduces the number of conversion cycles, so the speed can still be enhanced compared to a conventional structure regardless of any variation. Therefore, it is not always true that there is a huge difference between simulation and actual measurement result, and the simulation result shows very good correlation in a recent CMOS process.
Author stated “Regardless of the difference in the result between measurement and simulation, there is strong correlation between them. Therefore, even simulation result can demonstrate effectiveness of the proposed solution if there is a reference for comparison” in response 1, but I am totally alarmed by it.
If you were referring to your own past work, it might be true (although I wouldn’t buy it much). But you are actually referring to others work! Don’t you think they spend tremendous of time (on running PVT sim, careful layout, and post-layout simulation) to make strong correlation? How can you be so sure that you’ll get same measurement result from just running typical-case corners (with ideal voltage source)? Shouldn’t you spend similar effort like others?
=> In table 1 in the original manuscript, we compared the performance of the proposed one with that of a conventional one for fair comparison. We admit that we cannot compare our simulation result with others from measurement. However, we are asked by another reviewer to add them.
Author may argue that their work so similar to other references that it doesn’t need additional work. If that’s the case, you are actually devaluing your work (just tweaking numbers). If your work has such low significance, why it should be accepted in a journal with impact factor of 2.397?
- Based on reviewer’s knowledge, almost every circuit-related paper present measurement results from actual ASIC. There are few papers that is based on post-layout simulation (that’s why I am giving you option 2;post-layout simulation). But I never saw any paper based on pure simulation result like you presented.
It is weird to me to see that author is presenting so many references to support their claims, but all of them has measurement result. Don’t you think you should do the same?
=> There are not many journals focusing on circuit design, but IEEE transactions on circuits and systems(TCAS) belongs to the most well-known and authoritative ones. Many simulation papers can be found in TCAS.
Ex)
[paper 1] Wang, X.; Zhou, X.; Li, Q. A High-Speed Energy-Efficient Segmented Prequantize and Bypass DAC for SAR ADCs. IEEE Trans. Circuits Syst. II Express Briefs 2015, 62, 756–760.
[paper 2] Gupta, A.; Nagaraj, K.; Viswanathan, T. A Two-Stage ADC Architecture With VCO-Based Second Stage. IEEE Trans. Circuits Syst. II Express Briefs 2011, 58, 734–738.
[paper 3] Gao, J.; Li, G.; Huang, L.; Li, Q. An Amplifier-Free Pipeline-SAR ADC Architecture With Enhanced Speed and Energy Efficiency. IEEE Trans. Circuits Syst. II Express Briefs 2016, 63, 341–345.
[paper 4] Mroszczyk, P.; Goodacre, J.; Pavlidis, V. Energy Efficient Flash ADC With PVT Variability Compensation Through Advanced Body. IEEE Trans. Circuits Syst. II Express Briefs 2019, 66, 1775–1779.
[paper 5] Fan, H.; Maloberti, F. High-Resolution SAR ADC With Enhanced Linearity. IEEE Trans. Circuits Syst. II Express Briefs 2017, 64, 1142–1146.
[paper 6] Lin, H.; Jin, L.; Yang, J.; Lin, F.; Yao, L.; Jiang, X. Self-Dithering Technique for High-Resolution SAR ADC Design. IEEE Trans. Circuits Syst. II Express Briefs 2015, 62, 1124–1128.
- How come you are just showing typical case simulation? How come you are not doing any PVT simulations? Are you so certain that your circuit will maintain its SNDR at extreme corners?
It’s common practice in circuit design to run multiple PVT simulation to prove robustness of circuit (At least 5 process corners (tt/ss/ff/sf/fs), 3 supply voltage (-10%,0,+10%), 3 temperature (-40C, RT, 85C) are needed in PVT sims). I am quite certain that other papers that you have reference did the same thing (Please look at reference [5] for instance). Shouldn’t you do similar?
=> Thank you for the good suggestion. We added Fig. 14 showing corner simulation results. According to the results including FF/SS/TT (temp: -40 ~ 140), the maximum SNDR variation is less than 1dB although the maximum sampling speed is affected in a similar way to a conventional one. We have much experience in designing a SAR-based ADC and made our best to make the proposed architecture robust to any variation.
- If author was doing some kind of static-circuit (like reference, regulator), then I would lower the bar because the simulation result matches fairly well with measurement. But you are presenting on an ADC, which will have a lot of differences between measurement and simulation result. Actually, it needs very careful PVT sims, layout and through investigation on post-layout sim because 2nd order effect plays major role on ruining the performance.
=> SAR ADCs consist of CDACS, comparators and digital logics in most cases, so they are more robust to variations than static-circuits you mentioned. The CDAC mismatch might be an issue since it causes harmonics but there are thousands of ways calibrating the mismatch. Therefore, the mismatch is not a big concern anymore for resolutions up to 12bits, and there is a low chance for the 2nd order effect in the proposed design.
- Somehow, if your idea is brand new and something that no one have achieved, then I may consider as very special case and lower the bar. But the proposed concept is already well known and does not apply to you.
=> The proposed architecture is the first SAR+noise-shaping ADC that utilizes multi-bit conversion for speed enhancement. Also, we addressed some circuit issues occurring in its implementation. We used redundant conversion to solve jitter problem in multi-bit conversion and we also proposed tail-current sharing comparator. The proposed ideas greatly help to increase the resolution as well as conversion speed and they are not published in other papers yet.
- Lastly, you shouldn’t compare your simulation result with other measurement works (in Table 1). It can be very misleading. At least, the FOM comparison should be omitted out because it is not fair comparison. How can you compare simulated SNDR with measured SNDR? Also, author was relying on ideal component as peripheral circuitry (voltage references, LDO, etc). This will increase the power (and lower FOM) when it is actually included in the ASIC.
=> As already mentioned in the answer to #1, some of the content in Table 1 was added by request from another reviewer.
I still have bunch of other comments, but I’m not going to show here because lack of measurement is the most significant issue with current manuscript.
