# Hardware Implementation Study of Particle Tracking Algorithm on FPGAs

^{1}

^{2}

^{3}

^{4}

^{5}

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Hough Transform as Pattern Recognition Algorithm

- Eight input data channels, originated by the Tracker.
- The eight channels, in parallel, provide up to 500 inputs for a total number of data up to 4000 pair: These are called input Hits.
- Each of the eight channels provides integer number for the x and y CS couples, digitized using 18 bits.
- Each Hit is also provided on-the-fly with the CS pairs in the polar representation, besides the cartesian. The polar data are (r, ϕ) represented respectively with 12 and 16 digital bits.
- The system is targeted to work at a clock frequency of 250 MHz.
- For each input Hit 1200 $\varphi $0 angles are created to cover the desired spread of angles in the HS (1200 bins so using 11 bits).
- The momenta $\frac{Aq}{Pt}$ of the HT Formula (3) are binned in 64 bins, so using 6 digital bits.

## 3. Block Diagram of the HT Implementation on FPGA

#### 3.1. Event Memory Bank

#### 3.2. HT Computation

#### 3.3. Accumulator Filler

#### 3.4. Accumulator

#### Accumulator Sectors

#### 3.5. Sliding Windows

#### 3.6. Tower Finder

#### 3.7. Adders and Comparators

#### 3.8. Hit Extractor

#### 3.9. Circular Output Buffer

## 4. Firmware Design

#### FW Synthesis and Place & Route

- #Hits is the total number of input data (Hits) loaded eight at a time;
- #Roads is the total number of identified Roads within a given Event;
- Latency is the number of clock periods from when the entire Event is loaded to when the first set of Hits belonging to the first Road is sent out.

## 5. Conclusions

## Author Contributions

## Funding

## Acknowledgments

## Conflicts of Interest

## References

- Apollinari, G.; Béjar Alonso, I.; Brüning, O.; Fessia, P.; Lamont, M.; Rossi, L.; Tavian, L. High-Luminosity Large Hadron Collider (HL-LHC): Technical Design Report V. 0.1; CERN Yellow Report Monographs CERN-2017-007-M; CERN: Geneva, Switzerland, 2017; Volume 4, p. 599. [Google Scholar]
- Perkins, D.H. Introduction to High Energy Physics; Cambridge University Press: Cambridge, UK, 2000. [Google Scholar]
- Ryd, A.; Skinnari, L. Tracking Triggers for the HL-LHC. Annu. Rev. Nucl. Part. Sci.
**2020**, 70, 171–195. [Google Scholar] [CrossRef] - Hassanein, A.S.; Mohammad, S.; Sameer, M.; Ragab, M.E. A survey on Hough Transform, Theory, Techniques and Applications. Int. J. Comput. Sci.
**2015**, 12, 32–58. [Google Scholar] - Mukhopadhyay, P.; Chaudhuria, B.B. A survey of Hough Transform. Pattern Recognit.
**2015**, 48, 993–1010. [Google Scholar] [CrossRef] - Abeling, K. Expected tracking performance with the HL-LHC ATLAS detector. In Proceedings of the Science PoS(EPS-HEP2019)177, Ghent, Belgium, 10–17 July 2019; Volume 364. [Google Scholar]
- La Rosa, A. The Upgrade of the CMS Tracker at HL-LHC. JPS Conf. Proc.
**2021**, 34, 010006. [Google Scholar] - Ramesh, N.; Purdy, G.; Purdy, C.; Smith, J. A Hardware Implementation of Hough Transform Based on Parabolic Duality. In Proceedings of the IEEE 57th Int. Midwest Sym. on Circuits and Systems (MWSCAS), College Station, TX, USA, 3–6 August 2014; pp. 145–148. [Google Scholar]
- Ralston, J.; Ngo, H. Design of an embedded system for real-time lane detection based on the linear Hough transform. In Proceedings of the SPIE 11736, Real-Time Image Processing and Deep Learning, Online, 12–16 April 2021; Volume 11736. [Google Scholar] [CrossRef]
- Baranov, S. High Level Synthesis of Digital Systems: For Data Path and Control Dominated Systems; ACM Digital Library: Ottawa, ON, Canada, 2018; p. 207. ISBN 978-1-7750917-1-4. [Google Scholar]
- Zhang, J.; Ma, J.; Yan, Z. Identification of Pipeline Circuit Design. Electron. Signal Process.
**2015**, 97, 71–76. [Google Scholar] - Xilinx, UltraScale and UltraScale+ GTY Transceivers. UltraScale Architecture GTY Transceivers UG578. 2017, p. 446. Available online: https://www.xilinx.com/support/documentation/user\char_guides/ug578-ultrascale-gty-transceivers.pdf (accessed on 15 October 2021).
- Xilinx, Aurora 64B/66B v12.0 LogiCORE IP Product Guide. Vivado Design Suite PG074. 2020, p. 145. Available online: https://www.xilinx.com/support/documentation/ip\char_documentation/aurora\char_64b66b/v11\char_2/pg074-aurora-64b66b.pdf (accessed on 15 October 2021).
- Xilinx, UltraFast DesignMethodology Guide forXilinx FPGAs and SoCs. UG949 (v2021.1). 2020, p. 327. Available online: https://www.xilinx.com/support/documentation/sw\char_manuals/xilinx2020\char_1/ug949-vivado-design-methodology.pdf (accessed on 15 October 2021).

**Figure 1.**Example of Hough transform based on the straight line formula y = x · m + Q. The plot on the left shows the Coordinate Space, the right plot the Hough Space.

**Figure 2.**Hough Space after executing HT Formula (3): Example with electron-Volt eV and charge q set to 1 units.

**Figure 3.**3D plot of the Hough Space after executing the HT Formula (3).

**Figure 8.**Critical paths management in the FW. The logic has been divided and placed in different Super Logic Regions depending on the clock trees (different colours in the Figure).

Device | Firmware Version | Setup WNS (ns) | Failed Nets/Total Nets | Max Freq./ Targeted Freq. (MHz) | Development Strategy |
---|---|---|---|---|---|

Alveo U250 | Accumulator 216 qA/Pt by 64 $\varphi 0$, 800 hits | −0.673 | 4000/610,000 | 214/250 | Without SLRs |

Alveo U250 | Accumulator 222 qA/Pt by 72 $\varphi 0$, 800 hits | −0.254 | 4200/795,000 | 235/250 | With SLRs |

Alveo U250 | Accumulator 216 qA/Pt by 216 $\varphi 0$, 800 hits | −3.776 | 104,000/1,582,000 | 128/250 | Without SLRs |

Alveo U250 | Accumulator 222 qA/Pt by 224 $\varphi 0$, 800 hits | −0.441 | 52/1,769,000 | 225/250 | With SLRs |

Device | Firmware Version | Flip Flops (%) | Look-Up Table (%) | Digital Signal Processor (%) | GigaBit Transceivers IO (%) | Block RAM Memory (%) |
---|---|---|---|---|---|---|

Alveo U250 | Accumulator 216 qA/Pt by 64 $\varphi 0$, 800 hits | 9 | 17 | 8 | 100 | 1 |

Alveo U250 | Accumulator 222 qA/Pt by 72 $\varphi 0$, 800 hits | 11 | 19 | 8 | 100 | 1 |

Alveo U250 | Accumulator 216 qA/Pt by 216 $\varphi 0$, 800 hits | 24 | 52 | 12 | 100 | 1 |

Alveo U250 | Accumulator 222 qA/Pt by 224 $\varphi 0$, 800 hits | 28 | 53 | 12 | 100 | 3 |

Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations. |

© 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).

## Share and Cite

**MDPI and ACS Style**

Gabrielli, A.; Alfonsi, F.; Annovi, A.; Camplani, A.; Cerri, A.
Hardware Implementation Study of Particle Tracking Algorithm on FPGAs. *Electronics* **2021**, *10*, 2546.
https://doi.org/10.3390/electronics10202546

**AMA Style**

Gabrielli A, Alfonsi F, Annovi A, Camplani A, Cerri A.
Hardware Implementation Study of Particle Tracking Algorithm on FPGAs. *Electronics*. 2021; 10(20):2546.
https://doi.org/10.3390/electronics10202546

**Chicago/Turabian Style**

Gabrielli, Alessandro, Fabrizio Alfonsi, Alberto Annovi, Alessandra Camplani, and Alessandro Cerri.
2021. "Hardware Implementation Study of Particle Tracking Algorithm on FPGAs" *Electronics* 10, no. 20: 2546.
https://doi.org/10.3390/electronics10202546