Low-Process–Voltage–Temperature-Sensitivity Multi-Stage Timing Monitor for System-on-Chip Applications
Round 1
Reviewer 1 Report
This paper proposes a "timing monitor" that has better resolution than previous works. The authors describe reasonably well their design but (a) fail to motivate and clearly define the topic of this work, and (b) do not support the claim of the abstract that their work makes DVFS more efficient.
Abstract: "the proposed timing monitor has high immunity than the PVT variation". First check English. Second, the PVT variation is not defined (yet) and is potentially unknown to the reader.
Introduction: "the non-ideal effect ..." there is no such thing as "non-ideal effect". There are various real-life uncertainties at different levels of the implementation process.
pp1 last line: To overcome... critical timing". You do not clearly define what you are trying to did, and what are the requirements and restrictions. Looking at Fig 1, I can assume you are building a phgase correction module. However, it is unclear to me how you can determine the phase among two arbitrary signals (the lines front the digital block on the left of the figure. Do you assume the signals are "clean" i.e. they come directly from an FF? Are these clock signals? If not, how do you make heads and tails of them?
What are the rexstrictions of your approach? Do you assume the blocks are mesochronous?Can they have arbitrary clock periods?
The DVFS connection should be quantified if youmake the case for it. What can be gained if the accuracy of the timing monitor is better? How much does it affect actual designs? Etc.
Author Response
Please see the attachment.
Author Response File: 
Author Response.pdf
Reviewer 2 Report
This paper presents a timing monitor architecture for SoC applications. The literature review is not available and the comparison is not complete. More details can be found below.
- The drawbacks of the prior arts are not reviewed. In other words, the motivation is not highlighted well.
- Why do the curves in Figure 10 fluctuate? They need to be refined to give some insights.
- While the timing monitors in Table 2 were implemented in different processes, the measures are not normalized. Therefore, it is currently hard to say that the proposed one is superior to the others.
- In Table 2, the compared ones except [1] are rather old.
- Has this manuscript ever been submitted to the IEEE JSSC in which most of the compared ones published? The SSC-L would be appropriate if the length matters.
- English needs to be improved.
Author Response
Please see the attachment.
Author Response File: Author Response.pdf
Round 2
Reviewer 2 Report
The concerns of the reviewer have been addressed. Thank you.
