An Analog Voltage Similarity Circuit with a Bell-Shaped Power Consumption

Abstract

This paper presents a voltage similarity circuit (bump circuit) based on a novel voltage correlator. The proposed circuit is characterized by a power consumption which depends on the similarity between the two inputs. The sensitivity of the bump circuit and the power consumption are at the highest values when the inputs are equal. As the similarity between the input voltages decreases, the total current consumption decreases with a bell-shaped behavior. The proposed bump circuit is very simple in design, made of a new voltage correlator circuit in combination with a differential pair and mimics the behavior of the classical bump circuit. The voltage correlator was implemented using $AMS-350$ $\mathrm{nm}$ CMOS technology. Simulation and measurement results suggests that a low power consumption may be achieved if the circuit is used in applications where the input signals have large dissimilarity for most of the circuit operation.

1. Introduction

Circuits performing mathematical and logical operations, have been a research subject for many years [1]. Electrical signals, i.e., currents and voltages are suited for this purpose and variety of circuits and systems are proposed throughout the years. Circuits based on operational Amplifiers [2,3] can perform operations, such as addition, integration, inversion, multiplication, exponentiation, logarithm, division, etc. Analog signal processing, however, suffers from inaccuracy and is more susceptible to noise compared to their digital counterparts. Today, digital signal processing has become the dominant method thanks to introduction of integrated circuits which allows for higher integration and clock speeds. Despite this fact, analog signal processors are often far more effective and simpler in design than their digital counterparts [4,5,6]. Finding similarity or correlation between two or more analog signals is a good example. Current correlators [7] are used to find the correlation between two currents and voltage similarity circuits to find the similarity between voltages. One of the simplest and well-known voltage similarity circuits is the bump circuit presented by Tobias Delbrück [8] in 1991. Voltage similarity circuits are widely used in analog systems, such as in ultra low power energy harvesters [9], neuromorphic systems [10], and biological inspired circuits [11]. One of the main challenges with these circuits are the relatively high power consumption as they must be active all the time. Different approaches exist to lower the power consumption, such as clocking and/or lowering the power supplies, optimizing transistor sizes, and/or decreasing the bias voltages to limit the currents in the circuits. All of these methods will affect the operation of the circuit and can potentially decrease the sensitivity. Lu et al. [12] presented a bump circuit with a power consumption of $18.9nW@Vdd=3$ V using a novel pseudo-differential transconductor. This circuit requires additional complicated biasing circuitry which may make the design more challenging compared to the presented circuit. Pheng et al. [13] exploit the properties of multiple input floating-gate technique to realizes a tunable bump circuit. The main drawback with this circuit is that it needs a complicated digital circuitry for programming the floating gates. Other similarity circuits have also been presented which offer tunability [14,15,16].

This paper is an extended version of a previously published paper [17], which introduced the concept. In that paper, we presented a new voltage similarity circuit (bump circuit) where the power consumption depends on the input voltages. It can potentially have lower power consumption compared to the classic bump circuit with the same functionality. In this paper, we present measurements results from a 350 $\mathrm{nm}$ ASIC from $AMS$ and compare these to simulations. Simulations are done using Cadence with 350 $\mathrm{nm}$ CMOS models from AMS. In addition, the gain and common-mode behavior of the circuit are analyzed and an example of a energy harvester system, which may take advantage of the proposed bump circuit is presented.

2. New Voltage Correlator Circuit

The proposed voltage correlator circuit is shown in Figure 1. The correlator circuit consists of two equal legs with diode-connected transistors $M3$ and $M4$ in series with transistors $M1$ and $M2$, respectively. The gates of transistors $M1$ and $M2$ are connected to the gate of diode-connected transistor at the opposite leg. If the voltages $V1$ and $V2$ are equal and high enough to keep $M1$ and $M2$ in triode, i.e., $V_{gs1,2}>V_{th}+V_{d1,2}$, both legs conduct equally, and the currents are at their maximum values.

In this state, the currents $I1$ and $I2$ are roughly decided by the diode-connected transistors that are in saturation and can be approximated by

$$I1,\left(2\right)=\frac{{\beta }_{3,\left(4\right)}}{2}{(V1-Vd1,\left(d2\right)-V_{th})}^2,$$

(1)

where $\beta =\mathsf{\mu }Cox(W/L)$, and $V_{th}$ is the threshold voltage. Assuming $M1$ and $M2$ are in deep triode, $Vd1$ and $Vd2$ can be given as

$$Vd1,\left(d2\right)=I1,\left(2\right)\times R_{M1,\left(2\right)}=\frac{I1,\left(2\right)}{{\beta }_{1,\left(2\right)}(V1\left(2\right)-V_{th}{)}^{\prime }}$$

(2)

where $R_{M1,2}$ are the channel resistances at deep triode, which may be approximated by

$$R_{M1,\left(2\right)}=\frac{1}{{\beta }_{2,\left(1\right)}\times (V2,\left(1\right)-V_{th})}.$$

(3)

As the voltages $V1$ and $V2$ across the two legs become different, the transistors will behave differently. If all the transistors in the circuit are equal in size, currents in both legs will remain almost equal. In this state, the currents are always limited by the leg with the lowest of the two voltages. If $V1$ increases and $V2$ decreases, the voltages across $M1$ and $M3$ increase, and $M1$ goes into saturation, and $M2$ goes into deeper triode region. According to Equation (3), the resistance of $M2$ decreases, and the voltage $Vd2$ approaches the ground value. In this state, $M4$ forms a current mirror with $M1$, which controls and limits the current $I1$ equal to $I2$, as shown in Figure 2. The body effect of $M4$ decreases as its source approaches ground. Similar behavior can be expected when $V2$ becomes larger than $V1$.

As $V2$ decreases, $I1$ will decrease. If we ignore the channel modulation effect of $M1$, the current $I1$ can be expressed as:

$$I1=I2=\frac{{\beta }_4}{2}{(V2-V_{th})}^2.$$

(4)

As explained earlier, the correlation between the two voltages $V1$ and $V2$ is through the current mirrors created between the two legs of circuit. The weighting between the transistors forming the current mirror will, therefore, control the amount of current in each leg. Figure 3 and Figure 4 show how the voltages $Vd1,Vd2$ and the currents $I1$ and $I2$ are affected when the widths of the transistors $M1$ and $M2$ are increased from $1\mathsf{\mu }$m to $10\mathsf{\mu }$m simultaneously, and $M3$ and $M4$ are kept constant at $1\mathsf{\mu }$m. From the current simulation in Figure 3, we can see that the two currents are equal and at their maximum when $V1$ is approximately equal to $V2$ when all device widths are $1\mathsf{\mu }$m, i.e., the mirror is balanced. This figure shows that as the widths increase, the currents increase. When the mirror is formed due to difference between the voltages $V1$ and $V2$, the increased width increases the difference between the currents. Figure 4 shows as the widths increase, the voltages $Vd1$ and $Vd2$ are pulled closer to ground due to even larger ratio between the transistors in the current mirrors and higher conductivity in the transistors, i.e., less resistance. To summarize, the increased width has two important effects, one is that the resistance of the transistor in triode decreases, which makes the current mirror more ideal with less body effect and it makes the mirror unbalanced, i.e., the current in one leg becomes higher than the other one. As we will show later when this circuit is used in a bump circuit, an unbalanced current mirror is necessary to create the bump at the output current correlator.

The transistors in the simulations and measurements presented have lengths of 500 $\mathrm{nm}$ and widths of $1\mathsf{\mu }$m if not stated in the text explicitly. Transistors M1 and M2 have widths of $15\mathsf{\mu }$m. The bias voltage $VBias$ is set to $2.35$ V, and $Vdd$ is $3.2$ V in both measurements and simulations if not stated explicitly in the text.

Voltage Correlator Connected to a Differential Pair

By cascoding a PMOS differential pair to the voltage correlator as shown in Figure 5a, the functionality of these two circuits is combined. The currents through each leg of the combined circuit are denoted $Ic1$ and $Ic2$ and shown in Figure 6 as the black curves. This figure shows also the currents in the voltage correlator $I1$, $I2$ presented earlier as the blue curves and the currents in a different pair denoted $I_{diff1}$, $I_{diff2}$ as the red curves for comparison. The solid curves are the currents through the left leg, and the dashed ones are the currents in the right leg. The rapid decrease of current when the two inputs become equal is caused by the differential pair. From the simulation, we can see that currents $Ic1,Ic2$ follow $I_{diff1},I_{diff2}$ when the two input voltages are close to each other and follow the currents $I1$, $I2$ when the inputs become different.

When the inputs are equal, the transistors $M1$ and $M2$ are in deep triode and all other transistors are in saturation, i.e., voltages $VA$ and $VB$ will be just above threshold voltage. The current can be approximated as

$$Ic1=Ic2=\frac{{\beta }_{6\left(5\right)}}{2}{(Vdd-V2\left(1\right)-V_{th})}^2.$$

(5)

As the difference between the inputs increases, the circuit will change its state. Assuming $V1$ decreases and $V2$ increases, the circuit can be represented as in Figure 5b. Transistors $M5$ and $M2$ go into triode and all the others in saturation. The current $Ic2$ is then mirrored into $Ic1$. $M3$ will act as a diode connected transistor with a voltage approximately equal to the threshold voltage across it. The current in this state can be approximated as

$$Ic1=I_{M1}=I_{M3}=I_{M5}=K{I}_{M6},$$

(6)

where K is the ratio between the widths of the transistors forming the mirror $M1$ and $M4$. If we ignore the effect of this diode connected transistor, i.e. $M3$, and assuming that M5 is in deep triode, the circuit can be modeled in strong inversion as

$$\begin{array}{cc}\hfill Ic1& ={\beta }_5\left((Vdd-V1-V_{th})V_{DS}\right)\hfill \\ \hfill & =K\frac{{\beta }_6}{2}{(Vdd-V2-V_{th})}^2.\hfill \end{array}$$

(7)

Figure 7 shows the currents in circuit shown in Figure 5a when the widths of transistors $M1$ and $M2$ are increased from $1\mathsf{\mu }$m to $10\mathsf{\mu }$m simultaneously, and $M3$ and $M4$ are kept constant at $1\mathsf{\mu }$m. From the figure, we can see that the variations in currents due to the changes in the width of the transistors are smaller compared to the simulation in Figure 3, which is caused by the differential pair. The simulation shows the current $Ic1$ and $Ic2$ as solid and circled curves, respectively, and the total current in the circuit $Itot$ as dashed curves.

3. The Proposed Bump Circuit

By correlating the currents $I_{C1}$ and $I_{C2}$ in the circuit shown in Figure 5a using a current correlator made of two series connected transistors, the circuit will become a voltage similarity (bump) circuit as shown in Figure 8a. This bump circuit will have a similar behavior as the classic bump circuit developed by Delbrück [8] shown in Figure 8b. The output current of the bump circuit in weak inversion and strong inversion are given in References [8,15], respectively.

When the inputs are similar, the circuits in Figure 8a,b will behave similar and have the same current consumption. When the inputs become different, the current consumption of the classic bump circuit increases, while the proposed bump circuit will have a decreasing power consumption.

Figure 9 shows the voltages at the drain of the different pair for both bump circuits denoted $VA$ and $VB$ in Figure 8a and $VC$ and $VD$ for the classic bump circuit in the Figure 8b. Voltages VA and VB in the proposed bump circuit change their state from rail to rail as the input voltages cross each other, but $VC$ and $VD$ in the classic bump circuit change only between ground and the threshold voltage of the devices as they are connected as diodes. Voltages $VA$ and $VB$ can in some cases be regarded as a digital signal that changes its state when the inputs cross each other.

Figure 10 shows the simulation of the proposed bump circuit and the classic one when a differential voltage is applied to their inputs. The solid black and red colored curves marked $I_{tot}$ are the total current consumption of the classic bump circuit and the new proposed circuit, respectively. The variation in current consumption of the proposed bump circuit follows a bell-shaped curve.

The total static power consumption for all the combination of the input voltages of the proposed bump circuit and the classic bump is illustrated as a 3-d graph in Figure 11a,b, respectively. It is clear from the simulation that the proposed bump circuit will achieve low power consumption when one or both of the inputs are close to $Vdd$, approximately above 2.5 volts in this simulation.

The power consumed by the proposed bump circuit and the classic are compared and shown in Figure 11c. The relation between power of the two circuits increases exponentially with the increase in the difference between the input voltages. For the simulation in Figure 11c, it is as high as 5 orders of magnitude when the difference between the inputs approaches maximum.

The simulation in Figure 10 shows also the output currents $I_{out}$ in both the classic bump circuit as dashed black curve and the proposed bump circuit as dashed red curve. When the input voltages $V1$ and $V2$ are equal, $I_{out}$ is large and equal for both circuits. When the difference between the input increases, the output currents in both bump circuits decrease. In the classic bump circuit, the output current $Iout$ is close to zero as the inputs become different, while in the proposed bump circuit, the output current becomes null only when the $|V2-V1|\gg 0$. This difference is due to the fact that the sources of the diode connected transistors $M3$ and $M4$ in the proposed circuit are not completely grounded when the inputs are different, causing the output transistors to leak. This current leakage can be reduced by increasing the width of the transistors $M1$ and $M2$ to create a stronger ground as explained in Section 2. The effect of increasing the width of these transistors are shown in Figure 3, Figure 4, and Figure 7.

A well known non-ideality of the current correlator used in both circuits is the asymmetric bump at the output, which is caused by the fact that the series connected transistors $M8$ and $M9$ have different source voltages. This can be solved by adding an extra pair of transistors connected in parallel with $M8$ and $M9$ where their gate connections are interchanged as in References [12,14].

Common-Mode Behavior of Proposed Bump Circuit

The behavior of the proposed bump circuit, including its power consumption and the gain, is highly dependent on the input common-mode voltage. Figure 12 shows the sensitivity (S) of the proposed bump circuit at different common-mode voltages defined as

$$S=\frac{d(I2-I1)}{d(V2-V1)}.$$

(8)

The simulation results show that maximum gain is achieved at low common-mode voltages and decreases as the common mode voltage increases. This is expected due to larger currents in the circuit. This behavior would be opposite for NMOS input transistors, i.e., the gain would be at its maximum at higher voltages closer to Vdd.

Figure 13 shows the power consumption of the proposed bump circuit at different input common-mode voltages. The figure shows the simulation when the inputs cross each other at common-mode voltage levels = 0 V, 0.5 V, 1 V, 1.5 V, 2 V, 2.5 V, and 3 V. This simulation shows that the power consumption increases as the similarity occurs at lower voltages. The change in the common-mode voltage also changes the width of the bell. To be able to analyze this characteristic in more details, we measured the full width of half the maximum $\left(FWHM\right)$ of the bell-shaped current consumption as shown in Figure 13. We used two different parameters to analyze the power consumption as function of the common-mode voltage, quality Q and efficiency E. Q is the blue dashed curve in Figure 14 and defined as

$$Q=\frac{CMV}{{FWHM}^{\prime }}$$

(9)

where $CMV$ is the common-mode voltage. The power efficiency is shown as the green curve and defined as

$$E=\frac{Ipeak}{{FWHM}^{\prime }}$$

(10)

where $Ipeak$ is the maximum current consumption at the common-mode voltage and is shown in the figure as the black solid curve. The analysis show that efficiency reaches its maximum at common-mode voltage = $2.6$ V. The product of the $Ipeak$ and the $FWHM$ is also shown as the dashed black curve which relates to the average power consumption. From these analyses, we can conclude that the circuit is more effective at common-mode voltages close to Vdd.

Table 1. Comparison of bump circuits. <Nr of devices> in the table is the minimum number of devices needed to realize the circuit. Results from “[8]” in the figure below are from the presented work.

Ref.	This Work	[8]	[12]	[13]	[14]	[15]	[16]
Vdd (V)	3.2	3.2	3	2	5	$\pm 2.5$	5
Power (W)	256 n	256 n	18.9 n	na	na	na	na
Technology	350 $\mathrm{nm}$	350 $\mathrm{nm}$	500 $\mathrm{nm}$	1.2 $\mathsf{\mu }$m	500 $\mathrm{nm}$	3 $\mathsf{\mu }$m	ALD1106/7
Nr of devices	10	8	18	15	11	14	11

compares the performance of the proposed circuit with other bump circuits described in the current literature.

The main feature and novelty of the presented circuit is that power consumption is dependent on the input voltages. To our knowledge, no other circuit offers this feature. Furthermore, it is worth mentioning that the design presented in this work was not optimized for minimum power consumption; however, we have achieve power consumption in nano-watt region. As the power consumption may vary and is dependent on application, we have chosen to compare the static power consumption when inputs are equal, i.e., maximum power consumption at common-mode voltage at Vdd/2.

The power consumption of Reference [8] is similar with ours as shown in the table. This is because the circuit in Reference [8] is most similar to ours and the best one for comparison. We have simulated both circuits and presented the results in Figure 10 and Figure 11. Table 1 shows the maximum power consumption of our circuit which decreases as the inputs become different as shown in Figure 11a, but, for Reference [8], the power increases as shown in Figure 10 and Figure 11b. The minimum power consumption of our circuit is not easy to determine as it can approach 0 and lower than Reference [12] when the difference between the inputs becomes large enough.

4. Measurement Results

The proposed bump circuit was fabricated using 350 $\mathrm{nm}$ CMOS from $AMS$. Micrograph of the bump circuit including two buffers used at the outputs is shown in Figure 15a. In this implementation, the bump was given a separate power supply pad in order to measure the characteristic bell shaped power consumption of the circuit. The output buffers are connected to $Vout$ and node $VA$. $VB$ was omitted due to its symmetrical behavior. In the figure, all the circuit ports and some of the parts are marked with black text. In this chip, the transistors $M1$ and $M2$ have a width of $15\mathsf{\mu }$m and all others a width of $1\mathsf{\mu }$m.

The chip was mounted on chip-carrier and bonded in-house as shown in Figure 15b. Keysight DSOX3024T oscilloscope was used to read the output values, Fluke 45 multimeters was used for current measurement and Agilent 33521A signal generators was used to generate the input signals. The system was powered using GW GPS-3030 power supply. Figure 16 shows the measurement of the output voltage $Vout$ and the node $VA$ at 10 kHz frequency. The behavior of the circuit matches the simulation result shown in Figure 9, which is shown as the black dashed curve in the figure. The node $VA$ (red curve) follows $V2$ and is at its lowest value when the input $V2$ is at its minimum value. The voltage $Vout$ goes low when the inputs are equal. $Vout$ does not reach ground. The reason for this is unknown, but we think it may be due to the type of pad we used, which doesn’t have the correct ground value since the chip was a mixed design sharing pads with other circuitry.

Figure 17 shows the measured power consumption of the proposed bump circuit when $V2$ is grounded, and $V1$ is increased from ground to $Vdd$. The blue curve is the measurement result, and the green is the simulation result. The measured current does not reach zero due to the leakages in the protection diodes in the pad. Figure 18 shows the power consumption when the $V1$ is decreased to ground from $Vdd/2$ and $V2$ increased from $Vdd/2$ to $Vdd$ simultaneous. In this figure, we have also added the simulation result for the classic bump circuit for comparison. The two previous measurement result confirm the variation in the power consumption of the circuit as a function of the input voltages.

We could not measure the currents in each leg using the ASIC; therefore, all the circuits were implemented using the IC $CD4007UBE$ from Texas Instruments. Using this IC did not allow for sizing the transistors for optimal design and the measurements only serve the purpose of proving the concept. To realize the different circuits, we had to use more than one chip. The circuit in Figure 1 was realized using two chips as shown in Figure 19b and tested by applying differential input voltages $V1$ and $V2$ in the range $[2 \mathrm{V}–6 \mathrm{V}]$ with input common-mode voltage at $V_{icm}=4$ V. Measurement results for this circuit are shown in Figure 20. These measurement results provide the same wave forms obtained by the simulations in Figure 3, i.e., minimum currents $I1,I2$ at the maximum distance between the two input signals ($V1=2 \mathrm{V},V2=6 \mathrm{V},$ and $V1=6 \mathrm{V},V2=2$ V) and a maximum correlation of $I1$ and $I2$ when $V1=V2=4$ V.

Next, the measurement results for the circuit combining the correlator circuit and a different pair as shown in Figure 19a are shown in Figure 21. These measurement results also match the simulations shown in Figure 6. It is interesting to note that this behavior of currents in the two legs matches the one presented in Figure 7 for device widths equal to $1\mathsf{\mu }$m in the current mirror. The figure shows also the total power consumption of the classic bump circuit realized using the 3 ICs. We can see that the power consumption reduces by almost 72 percent compared to the classic bump when the difference between the input voltages is 4 V.

5. Double Charge Pump Interface with Bump Circuits

In the low power interface for a energy harvesting double charge pump proposed in Reference [9], the authors use two bump circuits for activating and deactivating the flyback switch, as shown in Figure 22. Capacitors Cvar 1 and Cvar 2 work deferentially and pump charges from the reservoir capacitance $Cres$ to the series connected capacitors $Cs$ and $Cs2$. As the charges are being pumped, the voltage across $Cs$ and $Cs2$ increase. $Cs2$ is chosen much smaller than $Cs$ and when the voltage across $Cs2$ reaches the voltage at $Cres$, the bump circuit 1 activates the flyback switch which transfers the charges to $Cres$ through the inductor $L_{fly}$. The voltage $V_{S}2$ is shown in Figure 23 as the dashed black curve and $Vres$ as the dashed blue curve. We compared the proposed bump circuit and classic one with each other for this application through simulation. The green and red solid curves are the current consumption of the proposed and classic bump circuits, respectively. The proposed bump circuit consumes almost 3.5 times less power consumption on average in this operation. After the switch goes on, the charges will flow from $Cs$ to $Cres$. $V_S$ approaches the voltage across the $Cres$, and the bump circuit 2 turns off the switch. This voltage change tends to be large and abrupt. This operation will take advantage of the variable power behavior of the proposed bump circuit. More detailed description of this charge pump is found in Reference [9].

6. Conclusions

In this paper, we presented a bump circuit, which finds the similarity between two voltages based on a novel voltage correlator. The proposed bump circuit offers the same properties of the classic bump circuit with the main difference that the current consumption approaches zero as the inputs become different. When the input voltages approach each other, currents flow increases, which also increases sensitivity. The simulations and measurements proved that the proposed bump circuit can use several orders of magnitude less power than classic bump circuit at maximum. Applications where similarity of two voltages is normally large, such as the low power interface for a charge pump presented, exploit the low power properties of the circuit at maximum. The proposed bump circuit was analyzed using simulation and measurements for proving the concept.