# LC Tank Oscillator Based on New Negative Resistor in FDSOI Technology

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## Abstract

**:**

## 1. Introduction

## 2. FDSOI Technology

_{t}) [12] mismatch factor when compared to other technologies such as 28 nm LP bulk technology. This in turn allows for excellent analog performance while minimizing power consumption.

_{Th}. Figure 4 presents the back-gate (BG) contact of such a transistor, and Figure 5 depicts the measured influence of the BG biasing on the V

_{Th}variation [13]. Compared to conventional transistors, in FDSOI technology, the value of V

_{Th}can be effectively reduced by BG biasing.

## 3. Current Mirror

#### 3.1. Classical Design

_{ref}/I

_{out}ratio is equal to the size ratio of the two transistors, given by the well-known Equation (1).

_{ref}and I

_{out}, are given by Equations (2) and (3).

_{gs}, the ratio becomes:

_{ds1}and V

_{ds2}, which may not be equal. This mismatch is worsened under short channel conditions with large λ. Several current mirror structures have been developed to reduce the short channel effect, such as the cascode current mirror and Wilson current mirror. These structures enforce equal V

_{ds}for the two transistors to ensure uniform channel modulation. However, cascoded types of the basic current mirror (such as Wilson or Widlar topologies) are not feasible for low power supply voltages such as 1 V, as they reduce voltage margin or increase power consumption.

#### 3.2. New Mirror Current Topology Using FDSOI Technology

_{ds}is not the same [6]. This approach can be applied to the basic current mirror depicted in Figure 6 by configuring the back-gates of FDSOI transistors, as shown in Figure 7.

_{ds}in the saturation region can be achieved by biasing the back-gate voltage. Figure 7a depicts the connection of V

_{out}to the back-gate of M1. With this setup, the back-gate voltage of M1 tracks the drain voltage of M2, which varies from 0 to 1 V. As the back-gate voltage rises, the threshold voltage drops, leading to a reduction in the biasing voltage (V

_{gs}) required to maintain the same source current (cf. Equation (2)). Consequently, the slope of the output current can be controlled, and it can become horizontal or negative based on the lengths of the transistors.

_{N}/L

_{N}= 80 nm/33 nm) to focus on the short channel effect. The output current (I

_{out}) exhibits an exponential relationship within the moderate region (red curve) when the back-gate of each transistor is biased to the ground, similar to a classical bulk transistor. This reveals that the basic current mirror without back-gate control experiences a significant mismatch between the reference current and the output current.

_{bias}(blue curve, cf. configuration Figure 7a). Moreover, connecting both back-gates of the two transistors to the drain voltages can result in an output current that increases up to the reference current of 1 µA, as illustrated by the green curve (cf. configuration Figure 7b).

_{ds}and g

_{mb}values. Finally, a transistor length of 35 nm, along with a fixed width of 100 µm, was found to be optimal for compensating g

_{ds}by g

_{mb}, with higher reference currents.

#### 3.3. Implementation and Measurements

_{DD}in the absence of back-gate control.

_{B}) has to be optimized. In order to achieve this more efficient length value, a series of DC simulations was conducted. In Figure 10, only three simulation results were presented with three different values of L (34 nm, 35 nm, and 36 nm) while maintaining a constant width of W = 100 µm, where I

_{REF}= 45 µA. The results indicate that the output current of the current mirror is highly dependent on the transistor length and is very sensitive. The optimal transistor length was found by the simulation to be 35 nm, as deviations from this length resulted in either undercompensation (for L = 34 nm) or overcompensation (for L = 36 nm).

_{DD}= 1 V), have been implemented in 28 nm FDSOI technology. The layout is depicted in Figure 11 and has a size of 30 × 40 µm

^{2}under the implementation of 28 nm FDSOI technology by STM. Finally, simulations and measurements are compared as shown in Figure 12 and Figure 13.

_{REF}= 45, 90, or 180 µA) and comparing the results with and without back-gate control. Both configurations with the optimal L value (35 nm) have the same size of transistors. In Figure 12 and Figure 13, measurements and simulations (solid and dotted lines, respectively) show good agreement in the saturation regions, despite slightly different saturation voltage values (0.1 V for simulation and a higher value for measurement). To our knowledge, we have not found an answer to explain this phenomenon to date. Therefore, it can be concluded that the cross-coupled back-gate auto-biasing technique effectively stabilizes the current in the saturation region at values of 45, 90, and 180 µA, respectively.

_{REF}= 180 µA). If this sensitivity can be a problem for the realization of a current mirror, it is not the case if we really want to realize a negative resistor, as described in Section 4.

## 4. New LC Tank Oscillator

_{B}) and to achieve the desired negative resistance, several simulations were conducted. We performed DC simulations to explore the behavior of the negative resistance circuit across varying reference current magnitudes. Figure 14 showcases the simulation outcomes corresponding to a reference current of 1 mA. These simulations were conducted considering an incremental elongation of transistor length (L) from 30 nm to 100 nm (by step of 10 nm), displayed sequentially from top to bottom.

_{BIAS}, as shown in Figure 15. The negative resistance circuit was connected in parallel with the oscillation circuit, enabling continuous oscillation. The oscillation frequency was determined by the values of the inductor and capacitor in the LC tank circuit.

_{BIAS}, several extensive simulations were performed. The impact of different V

_{BIAS}values on the circuit’s performance was the main focus. To realize more accurate simulations, the series resistance of the inductor was taken into account, which is depicted in Figure 16.

_{0}= 77. To verify these values, the impedance of the LC tank was simulated, including the series resistor r = 200 mΩ. The frequency response result is depicted in Figure 17. The impedance initially increases and then decreases as the frequency increases, reaching its maximum value at the resonant frequency.

_{0}= 2.45 GHz, cf. Figure 17), the simulated impedance equals R

_{//}= 1.2 kΩ as expected, and the bandwidth (for Z = 850 Ω) is 2472 − 2440 = 32 MHz, so the quality factor is given by Q = 2455/32 = 76.

_{//}. The size W/L of P

_{A}and P

_{B}and the minimum value of I

_{REF}(generated by N

_{1}through V

_{BIAS}) need to be determined. First, W = 100 µm was chosen to achieve some values of I

_{REF}higher than a few mA. By adjusting in simulation the size of L from 30 nm to 120 nm to perform a negative resistor, the slope of the circuit, |I

_{OUT}/V

_{DS}|, exhibits a non-linear trend, initially increasing and then decreasing until reaching its peak at approximately L = 80 nm. Notably, the output signal demonstrates its maximal amplitude and shortest response time when L is set to 80 nm. Finally, to determine the minimum value of I

_{REF}for the oscillation’s start, an ideal current generator was used to replace N1. The simulation results exhibit a value of I

_{REFmin}= 2.3 mA. To achieve this current with a low value of V

_{BIAS}(0.5 V for example), the size of N

_{1}is W/L = 30 µm/30 nm. Figure 18 gives the different sizes of the components.

_{1}. These results show that the oscillation frequency is quite stable and the best compromise between settling time, power consumption (cf. I

_{REF}), and phase noise is achieved for I

_{REF}= 5.0 mA (i.e., V

_{BIAS}= 0.6 V). Depending on the application, it is possible to adjust the phase noise to power consumption ratio while maintaining the same frequency resonance.

_{REF}was set to 5.0 mA (V

_{BIAS}= 0.6 V). In Figure 19a, the periodic output signal is displayed, with a settling time equal to 45 ns. In Figure 19b, the oscillation signal is scaled up to measure the oscillation frequency, which is found to be 2.37 GHz.

_{DS}(P

_{B}). This value equals C

_{out}= 0.3 pF. The total capacitance of the LC tank is C

_{T}= 4.2 + 0.3 = 4.5 pF, giving a resonance frequency f

_{0}= 2.37 GHz, as found in the simulation.

## 5. Comparison with Classical LC Tank VCO

_{T}in Figure 21, is one of the biggest noise contributors of this structure [19]. Different techniques to reduce this noise have been proposed, such as sinusoidal tail current shaping [20], tail current flicker noise reduction by complementary switched biasing [21], sinusoidal shaping of the ISF [22], novel tail current noise second harmonic filtering [23], … A significant and interesting contribution was proposed in 2007 [24] using SOI technology. In fact, the technology was PD (partially depleted) SOI, which allows to suppress the tail current transistor. The biasing current is directly modulated by the body voltage of the differential cross-coupled transistor pair, as depicted in Figure 22. More recent results have been published using FinFET or FDSOI technology [25,26,27]. Table 2 provides a comparison of LC tank performance with these latest works. The FOMs of the different circuits are quite similar, but this work exhibits a better phase noise with higher power consumption. The FOM is given by relation (8).

## 6. Conclusions

_{BIAS}of 0.6 V.

_{A}(cf. Figure 18). Therefore, if we divide the width of these two transistors by a factor of 10 (i.e., W

_{N1}= 3 µm instead of 30 µm and W

_{PA}= 10 µm instead of 100 µm), the current I

_{REF}is only 0.5 mA while the current in the output transistor (P

_{B}) remains at 5 mA for V

_{BIAS}= 0.6 V. This modification does not change the output current or the negative value of the equivalent resistance but allows the total consumption to be reduced to 5.1 mW instead of 9.26 mW. This modification also allows the size of the final integrated circuit to be reduced.

_{B}transistor if this length remains between 50 and 100 nm. We will conduct further studies, including process, voltage, and temperature (PVT) and Monte Carlo simulations, to fully evaluate the stability of the negative resistance and the performance of the LC VCO. However, it should be noted that this is more engineering work than research.

## Author Contributions

## Funding

## Data Availability Statement

## Conflicts of Interest

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**Figure 3.**Advantages of FDSOI technology for analog design [11].

**Figure 7.**Basic current mirrors with two different back-gate configurations: (

**a**) with one back-gate control and (

**b**) two calibrated back-gate control.

**Figure 10.**Simulations of a current mirror with BG control for different lengths of the output transistor.

**Figure 15.**LC tank oscillator based on new negative resistor where the red wires correspond to the back-gate biasing for each transistor.

**Figure 18.**Sizing of the LC tank oscillator (The red wires correspond to the back-gate biasing of each transistor).

V_{BIAS} (V) | I_{REF} (mA) | Settling Time (ns) | f_{osc} (GHz) | PN (dBc/Hz @1 MHz) |
---|---|---|---|---|

0.1–0.4 | No oscillation | |||

0.5 | 2.3 | 80 | 2.38 | −113 |

0.6 | 5.0 | 45 | 2.37 | −114 |

0.7 | 7.4 | 30 | 2.36 | −112 |

0.8 | 8.8 | 26 | 2.36 | −111 |

0.9 | 9.6 | 25 | 2.36 | −111 |

1.0 | 10.1 | 25 | 2.36 | −111 |

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**MDPI and ACS Style**

Mao, Y.; Charlon, Y.; Leduc, Y.; Jacquemod, G.
LC Tank Oscillator Based on New Negative Resistor in FDSOI Technology. *J. Low Power Electron. Appl.* **2024**, *14*, 8.
https://doi.org/10.3390/jlpea14010008

**AMA Style**

Mao Y, Charlon Y, Leduc Y, Jacquemod G.
LC Tank Oscillator Based on New Negative Resistor in FDSOI Technology. *Journal of Low Power Electronics and Applications*. 2024; 14(1):8.
https://doi.org/10.3390/jlpea14010008

**Chicago/Turabian Style**

Mao, Yuqing, Yoann Charlon, Yves Leduc, and Gilles Jacquemod.
2024. "LC Tank Oscillator Based on New Negative Resistor in FDSOI Technology" *Journal of Low Power Electronics and Applications* 14, no. 1: 8.
https://doi.org/10.3390/jlpea14010008