Next Article in Journal
Nanomaterial-Based Sensor Array Signal Processing and Tuberculosis Classification Using Machine Learning
Previous Article in Journal / Special Issue
Ultra-Low Power Programmable Bandwidth Capacitively-Coupled Chopper Instrumentation Amplifier Using 0.2 V Supply for Biomedical Applications
Order Article Reprints
Font Type:
Arial Georgia Verdana
Font Size:
Aa Aa Aa
Line Spacing:
Column Width:

Ultra-Low-Power ICs for the Internet of Things

Department of Electrical, Electronics and Telecommunication Engineering and Naval Architecture (DITEN), University of Genoa, 16100 Genova, Italy
J. Low Power Electron. Appl. 2023, 13(2), 38;
Received: 23 May 2023 / Accepted: 24 May 2023 / Published: 26 May 2023
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things)
The collection of research works in this Special Issue focuses on Ultra-Low-Power (ULP) Integrated Circuits (ICs) operating under a tight budget of power as a criterion to build electronic devices relying less and less on batteries. These enable the Internet of Things (IoT): a view of a world in which we are surrounded by devices that exchange data to enhance our quality of living. Thus, the goals of novel IC design strategies target both reducing the cost and the power consumption of any device. A method to reduce the cost is to minimize the use of a manual design process and maximize the use of a digital (automated) design flow so that the design is transferable across technological nodes. A digital-in-concept design also allows the scale of the supply voltage and offers a performance–power consumption trade-off [1,2,3,4]. In particular, a two-stage inverter-based operational transconductance amplifier (OTA) using rail-to-rail output operating with a supply voltage of 0.5 V is presented in [1]. Then, a novel implementation of a digital-based OTA consisting of only digital gates usually available in the standard cell libraries is the focus of [2]. In [3], a novel fully standard-cell-based common-mode feedback (CMFB) loop to improve the CMRR and to stabilize the DC output voltage of pseudo-differential standard-cell-based amplifiers is proposed. To further explore complexity, dynamic performance, and energy efficiency, a fully synthesizable digital–delta (Δ) modulator (ΔM) ADC with noise shaping using passive components (i.e., integrated capacitors and resistors) and standard-cell-based amplifiers is presented in [4].
The other research works exploit other methods, focusing on increasing the energy efficiency for a number of building blocks for general-purpose applications (i.e., amplifiers); more specifically, they target biomedical applications or at the system level. ULP/Ultra-Low-Voltage (ULV) ICs exploring bulk-drive solutions and operating with Sub-1V supply voltage down to 0.3 V were considered [5,6,7,8]. In [5], the authors proposed a new technique to improve the DC voltage gain, while keeping the high linearity in symmetrical bulk-driven (BD) OTA topology. A novel tree-based architecture that allows the implementation of a ULV OTA exploiting a body-driven input stage to guarantee a rail-to-rail input common mode range is also described in [6]. A bootstrapped BD Voltage Buffer is used to increase the intrinsic voltage gain of the Second-Order Gm-C Bandpass Filter in [7]. Moreover, a current-controlled CMOS ring oscillator topology, which exploits the bulk voltages of the inverter stages as control terminals to tune the oscillation frequency, is proposed and analyzed in [8]. Then, a fully differential (FD) instrumentation amplifier aimed at electrical impedance measurements in an IoT biomedical scenario is presented in [9].
To assist the ULP IC design flow, a compact and simplified approach that contains only four parameters and is based on the Advanced Compact MOSFET (ACM) model was implemented in Verilog-A and compared with the BSIM model in [10].
Sinusoidal oscillators based on second-generation voltage conveyors are investigated in [11], while a relaxation oscillator with valuable line sensitivity for Low Power Applications is shown in [12].
The last two studies in this Special Issue consider the IC as part of a ULP/ULV sensor system that needs to interact with the surrounding environment.
A wideband cascaded receiver including an inverter-based low-noise transconductance amplifier and a stacked receiver using an improved clock strategy with reduced mixer switches is described in [13]. Hardware solutions for Low-Power Smart Edge Computing are presented in [14].
In summary, the published research works cover a wide area of the ULP/ULV IC field, offering the reader many ideas inspired by these innovative design approaches.


The Guest Editor of the Special Issue “Ultra-Low-Power ICs for the Internet of Things” thanks the Multidisciplinary Digital Publishing Institute (MDPI) for the invitation to write this Editorial as a presentation of the 14 papers published in this Special Issue which is freely available at Moreover, based on the success of this Special Issue, a “Volume 2” has been launched at

Conflicts of Interest

The author declares no conflict of interest.


  1. Ballo, A.; Pennisi, S.; Scotti, G. 0.5 V CMOS Inverter-Based Transconductance Amplifier with Quiescent Current Control. J. Low Power Electron. Appl. 2021, 11, 37. [Google Scholar] [CrossRef]
  2. Palumbo, G.; Scotti, G. A Novel Standard-Cell-Based Implementation of the Digital OTA Suitable for Automatic Place and Route. J. Low Power Electron. Appl. 2021, 11, 42. [Google Scholar] [CrossRef]
  3. Centurelli, F.; Della Sala, R.; Scotti, G. A Standard-Cell-Based CMFB for Fully Synthesizable OTAs. J. Low Power Electron. Appl. 2022, 12, 27. [Google Scholar] [CrossRef]
  4. Correia, A.; Tavares, V.G.; Barquinha, P.; Goes, J. All-Standard-Cell-Based Analog-to-Digital Architectures Well-Suited for Internet of Things Applications. J. Low Power Electron. Appl. 2022, 12, 64. [Google Scholar] [CrossRef]
  5. Sanchotene Silva, R.; Rodovalho, L.H.; Aiello, O.; Ramos Rodrigues, C. A 1.9 nW, Sub-1 V, 542 pA/V Linear Bulk-Driven OTA with 154 dB CMRR for Bio-Sensing Applications. J. Low Power Electron. Appl. 2021, 11, 40. [Google Scholar] [CrossRef]
  6. Centurelli, F.; Della Sala, R.; Monsurrò, P.; Scotti, G.; Trifiletti, A. A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers. J. Low Power Electron. Appl. 2022, 12, 12. [Google Scholar] [CrossRef]
  7. Carrillo, J.M.; de la Cruz-Blas, C.A. 0.6-V 1.65-μW Second-Order Gm-C Bandpass Filter for Multi-Frequency Bioimpedance Analysis Based on a Bootstrapped Bulk-Driven Voltage Buffer. J. Low Power Electron. Appl. 2022, 12, 62. [Google Scholar] [CrossRef]
  8. Ballo, A.; Pennisi, S.; Scotti, G.; Venezia, C. A 0.5 V Sub-Threshold CMOS Current-Controlled Ring Oscillator for IoT and Implantable Devices. J. Low Power Electron. Appl. 2022, 12, 16. [Google Scholar] [CrossRef]
  9. Corbacho, I.; Carrillo, J.M.; Ausín, J.L.; Domínguez, M.Á.; Pérez-Aloe, R.; Duque-Carrillo, J.F. A Fully-Differential CMOS Instrumentation Amplifier for Bioimpedance-Based IoT Medical Devices. J. Low Power Electron. Appl. 2023, 13, 3. [Google Scholar] [CrossRef]
  10. Adornes, C.M.; Alves Neto, D.G.; Schneider, M.C.; Galup-Montoro, C. Bridging the Gap between Design and Simulation of Low-Voltage CMOS Circuits. J. Low Power Electron. Appl. 2022, 12, 34. [Google Scholar] [CrossRef]
  11. Stornelli, V.; Barile, G.; Pantoli, L.; Scarsella, M.; Ferri, G.; Centurelli, F.; Tommasino, P.; Trifiletti, A. A New VCII Application: Sinusoidal Oscillators. J. Low Power Electron. Appl. 2021, 11, 30. [Google Scholar] [CrossRef]
  12. Liao, Y.; Chan, P.K. A 1.1 V 25 ppm/°C Relaxation Oscillator with 0.045%/V Line Sensitivity for Low Power Applications. J. Low Power Electron. Appl. 2023, 13, 15. [Google Scholar] [CrossRef]
  13. Abbasi, A.; Nabki, F. Wideband Cascaded and Stacked Receiver Front-Ends Employing an Improved Clock-Strategy Technique. J. Low Power Electron. Appl. 2023, 13, 14. [Google Scholar] [CrossRef]
  14. Martin Wisniewski, L.; Bec, J.-M.; Boguszewski, G.; Gamatié, A. Hardware Solutions for Low-Power Smart Edge Computing. J. Low Power Electron. Appl. 2022, 12, 61. [Google Scholar] [CrossRef]
Disclaimer/Publisher’s Note: The statements, opinions and data contained in all publications are solely those of the individual author(s) and contributor(s) and not of MDPI and/or the editor(s). MDPI and/or the editor(s) disclaim responsibility for any injury to people or property resulting from any ideas, methods, instructions or products referred to in the content.

Share and Cite

MDPI and ACS Style

Aiello, O. Ultra-Low-Power ICs for the Internet of Things. J. Low Power Electron. Appl. 2023, 13, 38.

AMA Style

Aiello O. Ultra-Low-Power ICs for the Internet of Things. Journal of Low Power Electronics and Applications. 2023; 13(2):38.

Chicago/Turabian Style

Aiello, Orazio. 2023. "Ultra-Low-Power ICs for the Internet of Things" Journal of Low Power Electronics and Applications 13, no. 2: 38.

Note that from the first issue of 2016, this journal uses article numbers instead of page numbers. See further details here.

Article Metrics

Back to TopTop