Near-Threshold Voltage Design Techniques for Heterogenous Manycore System-on-Chips
Abstract
:1. Introduction
2. NTV Circuit Design Methodology
2.1. SRAM Memory and Register File (RF) Optimizations
2.2. Combinational Cells Design Criteria
2.3. Sequential Circuit Optimizations
2.4. Level Shifter Circuit Optimizations
3. Architecture Driven NTV Resilient NoC Fabrics
Resilient Router Architecture and Design
4. Designing for Wide-Dynamic Range: Tools, Flows and Methodologies
NTV Clocking Architecture
5. Key Results from Experimental NTV Prototypes
5.1. NTV-CPU Results
5.2. NTV-SIMD Engine Results
5.3. NTV-NoC Measurement Results and Learnings
Resilience to Inverse Temperature Dependence Effects
5.4. NTV-MCU Measurement Results and WSN Operation
6. Conclusions and Future Work
Author Contributions
Funding
Acknowledgments
Conflicts of Interest
References
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ISSCC 2012 [6] | ISSCC 2012 [8] | VLSI 2013 [10] | VLSI 2016 [11] | |
---|---|---|---|---|
NTV Design | 32-b ×86 CPU | SIMD Engine | 2D NoC fabric | mm-scale MCU |
Intel CMOS Technology | 32-nm high-K/metal-gate | 22-nm Tri-gate | 22-nm Tri-gate | 14nm Tri-gate |
Die Area (mm2) | 2 | 0.048 | Router: 0.051 2 × 2 Mesh: 0.93 | 0.79 |
VDD range and VOPT (V) | 0.28–1.2 (VOPT = 0.45) | 0.24–1.1 (VOPT = 0.26) | 0.34–0.85 (VOPT = 0.4) | 0.308–1.0 (VOPT = 0.37) |
Frequency range (MHz) | 3–915 | 10–2900 | 0.5–297 | 67–1000 |
Energy @ VOPT Benefit | 170pJ/cyclea, 4.7× | 1.9pJ/cycle, 9× | 36pJ/cycleb, 3.3× | 17.18pJ/cyclec, 4.8× |
Total on-chip memory | 8KB I$ + 8KB D$ | 1KB Reg. file (RF) memory | None | 8KB I$ + 8KB DTCM + 64KB SMEM + 16KB BootROM |
8T SRAM Device Type. | Gate Pitch | Normalized Frequency (0.5V) | Normalized Leakage (0.5V, 25C) | 14 nm Bit-Cell Area (µm2) |
---|---|---|---|---|
Standard performance (SP) | 70nm | 5× | 26× | 0.100 µm2 |
Ultralow power (ULP, NTV MCU Memory) | 84nm | 1× | 1× | 0.155 µm2 (1.55×) |
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Vangal, S.; Paul, S.; Hsu, S.; Agarwal, A.; Krishnamurthy, R.; Tschanz, J.; De, V. Near-Threshold Voltage Design Techniques for Heterogenous Manycore System-on-Chips. J. Low Power Electron. Appl. 2020, 10, 16. https://doi.org/10.3390/jlpea10020016
Vangal S, Paul S, Hsu S, Agarwal A, Krishnamurthy R, Tschanz J, De V. Near-Threshold Voltage Design Techniques for Heterogenous Manycore System-on-Chips. Journal of Low Power Electronics and Applications. 2020; 10(2):16. https://doi.org/10.3390/jlpea10020016
Chicago/Turabian StyleVangal, Sriram, Somnath Paul, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, James Tschanz, and Vivek De. 2020. "Near-Threshold Voltage Design Techniques for Heterogenous Manycore System-on-Chips" Journal of Low Power Electronics and Applications 10, no. 2: 16. https://doi.org/10.3390/jlpea10020016