A Minimum Leakage Quasi-Static RAM Bitcell
Abstract
:1. Introduction
2. The Proposed 9T Bitcell Design
2.1. Description
2.2. Write Operation
2.3. Read Operation
3. Cell Stability
3.1. Hold Stability
3.2. Read and Write Stability
4. Implementation and Performance
5. Conclusions
Process Technology | TSMC 40 nm LP | |
Simulator | Cadence spectre | |
# of Transistors | 9 | |
Minimum VDD | 300mV | |
Comparison with standard 8T bitcell | Hold ‘1’ State | Hold ‘0’ State |
Static Power Reduction @700 mV | 7.9× | 3.5× |
Static Power Reduction @1.1 V | 12× | 5.7× |
Read Access Ratio @700 mV | 1× | 1.74× |
Write Margin Ratio @700 mV | 2.2× | |
Write Access Ratio @700 mV | 0.17× |
Acknowledgments
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Teman, A.; Pergament, L.; Cohen, O.; Fish, A. A Minimum Leakage Quasi-Static RAM Bitcell. J. Low Power Electron. Appl. 2011, 1, 204-218. https://doi.org/10.3390/jlpea1010204
Teman A, Pergament L, Cohen O, Fish A. A Minimum Leakage Quasi-Static RAM Bitcell. Journal of Low Power Electronics and Applications. 2011; 1(1):204-218. https://doi.org/10.3390/jlpea1010204
Chicago/Turabian StyleTeman, Adam, Lidor Pergament, Omer Cohen, and Alexander Fish. 2011. "A Minimum Leakage Quasi-Static RAM Bitcell" Journal of Low Power Electronics and Applications 1, no. 1: 204-218. https://doi.org/10.3390/jlpea1010204