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Article

Novel 4H-SiC Double-Trench MOSFETs with Integrated Schottky Barrier and MOS-Channel Diodes for Enhanced Breakdown Voltage and Switching Characteristics

by
Peiran Wang
1,2,†,
Chenglong Li
2,†,
Chenkai Deng
2,3,
Qinhan Yang
2,
Shoucheng Xu
2,
Xinyi Tang
2,
Ziyang Wang
2,
Wenchuan Tao
2,
Nick Tao
4,
Qing Wang
2,5,* and
Hongyu Yu
1,2,5,*
1
School of Integrated Circuit, Shenzhen Polytechnic University, Shenzhen 518055, China
2
School of Microelectronics, Southern University of Science and Technology, Shenzhen 518055, China
3
School of Electronic Information and Engineering, Harbin Institute of Technology, Harbin 150001, China
4
Maxscend Microelectronics Co., Ltd., Wuxi 214072, China
5
Engineering Research Center of Integrated Circuits for Next-Generation Communications, Ministry of Education, Southern University of Science and Technology, Shenzhen 518055, China
*
Authors to whom correspondence should be addressed.
†
These authors contributed equally to this work.
Nanomaterials 2025, 15(12), 946; https://doi.org/10.3390/nano15120946
Submission received: 20 May 2025 / Revised: 16 June 2025 / Accepted: 17 June 2025 / Published: 18 June 2025
(This article belongs to the Section Nanoelectronics, Nanosensors and Devices)
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Versions Notes

Abstract

In this study, a novel silicon carbide (SiC) double-trench MOSFET (DT-MOS) combined Schottky barrier diode (SBD) and MOS-channel diode (MCD) is proposed and investigated using TCAD simulations. The integrated MCD helps inactivate the parasitic body diode when the device is utilized as a freewheeling diode, eliminating bipolar degradation. The adjustment of SBD position provides an alternative path for reverse conduction and mitigates the electric field distribution near the bottom source trench region. As a result of the Schottky contact adjustment, the reverse conduction characteristics are less influenced by the source oxide thickness, and the breakdown voltage (BV) is largely improved from 800 V to 1069 V. The gate-to-drain capacitance is much lower due to the removal of the bottom oxide, bringing an improvement to the turn-on switching rise time from 2.58 ns to 0.68 ns. These optimized performances indicate the proposed structure with both SBD and MCD has advantages in switching and breakdown characteristics.

1. Introduction

The silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) are commonly recognized as promising devices for high-voltage, high-temperature, and high-frequency application scenarios [1,2,3]. SiC-based devices are more competitive compared with Si-based devices, as they are a new class of power electronics components that solve the intrinsic limitations of silicon technology [4]. SiC MOSFETs have shown impressive characteristics like wider bandgap, higher thermal conductivity, and better switching performance, bringing significant advantages in power applications to reduce power loss and decrease system scale [5,6,7]. SiC trench MOSFETs feature lower specific ON-resistance (Ron,sp) by eliminating the junction field-effect transistor (JFET) region while bringing much more complicated manufacture processes [8]. Conventional SiC trench MOSFETs also have drawbacks like bipolar degradation and voltage drop due to the parasitic body diode [9]. These problems would make SiC MOSFETs not suitable for being driven as freewheeling diodes. Several methods to inactivate parasitic body diode and eliminate bipolar degradation have been introduced. A simple approach is to pair a SiC SBD externally, but it would increase the size of the system and integration cost [10,11].
Recently, the idea of integrating different kinds of diodes inside a device has been becoming increasingly popular. To suppress the bipolar degradation and the turn-on of the parasitic body diode, the integration of a Schottky barrier diode (SBD) or junction barrier Schottky diode (JBS) would solve the problems and improve the reverse performance [12,13,14,15,16,17,18]. Besides the SBD, a different kind of diode named the MOS-channel diode (MCD) is another feasible approach with which to eliminate the bipolar degradation and inactivate the parasitic body diode [19,20,21,22,23,24]. These methodologies of internal integration improve the freewheeling situation, while not benefiting the enhancement of breakdown voltage. The Schottky contact would be more vulnerable than the p-n diode structure when the device is under forward voltage, which would slightly decrease the breakdown voltage.
In this article, a SiC double-trench MOSFET embedded with both an MCD and SBD (MS-DTMOS) is proposed to further enhance the reverse performance and breakdown characteristics, and it is compared using Silvaco TCAD simulation [25] with a device with only an MCD (MCD-DTMOS). The integration of the MCD and SBD near the source trench region reduces the system cost of pairing an external SBD. While retaining the effect of inactivating the body diode and suppressing bipolar degradation, the pitch size is smaller than that integrating the two diodes separately. The introduction of the source SBD further enhances the switching performance and improves the breakdown characteristics, while bringing no extra volume. As a result of the Schottky contact adjustment, the reverse conduction characteristics are less influenced by the source oxide thickness, and the breakdown voltage (BV) is largely improved from 800 V to 1069 V. The gate-to-drain capacitance is much lower due to the removal of the bottom oxide, bringing an improvement to the turn-on switching rise time from 2.58 ns to 0.68 ns. These optimized performances indicate that the proposed structure with both an SBD and MCD has advantages in switching and breakdown characteristics.

2. Device Structure Design

The schematics of the proposed SiC MS-DTMOS and conventional MCD-DTMOS devices are shown in Figure 1. From bottom to top, both MOSFETs are constructed with an N+ substrate layer (N+ Sub), N drift layer, N current spreading layer (N-CSL), P base layer (P-base), and N+ layer. In both types of the SiC trench MOSFET, the MCD is integrated into the sidewall of the source trench region. The MOS-channel is formed by the source metal, source sidewall oxide, and the n-p-n structure. In the MS-DTMOS device, the bottom source oxide is removed to integrate the SBD. Thus, the SBD and MCD are both integrated into the SiC DTMOS near the source trench region. As the two diodes are integrated into one side of the device cell, the total device volume is reduced, resulting in a lower cost compared to the method of integrating two diodes separately. Table 1 lists the detailed parameters of the simulated devices.
When the device is working in reverse mode, the MCD or SBD would conduct before to the p-n diode near the gate trench region. The conduction of the p-n diode is suppressed. For the MS-DTMOS, the presence of the SBD provides an alternative current path concerning specific source oxide thickness (tsox), improving the reserve characteristics. However, the ability to control reverse current is different for the MCD affected by tsox, which would cause the phenomenon of dominance change between the SBD and MCD when the device is in reverse conduction mode.

3. Simulation Results and Discussion

3.1. Forward Output and Reverse Conduction Characteristics

The forward output and reverse conduction characteristics of the two devices at different values of gate voltage are shown in Figure 2. MS-DTMOS shows a larger reverse current than the MCD-DTMOS. The SBD structure inside the MS-DTMOS turns on and takes part in the reverse conduction. It provides an alternative path for reverse current, increasing the reverse current density. The MOS-channel diode turns on as the device switches to reverse mode as well. The capability to control the MCD is related to the source oxide thickness, and it becomes more apparent in the MS-DTMOS as the two diodes both exist. For MCD-DTMOS, the reverse conduction characteristic related to source oxide thickness is shown in Figure 2a. As the source oxide thickness increases, reverse current shifts to the negative side, which means the capability to control conduction is reduced. It becomes harder to be turned on when increasing the source oxide thickness. In Figure 2a, the reverse current characteristics of MS-DTMOS becomes similar when the source oxide thickness is above 20 nm. This is because the Schottky barrier diode maintains dominance when the source oxide is too thick for the MCD to conduct, while the SBD only requires a lower voltage to work.
The forward output characteristics of MS-DTMOS and MCD-DTMOS are presented in Figure 2b. Due to the current spreading area of MS-DTMOS being smaller than the current spreading area of MCD-DTMOS, as shown in Figure 3, the forward output current of MS-DTMOS is slightly lower than that of MCD-DTMOS. The introduction of the Schottky contact brings a slight drop in current density, resulting in a smaller forward current. When the SiC trench MOSFETs operate under forward voltage, the p-n diode near the gate region is turned to the on state, and current conduction through the MCD and SBD is suppressed.
Figure 4 shows the energy band diagrams extracted from source metal to N− CSL in the MS-DTMOS and MCD-DTMOS biased at Vgs = Vds = 20 V. For the MCD-DTMOS device, source metal–source oxide-N− CSL achieve a metal–insulator–semiconductor (MIS) structure. For the MS-DTMOS device, the N− CSL makes direct contact with the source metal and forms the Schottky barrier so that the conduction band is raised above the fermi energy level. Source oxide here can pull down the conduction band energy to below the fermi energy level so that the N− CSL-side conduction band energy in MCD-DTMOS is lower than that in MS-DTMOS devices. So, the depleted region area of MS-DTMOS is larger than that of MCD-DTMOS. When the devices are output mode, the current conduction path in MS-DTMOS will be limited compared to MCD-DTMOS so that the forward output current in MS-DTMOS is slightly lower than that of MCD-DTMOS.

3.2. Breakdown Characteristics and Electric Field Distribution

Figure 5 shows the off-state breakdown characteristics of the MS-DTMOS and the MCD-DTMOS. The breakdown voltage for MS-DTMOS is 1069 V, and for MCD-DTMOS, it is 800 V, which is an increase of 269 V.
To analyze the breakdown voltage characteristics, the electric field distributions at the off state, Vds = BV is displayed in Figure 6. The improved breakdown characteristics stem from the optimized electric field distribution, where the Schottky contact in MS-DTMOS mitigates field crowding at the source trench bottom, reducing peak field intensity from 6.0 MV/cm of the conventional MCD-DTMOS to 4.3 MV/cm of the MS-DTMOS. For MCD-DTMOS, the electric field concentrates on the source oxide sidewall, which leads the device to break down earlier. In the source–N− CSL Schottky junction, the electric field is governed by the depletion region modulated by the doping concentration and applied voltage, resulting in a smooth, laterally homogeneous distribution. Conversely, in the source–SiO2-N− CSL MIS structure, the presence of the SiO2 layer introduces dielectric mismatch (εr,ox < εr,sic), leading to localized field enhancement at SiO2 edges. Additionally, geometric fringe effects further distort the field in MIS structures. Consequently, MS-DTMOS achieves more predictable breakdown behavior, while MIS requires careful optimization of oxide quality and interface passivation to mitigate field non-uniformity and premature breakdown risks.

3.3. Parasitic Capacitance and Transient Characteristics

The parasitic capacitance characteristics of MS-DTMOS and MCD-DTMOS biased at 1 MHz, Vgs = 0 V, are exhibited in Figure 7. The drain-to-gate capacitance of MS-DTMOS is much lower due to the removal of the source button oxide layer [26]. Improvement in capacitance would result in better dynamic performance, indicating a better switching characteristic.
Figure 8 shows the turn-on switching test circuit and the switching characteristics of MS-DTMOS and MCD-DTMOS. The gate drive potential of DUT is a pulse rectangle wave with a 1 µs 15 V on-state signal and 3 µs −2 V signal off-state periodic operation. The rise time (Tr) of MS-DTMOS is 0.68 ns compared with the 2.58 ns of MCD-DTMOS due to the lower parasitic capacitance of MS-DTMOS. Therefore, MS-DTMOS appears to have a faster response speed than MCD-DTMOS, which shows great potential to reduce energy loss.
Figure 9 illustrates a feasible fabrication procedure of the proposed MS-DTMOS. Here, epitaxial layers comprising a 9 µm N− drift layer with an n-doped concentration of 7 × 1015 cm−3, a 1.4 µm N− CSL layer with an n-doped concentration of 1 × 1016 cm−3, a 0.5 µm P− base layer with a p-doped concentration of 3 × 1016 cm−3, and a 0.1 µm N+ layer with an n-doped concentration of 1 × 1019 cm−3 were grown on N+ 4H-SiC substrate with a doping concentration of 1 × 1018 cm−3, as shown in Figure 9a. Figure 9b displays that the gate trench region is created through inductively coupled plasma reactive ion etching (ICP-RIE). The P+ shielding layer is implanted using aluminum ions with a mask, as shown in Figure 9c. After the hard mask is removed, as shown in Figure 9d, the SiO2 layer is grown through low-pressure chemical vapor deposition (LPCVD) and region-selective etching as shown in Figure 9e. Using LPCVD, a p-type polysilicon layer is first deposited and subsequently etched back to create the lower polysilicon layer within the trench. Following this, n-type polysilicon is deposited to fill the trench and then etched back to achieve the configuration depicted in Figure 9f. With a similar procedure, the formation of the source trench region is completed, as displayed in Figure 9g, without the procedure of P+ implantation. Then, the SiO2 layer is grown through low-pressure chemical vapor deposition (LPCVD), as shown in Figure 9h, and region-selective etching, as shown in Figure 9i. Finally, the source and drain contact are formed after the isolation of the gate and source, as shown in Figure 9j. The described fabrication process outlines one potential implementation approach. However, substantial experimental verification and further development efforts remain necessary to realize the proposed device in practice.
Prior studies [27,28,29,30] have investigated various SiC MOSFET configurations with respect to their Ron, BV, and switching performance characteristics. As summarized in Table 2, the proposed MS-DTMOS structure demonstrates superior performance, particularly in achieving the shortest Tr among all compared device structures, indicating its potential for significantly reduced switching energy losses

4. Conclusions

In this article, a novel 4H-SiC DTMOS with Integrated Schottky barrier and MOS-channel diodes is proposed and investigated using ATLAS TCAD simulations. The proposed MS-DTMOS achieves a breakdown voltage of 1069 V, which is 269 V higher than that of the MCD-DTMOS. The 2D electric field distributions profile shows that a mitigation of the electric field peak is observed, contributing to a higher breakdown voltage. Furthermore, due to the removal of a source oxide layer in the MS-DTMOS structure, the parasitic capacitance is reduced. Hence, the turn-on time of MS-DTMOS is 0.68 ns compared to the 2.68 ns of MCD-DTMOS, revealing the potential for lower switching energy loss. In summary, the MS-DTMOS architecture significantly enhances breakdown voltage and switching speed while maintaining acceptable forward conduction performance, offering a promising solution for high-frequency power converters. This design is particularly suited for electric vehicle inverters and renewable energy systems, where high efficiency and compact integration are critical.

Author Contributions

Conceptualization, C.L. and P.W.; methodology, P.W.; software, C.L. and P.W.; validation, P.W., C.L. and C.D.; formal analysis, C.L. and N.T.; investigation, P.W.; resources, X.T.; data curation, Q.Y., S.X., Z.W. and W.T.; writing—original draft preparation, C.L.; writing—review and editing, P.W.; visualization, C.L. and P.W.; supervision, Q.W. and H.Y.; project administration, H.Y.; funding acquisition, H.Y. All authors have read and agreed to the published version of the manuscript.

Funding

This work was supported by Fabrication of Normally-Off GaN Devices based on in situ SiNx Passivation and Selective Area Growth Recessed-Gate Techniques and the Reliability Study (National Natural Science Foundation of China, grant no.: 62274082), Research on mechanism of Source/Drain ohmic contact and the related GaN p-FET (grant no.: 2023A1515030034), Research on high-reliable GaN power device and the related industrial power system (grant no.: HZQB-KCZYZ-2021052), Study on the reliability of GaN power devices (grant no.: JCYJ20220818100605012), Research on novelty low resistance Source/Drain ohmic contact for GaN p-FET (grant no.: JCYJ20220530115411025), the National Key R&D Program of China (2021YFB3600200), Guangdong Major Project of Basic and Applied Basic Research (2023B0303000012), the National Natural Science Foundation of China (62471011), and Research on GaN-based Devices for Industrial Applications (grant no.: 6025312001K).

Data Availability Statement

Data are contained within the article.

Conflicts of Interest

Nick Tao is currently employed at Maxscend Microelectronics Co., Ltd., and was employed by the company during the development of this manuscript. All contributions to this work and the manuscript were made independently, without any direction, guidance, or influence from the employer. Furthermore, no financial compensation was received from any source for Nick Tao’s contributions to this scientific work and manuscript. The remaining authors declare that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.

References

  1. Codreanu, C.; Avram, M.; Carbunescu, E.; Iliescu, E. Comparison of 3C–SiC, 6H–SiC and 4H–SiC MESFETs performances. Mater. Sci. Semicond. Process. 2000, 3, 137–142. [Google Scholar] [CrossRef]
  2. Zolper, J. Emerging silicon carbide power electronics components. In Proceedings of the Twentieth Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2005, Austin, TX, USA, 6–10 March 2025; pp. 11–17. [Google Scholar]
  3. Manikandan, E.; Agarwal, L. A Comprehensive Review of Recent Progress, Prospect and Challenges of Silicon Carbide and its Applications. Silicon 2022, 14, 12887–12900. [Google Scholar] [CrossRef]
  4. Li, L.; Li, C.; Cao, Y.; Wang, F. Recent progress of SiC power devices and applications. IEEJ Trans. Electr. Electron. Eng. 2013, 8, 515–521. [Google Scholar] [CrossRef]
  5. Akbar, G.; Di Fatta, A.; Rizzo, G.; Ala, G.; Romano, P.; Imburgia, A. Comprehensive Review of Wide-Bandgap (WBG) Devices: SiC MOSFET and Its Failure Modes Affecting Reliability. Physchem 2025, 5, 10. [Google Scholar] [CrossRef]
  6. Harasimczuk, M.; Kopacz, R.; Trochimiuk, P.; Miśkiewicz, R.; Rąbkowski, J. Experimental Investigation on SiC MOSFET Turn-Off Power Loss Reduction Using the Current Sink Capacitor Technique. Energies 2024, 17, 189. [Google Scholar] [CrossRef]
  7. Amirpour, S.; Thiringer, T.; Hagstedt, D. Power Loss Analysis in a SiC/IGBT Propulsion Inverter Including Blanking Time, MOSFET’s Reverse Conduction and the Effect of Thermal Feedback Using a PMSM Model. In Proceedings of the IECON 2020 The 46th Annual Conference of the IEEE Industrial Electronics Society, Singapore, 18–21 October 2020; pp. 1424–1430. [Google Scholar]
  8. Li, Y.; Cooper, J.; Capano, M. High-voltage (3 kV) UMOSFETs in 4H-SiC. IEEE Trans. Electron. Devices 2002, 49, 972–975. [Google Scholar] [CrossRef]
  9. Skowronski, M.; Ha, S. Degradation of hexagonal silicon-carbide-based bipolar devices. J. Appl. Phys. 2006, 99, 011101. [Google Scholar] [CrossRef]
  10. Pal, A.; Pilli, N.K.; Klumpner, C.; Ahmed, R. Improved Switching Performance of 3.3kV SiC MOSFETs using Synchronous Rectification in A Voltage Source Inverter. In Proceedings of the 2022 IEEE Applied Power Electronics Conference and Exposition (APEC), Houston, TX, USA, 20–24 March 2022; pp. 1–6. [Google Scholar]
  11. Ishigaki, T.; Hayakawa, S.; Murata, T.; Masuda, T.; Oda, T.; Takayanagi, Y. Diode-Less SiC Power Module With Countermeasures Against Bipolar Degradation to Achieve Ultrahigh Power Density. IEEE Trans. Electron. Devices 2020, 67, 2035–2043. [Google Scholar] [CrossRef]
  12. Sung, W.; Baliga, B.J. Monolithically Integrated 4H-SiC MOSFET and JBS Diode (JBSFET) Using a Single Ohmic/Schottky Process Scheme. IEEE Electron Device Lett. 2016, 37, 1605–1608. [Google Scholar] [CrossRef]
  13. Jiang, H.; Wei, J.; Dai, X.; Zheng, C.; Ke, M.; Deng, X.; Sharma, Y.; Deviny, I.; Mawby, P. SiC MOSFET with built-in SBD for reduction of reverse recovery charge and switching loss in 10-kV applications. In Proceedings of the 2017 29th International Symposium on Power Semiconductor Devices and IC’s (ISPSD), Sapporo, Japan, 28 May–1 June 2017; pp. 49–52. [Google Scholar]
  14. Matsui, K.; Aiba, R.; Yano, H.; Iwamuro, N.; Baba, M.; Harada, S. Comprehensive Study on Electrical Characteristics in 1.2 kV SiC SBD-integrated Trench and Planar MOSFETs. In Proceedings of the 2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD), Nagoya, Japan, 30 May–3 June 2021; pp. 215–218. [Google Scholar]
  15. Todaka, S.; Matsui, K.; Aiba, R.; Yano, H.; Iwamuro, N.; Baba, M.; Harada, S. Experimental and Numerical Demonstration of Superior RBSOAs in 1.2 kV SiC Trench and SBD-integrated Trench MOSFETs. In Proceedings of the 2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD), Nagoya, Japan, 30 May–3 June 2021; pp. 219–222. [Google Scholar]
  16. Han, K.; Agarwal, A.; Kanale, A.; Baliga, B.J.; Bhattacharya, S.; Cheng, T.-H.; Hopkins, D.; Amarasinghe, V.; Ransom, J. Monolithic 4-Terminal 1.2 kV/20 A 4H-SiC Bi-Directional Field Effect Transistor (BiDFET) with Integrated JBS Diodes. In Proceedings of the 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD), Vienna, Austria, 13–18 September 2020; pp. 242–245. [Google Scholar]
  17. Sundaresan, S.; Park, J.; Mulpuri, V.; Singh, R. Performance and Robustness of 6500 V SiC DMOSFETs with Integrated MPS diodes. In Proceedings of the 2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD), Nagoya, Japan, 30 May–3 June 2021; pp. 235–238. [Google Scholar]
  18. Li, X.; Tong, X.; Huang, A.Q.; Tao, H.; Zhou, K.; Jiang, Y.; Jiang, J.; Deng, X.; She, X.; Zhang, B.; et al. SiC Trench MOSFET With Integrated Self-Assembled Three-Level Protection Schottky Barrier Diode. IEEE Trans. Electron. Devices 2017, 65, 347–351. [Google Scholar] [CrossRef]
  19. Uchida, M.; Horikawa, N.; Tanaka, K.; Takahashi, K.; Kiyosawa, T.; Hayashi, M.; Niwayama, M.; Kusumoto, O.; Adachi, K.; Kudou, C.; et al. Novel SiC power MOSFET with integrated unipolar internal inverse MOS-channel diode. In Proceedings of the 2011 International Electron Devices Meeting, Washington, DC, USA, 5–7 December 2011; pp. 26.6.1–26.6.4. [Google Scholar] [CrossRef]
  20. Zhang, M.; Wei, J.; Zhou, X.; Jiang, H.; Li, B.; Chen, K.J. Simulation Study of a Power MOSFET with Built-in Channel Diode for Enhanced Reverse Recovery Performance. IEEE Electron Device Lett. 2019, 40, 79–82. [Google Scholar] [CrossRef]
  21. Zhou, X.; Gong, H.; Jia, Y.; Hu, D.; Wu, Y.; Xia, T.; Pang, H.; Zhao, Y. SiC Planar MOSFETs With Built-In Reverse MOS-Channel Diode for Enhanced Performance. IEEE J. Electron Devices Soc. 2020, 8, 619–625. [Google Scholar] [CrossRef]
  22. Deng, X.; Xu, X.; Li, X.; Li, X.; Wen, Y.; Chen, W. A Novel SiC MOSFET Embedding Low Barrier Diode With Enhanced Third Quadrant and Switching Performance. IEEE Electron Device Lett. 2020, 41, 1472–1475. [Google Scholar] [CrossRef]
  23. Li, P.; Guo, J.; Hu, S.; Lin, Z. A SiC Planar MOSFET with an Embedded MOS-Channel Diode to Improve Reverse Conduction and Switching. Micromachines 2023, 14, 1282. [Google Scholar] [CrossRef] [PubMed]
  24. Wei, J.; Jiang, Q.; Luo, X.; Huang, J.; Yang, K.; Ma, Z.; Fang, J.; Yang, F. High performance SiC trench-type MOSFET with an integrated MOS-channel diode. Chin. Phys. B 2023, 32, 028503. [Google Scholar] [CrossRef]
  25. ATLAS User’s Manual; Silvaco Int.: Santa Clara, CA, USA, 2010.
  26. Luo, X.; Liao, T.; Wei, J.; Fang, J.; Yang, F.; Zhang, B. A novel 4H-SiC trench MOSFET with double shielding structures and ultralow gate-drain charge. J. Semicond. 2019, 40, 052803. [Google Scholar] [CrossRef]
  27. Han, Z.; Bai, Y.; Chen, H.; Li, C.; Lu, J.; Yang, C.; Yao, Y.; Tian, X.; Tang, Y.; Song, G.; et al. A novel 4H-SiC trench MOSFET integrated with mesa-sidewall SBD. IEEE Trans. Electron. Devices 2020, 68, 192–196. [Google Scholar] [CrossRef]
  28. Tian, K.; Hallen, A.; Qi, J.; Ma, S.; Fei, X.; Zhang, A.; Liu, W. An improved 4H-SiC trench-gate MOSFET with low ON-resistance and switching loss. IEEE Trans. Electron. Devices 2019, 66, 2307–2313. [Google Scholar] [CrossRef]
  29. Huang, M.; Deng, Y.; Lai, L.; Yang, Z.; Gao, B.; Gong, M. A vertical superjunction MOSFET with n-Si and p-3C-SiC pillars. IEEE Trans. Electron. Devices 2019, 66, 3922–3928. [Google Scholar] [CrossRef]
  30. Yang, T.; Wang, Y.; Yue, R. SiC trench MOSFET with reduced switching loss and increased short-circuit capability. IEEE Trans. Electron. Devices 2020, 67, 3685–3690. [Google Scholar] [CrossRef]
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Figure 1. Schematic cross-sectional view of SiC (a) MS-DTMOS and (b) MCD-DTMOS.
Figure 1. Schematic cross-sectional view of SiC (a) MS-DTMOS and (b) MCD-DTMOS.
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Figure 2. (a) Reverse conduction and (b) forward output characteristics of MS-DTMOS and MCD-DTMOS devices with different tsox values.
Figure 2. (a) Reverse conduction and (b) forward output characteristics of MS-DTMOS and MCD-DTMOS devices with different tsox values.
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Figure 3. Current density distribution of (a) MS-DTMOS and (b) MCD-DTMOS when the devices are in output mode.
Figure 3. Current density distribution of (a) MS-DTMOS and (b) MCD-DTMOS when the devices are in output mode.
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Figure 4. Energy band and electron concentration distribution at x = 0.2 μm of MS-DTMOS and MCD-DTMOS extracted from the source to drain.
Figure 4. Energy band and electron concentration distribution at x = 0.2 μm of MS-DTMOS and MCD-DTMOS extracted from the source to drain.
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Figure 5. Breakdown characteristics of MS-DTMOS and MCD-DTMOS.
Figure 5. Breakdown characteristics of MS-DTMOS and MCD-DTMOS.
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Figure 6. Electric field distribution of (a) MS-DTMOS at Vds = 1069 V and (b) MCD-DTMOS at Vds = 800 V.
Figure 6. Electric field distribution of (a) MS-DTMOS at Vds = 1069 V and (b) MCD-DTMOS at Vds = 800 V.
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Figure 7. Parasitic capacitance characteristics biased at Vgs = 0 V of MS-DTMOS and MCD-DTMOS.
Figure 7. Parasitic capacitance characteristics biased at Vgs = 0 V of MS-DTMOS and MCD-DTMOS.
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Figure 8. Turn-on switching test: (a) circuit and (b) switching characteristics of MS-DTMOS and MCD-DTMOS.
Figure 8. Turn-on switching test: (a) circuit and (b) switching characteristics of MS-DTMOS and MCD-DTMOS.
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Figure 9. Proposed fabrication procedure steps of MS-DTMOS. (a) Epitaxial layer grown on 4H-SiC substrate. (b) Form trench by ICP-RIE. (c) Form p+ shielding region by implantation. (d) Mask removed by BOE wet etch. (e) Form gate oxide by thermal oxidation and ICP-RIE. (f) Form gate electrode by LPCVD. (g) Form trench by ICP-RIE. (h) Form source oxide by thermal oxidation. (i) Remove bottom oxide of source by ICP-RIE. (j) Form source and drain electrode by LPCVD.
Figure 9. Proposed fabrication procedure steps of MS-DTMOS. (a) Epitaxial layer grown on 4H-SiC substrate. (b) Form trench by ICP-RIE. (c) Form p+ shielding region by implantation. (d) Mask removed by BOE wet etch. (e) Form gate oxide by thermal oxidation and ICP-RIE. (f) Form gate electrode by LPCVD. (g) Form trench by ICP-RIE. (h) Form source oxide by thermal oxidation. (i) Remove bottom oxide of source by ICP-RIE. (j) Form source and drain electrode by LPCVD.
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Table 1. Device parameters for simulations.
Table 1. Device parameters for simulations.
ParametersValues
N− Drift layer thickness (TDrift)9 µm
N− Drift layer concentration (NDrift)7 × 1015/cm3
N− CSL layer thickness (TCSL)1.4 µm
N− CSL Concentration (NCSL)1 × 1016/cm3
Trench size1.0 × 1.0 µm
Source length (Lsource)1.0 µm
P− base layer length (LBase)0.63 µm
P− base layer thickness (Tch)0.5 µm
P− base layer concentration (Nbase)3 × 1016/cm3
N+/P+ concentration (NN+)1 × 1019/cm3
N+ layer thickness (TN+)0.1 µm
N+ Sub layer concentration (NSub)1 × 1018/cm3
N+ Sub layer thickness (TSub)1 µm
Table 2. Summary of the performance parameters of this work compared with previous work.
Table 2. Summary of the performance parameters of this work compared with previous work.
ParametersPrevious Work [27,28,29,30]This Work
[27][28][29][30]
Ron. sp (mΩ·mm)1.982.315.11.283.2
BV (V)1200129060615601069
Tr (ns)1116.32.633.40.68
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MDPI and ACS Style

Wang, P.; Li, C.; Deng, C.; Yang, Q.; Xu, S.; Tang, X.; Wang, Z.; Tao, W.; Tao, N.; Wang, Q.; et al. Novel 4H-SiC Double-Trench MOSFETs with Integrated Schottky Barrier and MOS-Channel Diodes for Enhanced Breakdown Voltage and Switching Characteristics. Nanomaterials 2025, 15, 946. https://doi.org/10.3390/nano15120946

AMA Style

Wang P, Li C, Deng C, Yang Q, Xu S, Tang X, Wang Z, Tao W, Tao N, Wang Q, et al. Novel 4H-SiC Double-Trench MOSFETs with Integrated Schottky Barrier and MOS-Channel Diodes for Enhanced Breakdown Voltage and Switching Characteristics. Nanomaterials. 2025; 15(12):946. https://doi.org/10.3390/nano15120946

Chicago/Turabian Style

Wang, Peiran, Chenglong Li, Chenkai Deng, Qinhan Yang, Shoucheng Xu, Xinyi Tang, Ziyang Wang, Wenchuan Tao, Nick Tao, Qing Wang, and et al. 2025. "Novel 4H-SiC Double-Trench MOSFETs with Integrated Schottky Barrier and MOS-Channel Diodes for Enhanced Breakdown Voltage and Switching Characteristics" Nanomaterials 15, no. 12: 946. https://doi.org/10.3390/nano15120946

APA Style

Wang, P., Li, C., Deng, C., Yang, Q., Xu, S., Tang, X., Wang, Z., Tao, W., Tao, N., Wang, Q., & Yu, H. (2025). Novel 4H-SiC Double-Trench MOSFETs with Integrated Schottky Barrier and MOS-Channel Diodes for Enhanced Breakdown Voltage and Switching Characteristics. Nanomaterials, 15(12), 946. https://doi.org/10.3390/nano15120946

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