Article Versions Notes

Zhang Q, Gu J, Xu R, Cao L, Li J, Wu Z, Wang G, Yao J, Zhang Z, Xiang J, et al. Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices. Nanomaterials. 2021; 11(3):646. https://doi.org/10.3390/nano11030646

Zhang, Qingzhu, Jie Gu, Renren Xu, Lei Cao, Junjie Li, Zhenhua Wu, Guilei Wang, Jiaxin Yao, Zhaohao Zhang, Jinjuan Xiang, and et al. 2021. "Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices" Nanomaterials 11, no. 3: 646. https://doi.org/10.3390/nano11030646

Zhang, Q., Gu, J., Xu, R., Cao, L., Li, J., Wu, Z., Wang, G., Yao, J., Zhang, Z., Xiang, J., He, X., Kong, Z., Yang, H., Tian, J., Xu, G., Mao, S., Radamson, H. H., Yin, H., & Luo, J. (2021). Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices. Nanomaterials, 11(3), 646. https://doi.org/10.3390/nano11030646