Combinational Circuits Testing Based on Hsiao Codes with Self-Dual Check Functions

Abstract

This paper investigates the features of using modified Hamming codes, which are also known as Hsiao codes. Self-checking digital devices are proposed to be implemented with calculations testing using two diagnostic signs. These signs indicate that the functions (there are functions that describe check bits) belong to the class of self-dual Boolean functions and also belong to the codewords of Hsiao codes (these are codes with an odd column of weights). The authors have established that all check functions can be self-dual for a certain number of the Hsiao codes’ data symbols. Such codes can be used in the synthesis of concurrent error-detection circuits by two diagnostic signs. The paper describes the structure of an organization for a concurrent error-detection circuit based on Hsiao codes with self-dual check functions. Some experimental results are presented on the synthesis of self-checking devices using the proposed methodology. The controllability of the structure and the number of test combinations both increased. Hsiao codes can be effectively used with self-dual check functions in the synthesis of self-checking digital devices.

1. Introduction

The methods of redundancy and technical diagnostics are widely applied in the construction of highly reliable safety devices and operation systems [1,2,3,4,5,6]. Time redundancy is one of the ways to add redundancy. The time redundancy implies the availability of a time resource to perform procedures for checking and performance restoration of the original object [7]. Self-testing and self-checking digital devices are created when using a time redundancy along with a special representation of signals [8,9]. Calculations testing is convenient to use in this case when functions belonged to special classes of Boolean functions such as monotonous, linear and/or self–dual functions [10,11,12,13,14]. Let us focus on the combination of linearity and self-duality of generated functions when performing calculations testing using time redundancy and the pulse mode of operation. Linear redundant codes can be used for this [15,16]. Such double calculations testing makes it possible to enhance the controllability of a final self-checking device and to ensure the testing of faults and errors in calculations over a much larger number of input combinations. This will not be effective when using a single diagnostic sign.

It should be noted that the calculations testing by two signs has already been considered in several papers. The authors of [17,18] report the features of the organization of calculations testing using the control of monotonicity and self-duality of calculated functions. The first property relates to the functions that generate the values for the codewords bits in the «r-out-of-2r» constant-weight codes, where r is the codeword weight. The second property relies on the use of a method for logical signals correction, or logical complement [19,20,21], in a concurrent error-detection circuit (CED). Additionally, the values are generated by each input set of codewords and must be such that each function describes the digits of a self-dual codeword. The authors of [15,16] report that classical and modified Hamming codes [22] can also be used for calculations testing by two diagnostic signs. These codes have the property of self-dual functions (which describe the check bits) for certain data symbols values. An example is also given for the synthesis of a device with the calculations testing by two signs for a four-output device.

The author of [23] reports that one of the well-known modifications of Hamming codes is the odd-weight-column codes. These codes are called by the name of their discoverer, Hsiao. They are often used in the implementation of devices with error detection and correction [24,25]. They are linear and have self-dual functions, which describe the check bits under certain conditions.

A large number of works are devoted to the use of Hsiao codes for the organization of CED circuits. Papers [26,27,28] report that these codes are used to calculate the testing and correct errors at the cache level of the memory hierarchy to increase reliability. However, in all papers, only the sign of control is used, which relates to the codewords of Hsiao codes. These papers focus on the application of Hsiao codes for the organization of CED circuits. The authors of this paper conducted an analysis and discovered that the Hsiao codes also have another “natural” property in which their check symbols are described by self-dual Boolean functions under certain conditions. In this paper, we propose a way to organize CED circuits. There is another diagnostic sign in the Hsiao code that is embedded within the Hsiao code at certain values of the number of data symbols and conditions for code construction. In the paper, the CED circuit is developed based on two diagnostic signs. It has improved performance indicators compared to well-known structures, for example, from [13,14], as well as traditional ones [29,30].

2. The Hsiao Codes

The Hsiao codes are generated in accordance with the following rules [31]:

• The value of the number of data symbols m is the selected item.
• All columns are assigned to check symbols in the check matrix with weight r = 1 (their number is $\left(\begin{array}{c}k\\ 1\end{array}\right),$ where k is the number of check symbols and the number of rows in the matrix).
• All columns are selected sequentially with an odd weight value r = 3, 5, 7, … corresponding to data symbols $\left(\begin{array}{c}k\\ 3\end{array}\right)$ columns with an odd weight r = 3; then, $\left(\begin{array}{c}k\\ 5\end{array}\right)$ columns are selected with an odd of weight r = 5, and so on, until m columns have been selected with an odd weight.

Table 1. Parameters of the Hsiao codes.

k	Nr	mmax
4	$\left(\begin{array}{c}4\\ 3\end{array}\right)$	4
5	$\left(\begin{array}{c}5\\ 3\end{array}\right)+\left(\begin{array}{c}5\\ 5\end{array}\right)$	11
6	$\left(\begin{array}{c}6\\ 3\end{array}\right)+\left(\begin{array}{c}6\\ 5\end{array}\right)$	26
7	$\left(\begin{array}{c}7\\ 3\end{array}\right)+\left(\begin{array}{c}7\\ 5\end{array}\right)+\left(\begin{array}{c}7\\ 7\end{array}\right)$	57
8	$\left(\begin{array}{c}8\\ 3\end{array}\right)+\left(\begin{array}{c}8\\ 5\end{array}\right)+\left(\begin{array}{c}8\\ 7\end{array}\right)$	120
9	$\left(\begin{array}{c}9\\ 3\end{array}\right)+\left(\begin{array}{c}9\\ 5\end{array}\right)+\left(\begin{array}{c}9\\ 7\end{array}\right)+\left(\begin{array}{c}9\\ 9\end{array}\right)$	247
10	$\left(\begin{array}{c}10\\ 3\end{array}\right)+\left(\begin{array}{c}10\\ 5\end{array}\right)+\left(\begin{array}{c}10\\ 7\end{array}\right)+\left(\begin{array}{c}10\\ 9\end{array}\right)$	502

reports the values of m for various k. m_max is the maximum value of the number m for a particular k, and N_r is the total number of columns with an odd weight r: $\left(\begin{array}{c}k\\ 3\end{array}\right)+\left(\begin{array}{c}k\\ 5\end{array}\right)+\dots +\left(\begin{array}{c}k\\ l\end{array}\right),$ l = m, if m is an odd, l = m–1, if m is an even.

The Hsiao codes can be generated by using a check matrix. The columns are removed with a weight of r = 1 in this matrix (these columns correspond to check symbols), and all other columns remain (these columns correspond to data symbols). The value of the y_i, $i=\overline{1,k}$ bit is calculated as the sum modulo M = 2 data symbols, for which 1 is present in the intersection of the i-th row and all columns that have a weight r ≥ 3. A check matrix is given for the Hsiao codes with the value k = 5:

$$H_5=\left(\begin{array}{ccccccccccc}0& 0& 0& 0& 1& 1& 1& 1& 1& 1& 1\\ 0& 1& 1& 1& 0& 0& 0& 1& 1& 1& 1\\ 1& 0& 1& 1& 0& 1& 1& 0& 0& 1& 1\\ 1& 1& 0& 1& 1& 0& 1& 0& 1& 0& 1\\ 1& 1& 1& 0& 1& 1& 0& 1& 0& 0& 1\end{array}\right).$$

(1)

The maximum number of data symbols in the Hsiao code for a given value k is determined by

$$m_{\max }={\displaystyle \sum _{r=1+2j}\left(\begin{array}{c}k\\ r\end{array}\right)},j=1,2,\dots ,⌊{\displaystyle \frac{k}{2}}⌋.$$

(2)

It follows from the last formula that the number of ways to build a code with the value m ≤ m_max is determined by

$$N_{k,m}=\left(\begin{array}{c}{m}_{\max }\\ m\end{array}\right).$$

(3)

The permutation of columns in check matrices allows for the construction of Hsiao codes by selecting m columns from a max with various arguments used in formulas to determine the check symbols. For example, for m = 7, we have $N_{5,7}=\left(\begin{array}{c}11\\ 7\end{array}\right)=330$.

Research has shown that the Hsiao codes possess the property of detecting errors with multiplicities d ≤ 3. Specifically, these codes are endowed with corrective properties. These are the features of the Hsiao codes that can be considered when designing self-checking combinational circuits. Therefore, this paper will focus on the detecting abilities of these codes. We will consider the codewords’ bits on the outputs of diagnostic objects belonging to the calculated Hsiao codes in the CED as a diagnostic sign. Additionally, another feature of these codes can serve as a second diagnostic sign. Some methods for constructing generating matrices produce Hsiao codes, whose check symbols are determined by self-dual Boolean functions. The authors of [15,16,17,18] have shown that using two diagnostic signs can increase the number of test combinations in which one or another fault of the diagnostic object is manifested.

The author of [16] reports that a linear Boolean function is self-dual if it has an odd number of arguments on which it significantly depends. Therefore, among the Hsiao codes, those can be selected for which all the check symbols will have the property of self-duality of Boolean functions. Analysis of the check matrix (1) showed that codes with k = 5 can be constructed for the cases where the number of data symbols is m = 5, 7 and 11. Next, we will demonstrate how to select Hsiao codes that use self-dual Boolean functions to describe the check symbols.

3. Structure of the Concurrent Error-Detection Circuit

From (1), we derive the following system of functions describing the check symbols (check functions):

$$H_5=\left(\begin{array}{ccccccc}0& 0& 0& 0& 1& 1& 1\\ 0& 1& 1& 1& 0& 0& 0\\ 1& 0& 1& 1& 0& 1& 1\\ 1& 1& 0& 1& 1& 0& 1\\ 1& 1& 1& 0& 1& 1& 0\end{array}\right).$$

(4)

From (4), we derive the following system of functions describing the check symbols:

$$\left\{\begin{array}{l}{g}_1=f_1\oplus f_2\oplus f_3\oplus f_5\oplus f_6;\\ g_2=f_1\oplus f_2\oplus f_4\oplus f_5\oplus f_7;\\ g_3=f_1\oplus f_3\oplus f_4\oplus f_6\oplus f_7;\\ g_4=f_2\oplus f_3\oplus f_4;\\ g_5=f_5\oplus f_6\oplus f_7.\end{array}\right.$$

(5)

In Formula (5), all five functions (which describe the check symbols) have an odd number of arguments. The authors of [15,16] state that any linear Boolean function is self-dual with an odd number of arguments. Since all five functions are self-dual, the Hsiao code encoder is a self-dual digital device implemented by Formula (5).

The authors of [15,16] report the method for using classical and modified Hamming codes in the synthesis of the CED according to two diagnostic signs. We implement a structure of CED using the Hsiao code, which is describing check symbols by the system (5). Figure 1 illustrates this. Block G(f) is implemented by Formula (5) and is a encoder of the Hsiao code. The cascade connection of the diagnostic object F(x) and the encoder G(f) result in the formation of block G(x), which is then optimized further. Both devices, G(f) and G(x), perform identical functions, and their eponymous outputs are compared at the inputs of the comparator 5TRC1. This is implemented using four modules of two-rail checkers TRC (check pair A). The comparator operates in two-rail logic; therefore, the signals from block G(x) are previously inverted. On the other hand, the outputs of the encoder G(f) are controlled by the device 5SSC1 (check pair B). A self-dual self-checking checker (SSC) has been installed on each output, and the control outputs from each self-dual checker are connected to the inputs of the 5TRC1 two-rail signal comparator. The outputs from two comparators (subcircuits for the testing belonging to the Hsiao codes and subcircuits for the testing the self-duality of check functions) are connected to the inputs of one module of the two-rail checker TRC (check pair C). The outputs of the last are the check outputs of the CED.

Figure 1 illustrates the basic structure, which is implemented for a group of seven outputs. The devices with $m\left(\mathrm{mod}7\right)\ne 0$ outputs are controlled by allocating several groups of outputs. At the same time, they can be divided into groups of seven outputs each, allowing for intersection. Individual outputs can only be controlled on the sign of self-duality.

4. Experiments with Benchmarks

We considered a non-self-dual test combination circuit (benchmark). This was implemented in the bases of NOR (OR-NOT) gates. Any Boolean function can be converted into a self-dual function with only one additional (alternative) variable a [8] required. For example, the following expression is used to convert the function $f_{NOR2}=x_1\downarrow x_2$ [32]:

$$f_{NOR2}^{SD}=\overline{a}\left(\overline{x_1}\vee \overline{x_2}\right)x_1{x}_2.$$

(6)

Therefore, a self-dual analogue can be realized by introducing structural redundancy into the source object.

Figure 2 demonstrates that by replacing each logic gate in the source circuit with a self-dual analogue, a self-dual circuit is generated.

Next, the CED (not provided due to cumbersomeness) was implemented according to a given structure with the testing by two diagnostic signs. Figure 1 illustrates these signs, such as testing calculations using the Hsiao codes and each checking function belonging to the class of self-dual Boolean functions. The operation of the final device was simulated in a pulsed mode of operation, in which the input was sent pairs of ax₁x₂x₃x₄x₅ input combinations orthogonal by all variables to the inputs: (000000, 111111), (000001, 111110), …, (011111, 100000). At the same time, both regular operation and operation under the influence of a single stuck-at fault were simulated at the outputs of the self-dual analogues of the functional gates of the source circuit (total of 24 faults). We have reported the features of modeling self-dual circuits in [15,16].

Figure 3 illustrates time diagrams of the circuit operation when introducing stuck-at-0 and stuck-at-1 faults at the output of the selected cascade in Figure 2. It also shows diagrams for devices SSC1…SSC5 and TRC7…TRC9. The first five devices are self-dual checkers controlling the checking functions g₁…g₅. The TRC7 gate is a check gate of a check subcircuit regarding the self-duality of signals from gates SSC1…SSC5. The TRC8 gate is the check gate of the calculation testing subcircuit belonging to the checking functions joined with digits of the Hsiao code. The TRC9 gate is the check output of the CED. The outputs of the TRC7…TRC9 gates are of interest, as check signals can be observed on them. If a two-rail signal is violated, it indicates that an error has occurred.

Figure 3 illustrates the operation of the structure shown in Figure 1 for the given benchmark, focusing only on its control outputs. Pairs of control and check combinations are supplied to the inputs of device with a CED circuit. These combinations are presented in

Table 2. Tables should be placed in the main text near to the first time they are cited.

Pair Number	ax1x2x3x4x5	TRC7 0/1 B	TRC7 0/1 A	TRC7 0/1 C	Pair Number	ax1x2x3x4x5	TRC7 0/1 B	TRC7 0/1 A	TRC7 0/1 C
1	000000	1/0	0/1	1/0	17	010000	1/0	1/0	0/1
	111111	1/1	1/1	1/1		101111	1/1	1/1	1/1
2	000001	1/0	1/0	0/1	18	010001	1/0	1/0	0/1
	111110	0/1	0/1	0/1		101110	1/1	1/1	1/1
3	000010	1/0	0/1	1/0	19	010010	1/0	1/0	0/1
	111101	1/1	1/1	1/1		101101	1/1	1/1	1/1
4	000011	1/0	0/1	1/0	20	010011	1/0	0/1	1/0
	111100	1/0	1/0	0/1		101100	1/1	1/1	1/1
5	000100	1/0	1/1	1/1	21	010100	1/0	1/1	1/1
	111011	1/1	0/1	1/1		101011	1/1	1/0	1/1
6	000101	1/0	0/1	1/0	22	010101	1/0	0/0	0/0
	111010	1/0	1/0	0/1		101010	0/0	0/1	0/0
7	000110	1/0	0/1	1/0	23	010110	1/0	0/1	1/0
	111001	1/1	1/1	1/1		101001	1/1	1/1	1/1
8	000111	1/0	0/1	1/0	24	010111	1/0	1/0	0/1
	111000	1/0	1/0	0/1		101000	0/0	0/0	0/0
9	001000	1/0	1/0	0/1	25	011000	1/0	1/0	0/1
	110111	1/1	1/1	1/1		100111	1/1	1/1	1/1
10	001001	1/0	1/0	0/1	26	011001	1/0	1/0	0/1
	110110	1/1	1/1	1/1		100110	1/1	1/1	1/1
11	001010	1/0	1/0	0/1	27	011010	1/0	1/0	0/1
	110101	1/1	1/1	1/1		100101	1/1	1/1	1/1
12	001011	1/0	0/1	1/0	28	011011	1/0	0/1	1/0
	110100	1/1	1/1	1/1		100100	1/1	1/1	1/1
13	001100	1/0	1/1	1/1	29	011100	1/0	1/1	1/1
	110011	1/1	1/0	1/1		100011	1/1	1/0	1/1
14	001101	1/0	0/0	0/0	30	011101	1/0	0/0	0/0
	110010	0/0	0/1	0/0		100010	0/0	0/1	0/0
15	001110	1/0	0/1	1/0	31	011110	1/0	0/1	1/0
	110001	1/1	1/1	1/1		100001	1/1	1/1	1/1
16	001111	1/0	1/0	0/1	32	011111	1/0	1/0	0/1
	110000	0/0	0/0	0/0		100000	0/0	0/0	0/0

and

Table 3. The results of testing the introduced fault type stuck-at-1.

Pair Number	ax1x2x3x4x5	TRC7 0/1 B	TRC7 0/1 A	TRC7 0/1 C	Pair Number	ax1x2x3x4x5	TRC7 0/1 B	TRC7 0/1 A	TRC7 0/1 C
1	000000	1/0	1/1	1/1	17	010000	1/0	1/1	1/1
	111111	1/1	1/0	1/1		101111	1/1	0/1	1/1
2	000001	1/0	1/0	0/1	18	010001	1/0	0/0	0/0
	111110	0/1	0/1	0/1		101110	0/0	0/1	0/0
3	000010	1/0	1/1	1/1	19	010010	1/0	1/1	1/1
	111101	1/1	1/0	1/1		101101	1/1	0/1	1/1
4	000011	1/0	0/1	1/0	20	010011	1/0	1/1	1/1
	111100	1/0	1/0	0/1		101100	1/1	1/0	1/1
5	000100	1/0	1/0	0/1	21	010100	1/0	0/1	1/0
	111011	1/1	1/1	1/1		101011	1/1	1/1	1/1
6	000101	1/0	0/1	1/0	22	010101	1/0	1/0	0/1
	111010	1/0	1/0	0/1		101010	1/1	1/1	1/1
7	000110	1/0	1/1	1/1	23	010110	1/0	1/1	1/1
	111001	1/1	1/0	1/1		101001	1/1	1/0	1/1
8	000111	1/0	0/1	1/0	24	010111	1/0	1/1	1/1
	111000	1/0	1/0	0/1		101000	1/1	0/1	1/1
9	001000	1/0	1/1	1/1	25	011000	1/0	1/1	1/1
	110111	1/1	0/1	1/1		100111	1/1	0/1	1/1
10	001001	1/0	0/0	0/0	26	011001	1/0	0/0	0/0
	110110	0/0	0/1	0/0		100110	0/0	0/1	0/0
11	001010	1/0	1/1	1/1	27	011010	1/0	1/1	1/1
	110101	1/1	0/1	1/1		100101	1/1	0/1	1/1
12	001011	1/0	1/1	1/1	28	011011	1/0	1/1	1/1
	110100	1/1	1/0	1/1		100100	1/1	1/0	1/1
13	001100	1/0	0/1	1/0	29	011100	1/0	0/1	1/0
	110011	1/1	1/1	1/1		100011	1/1	1/1	1/1
14	001101	1/0	1/0	0/1	30	011101	1/0	1/0	0/1
	110010	1/1	1/1	1/1		100010	1/1	1/1	1/1
15	001110	1/0	1/1	1/1	31	011110	1/0	1/1	1/1
	110001	1/1	1/0	1/1		100001	1/1	1/0	1/1
16	001111	1/0	1/1	1/1	32	011111	1/0	1/1	1/1
	110000	1/1	0/1	1/1		100000	1/1	0/1	1/1

. Each SSC1…SSC5 tester converts a serial two-rail signal into a parallel signal at outputs z0 and z1. If a two-rail signal is disrupted when a pair of combinations is applied, then a non-two-rail signal is also generated at outputs z0 and z1. This indicates an error in the calculations. The first ten signals demonstrate the operation of self-dual signal checkers on each of the diagrams. The signals from the outputs SSC1…SSC5 are compressed using elementary two-rail signal compression modules into a single signal. This is demonstrated in the diagrams in lines TRC7_f0 and TRC7_f1 (point B in Figure 1). The conclusion can be made based on the violation of a two-rail signal regarding the presence of an error in the calculations. We have highlighted the violation of a two-rail signal using black dots in order to facilitate the analysis of the diagrams. In parallel, the calculations are monitored by whether the codewords belong to the Hsiao code. The signals are shown in lines TRC8_f0 and TRC8_f1 (point A in Figure 1) from the control outputs of this monitoring subcircuit. Here, too, moments of two-rail signal violation are highlighted with black dots. Moments do not always coincide with fixing errors in calculations by different subcircuits. This is what makes it possible to improve the observability of errors at the control outputs of the CED circuit. Lines TRC9_f0_z0 and TRC9_f1_z1 represent the signals at the control outputs of the entire CED circuit (point C in Figure 1). There are a total of 32 pairs of combinations on which the circuit can operate. If the calculations were based on only one diagnostic sign, for example as assumed in [26,27,28,29,30], the error rate would be much lower.

In addition to Figure 3, Table 2 and Table 3 list all pairs of combinations supplied to the device inputs. The background color indicates which input combinations are used for testing the corresponding faults. These combinations are tested (the output signals on the corresponding check device are the same on such input combinations). The corresponding combinations are also shown in Figure 3 and Figure 4 as dots on the corresponding clock cycle. When the circuit is operating with a stuck-at-0 fault at the output of the designated cascade in Figure 2, 28 input combinations are checked using one of two diagnostic signs (43.75% of the total number of combinations). Checking by two signs allows for increasing the number of test combinations to 35 (54.69% of the total number of combinations). When the circuit is operating with a stuck-at-1 fault at the output of the cascade designated in Figure 2, 28 input combinations are also checked using each of the signs (43.75% of the total number of combinations). Checking by two signs increases this number to 49 (76.56% of the total number of combinations). For the stuck-at-0 fault, an improvement of about 11% was achieved; for the stuck-at-1 fault, an improvement of about 33% was achieved.

The calculations testing with two diagnostic signs makes it possible in all cases to increase the controllability of circuits. This allows for a higher probability of detecting emerging faults when using a subset of the full input combinations set. This indicates the potential applicability of the described approach for calculations testing in devices with inputs that rarely change, which is common for many safety-critical systems [33,34].

Figure 4 shows a histogram that allows us to judge the increase in the controllability of the circuit due to the organization of calculations testing by two diagnostic signs and not by one of them. On average, 40.104% of the input combinations are also tested when testing by one sign of all faults. This number increase to 60.156% when the calculations are testing by two signs. Thus, the number of test combinations on average increased by 1.5 times. The columns (highlighted in blue) correspond to the operation of the CED circuit only according to whether the generated codewords belong to the Hsiao codes. Thus, the observability of errors at the outputs is significantly increased in contrast to traditional structures of computing control organization [26,27,28,29,30] due to the monitoring of several diagnostic signs at once. This demonstrates the effectiveness of the technical solution proposed by the authors of this paper. At the same time, it should be noted that we do not use any modifications of the Hsiao code but apply its natural properties. These properties consist of the fact that under certain conditions, the check symbols can be described by self-dual Boolean functions.

5. Discussion

Hsiao codes are commonly employed in the construction of structures with error detection and correction [24,25,26,27,28]. Nevertheless, all applications of these codes are limited to the properties of the code itself for detecting and correcting errors in data symbols. The authors of this paper point out that Hsiao codes possess another diagnostic property that can be effectively used in the design of CED circuits. The research conducted by the authors has demonstrated that Hsiao codes can be effective for use in the synthesis of CED circuits for self-dual digital devices. It has also been found that calculations testing is highly effective when based on two diagnostic signs. The check functions belong to the class of self-dual Boolean functions, and the code vector belongs to the Hsiao code that is generated in a CED circuit. This is supported by numerous experiments, one example of which is provided in Section 4 of the paper. Figure 4 shows that the calculations testing increases the detection abilities of the CED circuit by simultaneously using two diagnostic signs. For various circuits, the improvement is between 20% and 25%. In addition, control indicators have been significantly increased in terms of fault detection. This indicates possible prospects for applying the developed method of circuit synthesis based on two diagnostic signs in the design of highly reliable devices for critical systems.

It is important to note the following feature of Hsiao codes: they have a lower coding rate compared to classic Hamming codes, which affects the hardware cost of designing a CED circuit. Figure 1 illustrates the structure of a CED circuit, where a group of seven diagnostic object outputs is controlled by compressing signals into five using a Hsiao code encoder. Structures for larger numbers of discrete device outputs can be proposed, and the structural redundancy can be reduced of the self-testing device. There will be a significant difference between the values of m and k in this case. The author of [14] reports that the self-dual signal compression circuit can be used along with a single self-dual signal checker instead of a group of self-dual signal checker in the structure illustrated in Figure 1. This would simplify the structure of the CED circuit.

Note also that the structure depicted in Figure 1 is a special type of structure and is designed for a group of seven outputs from the diagnostic object. Using other Hsiao codes would allow for the creation of similar structures with more outputs and different lengths of data vectors.

Table 4. Hsiao codes with self-dual encoders at k = 5.

Indicator	m							Total with k = 5
	5	6	7	8	9	10	11
$N_{k,m}^{SD}$	27	0	24	0	0	0	1	52
$N_{k,m}$	462	462	330	165	55	11	1	1486
ω, %	5.844	0	7.273	0	0	0	100	3.499

present the ratio of the number of ways to construct Hsiao codes for the case k = 5, which has self-dual encoder properties. Researchers have shown that such Hsiao codes can only be generated for cases m = 5, 7 and 11. Row $N_{k,m}^{SD}$ shows the number of Hsiao codes with self-dual encoders. Row $N_{k,m}$ shows the total number of Hsiao codes. Row ω calculates the relative indicator of the number of Hsiao codes with self-dual encoders compared to the total number of Hsiao codes: $\omega ={\displaystyle \raisebox{1ex}{$N_{k,m}^{SD}$}\!\left/ \!\raisebox{-1ex}{$N_{k,m}$}\right.}\cdot 100\%$. The last column of the table shows the total values of ${\displaystyle \sum _{m=5}^{11}{N}_{k,m}^{SD}},$${\displaystyle \sum _{m=5}^{11}{N}_{k,m}}$ and $\overline{\omega }={\displaystyle \raisebox{1ex}{${\displaystyle \sum _{m=5}^{11}{N}_{k,m}^{SD}}$}\!\left/ \!\raisebox{-1ex}{${\displaystyle \sum _{m=5}^{11}{N}_{k,m}}$}\right.}\cdot 100\%$. There are only 52 ways to construct Hsiao codes using self-dual encoders from a total of 1486 Hsiao codes with k = 5. This number of ways to construct Hsiao codes using self-dual encoders is relatively small compared to the total number. Nevertheless, this provides 52 ways of synthesizing a CED circuit based on two diagnostic signs. Hsiao codes with large k > 5 values can also be considered. Furthermore, as the k value increases, there are increasing numbers of Hsiao codes available. Among these, codes can be implemented with self-dual functions describing check symbols.

It is also worth noting the error-detecting properties of the Hsiao codes. These codes are able to identify any errors that occur in codewords bits with multiplicities d < 4. Hsiao codes have a much higher effectiveness at detecting errors in the area with small multiplicities compared to classical Hamming codes. This allows for the synthesis of CED circuits with high efficiency indicators of errors detection efficiency at the outputs of diagnostic objects. However, the Hsiao codes are inferior to the Hamming codes in terms of the code rate. They always have one more check symbol than the classic Hamming codes. However, this may be seen as a consequence of the high level of error detection efficiency in the CED circuit. At the same time, there is a slight increase in the additional cost associated with synthesis and the structural redundancy in the CED circuit (a larger number of self-dual checkers, two-rail checker modules, as well as a slightly more complex control logic block are required).

Additionally, it is important to discuss the disadvantages of employing the method described in the paper. This method involves pulsed operation, which necessitates a specific representation of signals. This task can be solved by simply installing a square-wave generator and configuring the circuit operation. The combinations are supplied in pairs with every first clock cycle representing data and every second clock cycle performing a check. This reduces the performance of the devices with CED circuits by half compared to the traditional way of organizing CED circuits. Additionally, we would like to stress a point that in order to organize the CED circuit according to the proposed method, it will be necessary to transform the structure of a non-dual diagnosis object into a self-dual structure. This, of course, is a relatively simple process, but it can lead to an increased device redundancy [14]. The Boolean correction of signals can also be applied to check non-dual structures of diagnostic objects [16]. Another disadvantage of the proposed method is that it may introduce complexity. These is commensurate with or exceeds that of the widely used duplication approach. And it may prove to be ineffective in terms of structural redundancy when used for modeling and evaluating efficiency indicators of CED circuits.

In future research, the authors intend to analyze other features of the Hsiao codes. These features can be considered when designing highly reliable devices. Additionally, we also intend to develop a methodology for the synthesis of real control devices for the implementation of critical technological processes using parallel CED circuits based on two diagnostic signs.

6. Conclusions

The Hsiao codes possess the ability to detect any one-, two- and three- fold errors in the bits of codewords. These codes are characterized by the property of self-dual functions (which describe check symbols) under certain conditions. Therefore, the Hsiao codes can be used in the design of CEDs with calculations testing by two diagnostic signs. This increases the structural redundancy indicators of the CED, but the number of test combinations increases significantly. These combinations are both operating for the device.

The structural redundancy does not significantly increase. A self-duality check device for Boolean functions is included in the CED in addition to the Hsiao code checker. This device has the simplest typical implementation. The authors of [15,16] describe the principle of operation and structure of the self-duality checker. The complexity indicators for the technical implementation of the standard part of the CED increase linearly as the number of outputs from the diagnostic object (source device) increases. Controllability indicators also increase with various faults in different ways and can reach an increase of 1.5–1.8 times when faults are observed at the device’s outputs.

The Hsiao codes are of interest with self-dual check functions in the development of self-checking digital computing devices and systems, and, importantly, critical application systems, for which the input data rarely change.