Compact Model for L-Shaped Tunnel Field-Effect Transistor Including the 2D Region

Abstract

The L-shaped tunneling field-effect transistor (LTFET) is the only line-tunneling type of TFET to be experimentally demonstrated. To date, there is no literature available on the compact model of LTFET. In this paper, a compact model of LTFET is presented. LTFET has both one-dimensional (1D) and 2D band-to-band tunneling (BTBT) components. The 2D BTBT part dominates in the subthreshold region, whereas the 1D BTBT dominates at higher gate-source biases. The model consists of 1D and 2D BTBT models. The 2D BTBT model is based on the assumption that the electric field originating from the gate and terminating at the source edge is perfectly circular. Tunneling path length is obtained by calculating the distance along an electric field arc that runs from gate to source. The 1D BTBT model is based on a simultaneous solution of the 1D Poisson equation in source and channel regions. Expressions for electric field and potential obtained from integrating the Poisson equation in source and channel regions are solved simultaneously to find the surface potential. Once the surface potential is known, all the other unknown variables, including junction potential and source depletion length, can be calculated. Using the potential profile, tunneling lengths were found for both the source-to-channel BTBT regime, and channel-to-channel BTBT regime. The tunneling lengths were used to calculate the BTBT tunneling rate, and finally, the drain-source current as a function of gate-source, and drain-source bias was calculated. The model results were compared against technology computer-aided design (TCAD) simulation results and were found to be in reasonable agreement for a compact model.

1. Introduction

With the power requirements of complementary metal–oxide–semiconductor (CMOS) technology surging beyond unreasonable levels to meet the high computing demands of today’s world, there has been a desperate push for devices that can perform better for less power [1]. The tunnel field-effect transistor (TFET) is one such device among the potential candidate devices [2]. TFET works on the principle of band-to-band-tunneling (BTBT) and achieves a steeper subthreshold slope (SS) than a metal–oxide–semiconductor field-effect transistor (MOSFET) of equivalent dimensions and electrical parameters.

However, the on-current (I_ON) of TFET is lower than that of MOSFET of equivalent dimensions/electrical parameters. To overcome this problem, different types of TFET architectures have been suggested, including the line-tunneling type [3] TFETs. The structure of line tunneling type TFETs has a gate-source overlap. This overlap increases the BTBT area and consequently increases the I_ON. The L-shaped TFET (LTFET) [4] is an example of a line-tunneling TFET that features the channel region grown vertically in the form of an L-shape. The LTFET offers the same benefits as a conventional line-tunneling type TFET, but with a much lower device footprint. More significantly, LTFET is the only example of a line-tunneling TFET that has been experimentally realized.

Compact modeling is an important part of the circuit design process. While there are compact models available for the conventional TFET [5,6,7], the literature is almost completely lacking in compact models for the line-tunneling type TFETs. Vandenberghe et al. [3] developed a compact model for conventional line-tunneling TFET. Najam et al. [8] developed a compact model for LTFET. However, the line-tunneling TFET considered in [3] features a significant difference from the LTFET: The gate directly overlaps with the source region, as shown in Figure 1 in [3], whereas in the LTFET, there is a channel region present between the source and the gate. Direct overlapping of gate/source without any channel layer present in between completely changes the electrostatics of the device and makes the model presented in [3] inapplicable to LTFET. In [8], only the one-dimensional (1D) model is presented. In LTFET, both 1D and 2D BTBT components are present.

This paper presents a complete model of the LTFET, including both the 2D and 1D BTBT, which is presented in Section 2. The model presented is continuous from the subthreshold region to strong inversion. The model is tested for LTFETs with varying geometries, and the results are presented in Section 3. A conclusion is presented in Section 4.

2. Model Development

Figure 1 shows the schematic of the LTFET. The channel region shown in blue color is found in an L-shape and is sandwiched between the gate and the source. The part of the channel region found in between the source and gate regions is termed as C_overlap with height (H_overlap) = 40 nm and length (T_j) = 4 nm. The source and drain are p⁺ (N_a = 10²⁰ cm⁻³) and n⁺ (N_drain = 10²⁰ cm⁻³) doped, respectively, while the channel is lightly n⁻ doped (N_d = 10¹⁵ cm⁻³). The source region height (H_s) and length (L_s) are 40 and 50 nm, respectively. The bottom part of the channel, which is not in between the source and gate regions, is termed as C_nonoverlap and has a height (H_nonoverlap) = 20 nm, and length (L_nonoverlap) = 50 nm. An HfO₂ dielectric of thickness (t_ox) = 2 nm for gate oxide was considered.

Dynamic nonlocal BTBT model [9], fermi statistics, and constant mobility models were considered in the technology computer-aided design (TCAD) simulation.

As shown in Figure 1, the source has a sharp corner marked by an X in Figure 1. The electric field from the gate converges at and around this sharp source corner, increasing the potential around this point. The right axis in Figure 2a shows surface potential (φ_s) at V_gs = 0.15 V and V_ds = 0.5 V. As shown in Figure 2a, φ_s sharply rises in C_nonoverlap because of convergence of the electric field, whereas φ_s is less in C_overlap where this convergence does not take place. This convergence affects the BTBT threshold voltage of C_overlap and C_nonoverlap. C_nonoverlap is found to have a lower BTBT threshold voltage because of this increased φ_s. Meanwhile, C_overlap has a significantly higher BTBT threshold voltage because of the lower potential [10]. This can be seen in Figure 2b, which shows integrated BTBT tunneling rates [10] (G_tuns) in x and y directions in C_overlap and C_nonoverlap, respectively; that is, ${{\displaystyle \int }}_{L_s+T_j}^0{{\displaystyle \int }}_0^{H_{\mathrm{overlap}}}{G}_{\mathrm{tun}}dxdy$ in C_overlap (black triangles) and ${{\displaystyle \int }}_{L_{\mathrm{nonoverlap}}}^0{{\displaystyle \int }}_{H_{\mathrm{overlap}}}^{H_{\mathrm{nonoverlap}}}{G}_{\mathrm{tun}}dxdy$ in C_nonoverlap (red circles) in the left axis. Figure 2b clearly shows that C_nonoverlap turns on earlier than C_overlap. The right axis in Figure 2b shows the drain-source current (I_ds) as a function of gate–source bias (V_gs) of LTFET. It is shown that in the subthreshold part of the I_ds–V_gs characteristics, only the C_nonoverlap is active. C_overlap turns on at V_gs = 0.15 V. When C_overlap turns on, its G_tun is significantly higher because of 1D BTBT paths. As a result, it dominates the 2D G_tun in C_nonoverlap, as can be seen in Figure 2b. Based on this analysis, I_ds–V_gs characteristics of LTFET were modeled in two parts, first the 2D model in C_nonoverlap for the subthreshold region and then the 1D model in C_overlap.

2.1. 2D Model: C_nonoverlap Model

The 2D model is based on the work in [3]. The following assumptions are used in this model: (1) Electric fields are assumed to be completely circular and terminate from gate to source. This helps in obtaining a convenient expression for the tunneling length (W_t); (2) Gate dielectric is treated as the same material as the channel with an equivalent dielectric thickness t’_ox given by t’_ox = t_oxε_si/ε_ox, where t_ox, ε_si, and ε_ox are the physical dielectric thickness, silicon dielectric permittivity, and oxide dielectric permittivity, respectively. This is necessary to ensure a continuous and perfectly circular electric field from the gate-to-channel/gate dielectric interface, and finally terminate at the source. Without this assumption, the electric field will be discontinuous, that is, not perfectly circular in its path from gate to source. In this work, W_t is conveniently calculated as the length along the perfectly circular electric field arc, from gate to source, as will be shown below. If a discontinuity arises in the circularity of the electric field arc, such convenient calculation of W_t will not be possible; (3) The source is assumed to be completely depleted, and depletion length is ignored. The source is heavily doped. Depletion length is inversely proportional to doping concentration [3]. This makes the source depletion length negligible. Including the source depletion length would add complexity to the model without significantly increasing the accuracy of the model; (4) The source is assumed to be touching the gate.

Table 1. List of all the symbols specific to the two-dimensional (2D) model.

Symbol	Description	Value/Unit
φsource	Potential at source edge	V
φg	Potential at gate	V
tox	Physical oxide thickness	2 × 10−7 cm
t’ox	Equivalent semiconductor thickness	cm
εsi, εox	Silicon, oxide permittivity	11.9, 25 F/cm
θ0	Angle when the BTBT condition is satisfied	Radian
r0	Radius of an electric field arc	cm/radian

mentions most of the symbols used in the equations below.

With these assumptions, the boundary conditions at source and gate can be given by

$$\phi \left(x,0\right)={\phi }_{\mathrm{source}} \mathrm{and} \phi \left(0,y\right)={\phi }_{\mathrm{g}}.$$

(1)

where φ_source is assumed to be 0 V and φ_g is the gate–source bias minus the flat band voltage (V_fb), that is, φ_g = V_gs − V_fb. The solution of potential in polar co-ordinates is given by

$$\phi \left(x,y\right)=\frac{2\theta {\phi }_{\mathrm{g}}}{\pi }, 0\le \theta \le \frac{\pi }{2}.$$

(2)

The above boundary condition along with θ₀ is shown in Figure 3a. Thanks to assumptions 1 and 2, W_t is calculated as the length along a perfectly circular electric field line as follows:

$$W_{\mathrm{t}}=r_0{\theta }_0$$

(3)

where θ₀ is given by θ₀ = πE_g/(2qφ_g), (where E_g is the bandgap, and q is the charge on an electron) and is the angle when the potential difference between the source edge and some point along the electric field line becomes equal to E_g/q. θ₀ is obtained by substituting the BTBT condition, that is, φ = E_g/q in (2), and inverting it. Since θ₀ is bias-dependent, θ₀ decreases, and W_t decreases as V_gs bias increases. This is illustrated in Figure 3b. r₀ is the radius of the electric field arc and is given by r₀ = t’_ox/cos (θ₀). Drain current expression in C_nonoverlap (I_{ds_Cnonoverlap}) is given by the following equation for D = 2.5 [3]:

$$I_{\mathrm{ds}\_\mathrm{Cnonoverlap}}=\frac{qW{A}_{\mathrm{k}}{E}_{\mathrm{g}}{t}_{\mathrm{ox}}^{\prime }}{q^{4.5}{B}_{\mathrm{k}}^2}.\frac{1}{{\theta }_0^{4.5}{r}_0^{3.5}}.\exp \left(-q{B}_{\mathrm{k}}{r}_0{\theta }_0\sqrt{E_{\mathrm{g}}}\right),$$

(4)

where W (=10⁻⁴ cm) is the device width, and A_k = 1 × 10¹⁵ eV^0.5·cm^−1/2·s⁻¹·V^−2.5 and B_k = 1.5 × 10⁷ V·cm⁻¹·eV^−1.5 are the parameters used in the dynamic nonlocal BTBT model. There is one notable difference between this work and [3] which is that, as C_overlap turns on, I_{ds_Cnonoverlap} is assumed to saturate. This is in line with the results presented in Figure 2b. Once C_overlap turns on, it dominates, and C_nonoverlap does not have any significant contribution beyond that point. Without this assumption, the model overestimates I_{ds_Cnonoverlap} in the high V_gs region.

2.2. 1D Model: C_overlap Model

Figure 4a shows a magnified C_overlap and source regions. The channel region considered in the 1D model comprises the C_overlap region. Figure 4a mentions the important parameters used in the 1D model, including the location of φ_s and junction potential (φ_j). φ_j is the potential at the junction of the source and channel region in Figure 4a. The device origin is at the top of the channel/gate dielectric interface, and x_channel and x_source correspond to the x-coordinate in channel and source regions, respectively. The dimension for the 1D model is along the x-direction, as shown by the cutline shown in Figure 4b. The cutline begins at the channel/gate dielectric interface and ends in the source region. Figure 5d–f and Figure 6a,b are along the black cutline shown in Figure 4b.

The 1D model is based on the solution of the 1D Poisson equation. Integrating the 1D Poisson equation once, in source and channel regions, and neglecting electron and hole carrier concentrations yields the electric field in the respective regions, which are given by

$$\frac{\partial {\phi }_{\mathrm{source}}}{\partial x_{\mathrm{source}}}=\frac{q{N}_{\mathrm{a}}}{{\epsilon }_{\mathrm{si}}}{x}_{\mathrm{source}}+\frac{q{N}_{\mathrm{a}}}{{\epsilon }_{\mathrm{si}}}\left(L_{\mathrm{dep}}\right),$$

(5)

$$\frac{\partial {\phi }_{\mathrm{channel}}}{\partial x_{\mathrm{channel}}}=\frac{q{N}_{\mathrm{d}}}{{\epsilon }_{\mathrm{si}}}{x}_{\mathrm{channel}}+\frac{{\epsilon }_{\mathrm{ox}}}{{\epsilon }_{\mathrm{si}}{t}_{\mathrm{ox}}}\left(V_{\mathrm{gs}}-V_{\mathrm{fb}}-{\phi }_{\mathrm{s}}\right),$$

(6)

where L_dep is the depletion length of the source region. Integrating (5) and (6) again yields potential in source and channel regions, which is given by

$${\phi }_{\mathrm{source}}\left(x_{\mathrm{source}}\right)=\frac{q{N}_{\mathrm{a}}}{2{\epsilon }_{\mathrm{si}}}{\left(x_{\mathrm{source}}+L_{\mathrm{dep}}\right)}^2+{\phi }_{\mathrm{dep}}$$

(7)

$${\phi }_{\mathrm{channel}}\left(x_{\mathrm{channel}}\right)=\frac{q{N}_{\mathrm{d}}}{2{\epsilon }_{\mathrm{si}}}{x}_{\mathrm{channel}}^2+\frac{{\epsilon }_{\mathrm{ox}}}{{\epsilon }_{\mathrm{si}}{t}_{\mathrm{ox}}}\left(V_{\mathrm{gs}}-V_{\mathrm{fb}}-{\phi }_{\mathrm{s}}\right)x_{\mathrm{channel}}+{\phi }_{\mathrm{s}}$$

(8)

$$\begin{array}{l}{\phi }_{\mathrm{s}}=V_{\mathrm{gs}}-V_{\mathrm{fb}}+\frac{q\left(N_{\mathrm{a}}+N_{\mathrm{d}}\right)}{C_{\mathrm{ox}}}{T}_{\mathrm{j}}+\frac{q{\epsilon }_{\mathrm{si}}{N}_{\mathrm{a}}}{C_{\mathrm{ox}}^2}\\ -\gamma \sqrt{V_{\mathrm{gs}}-V_{\mathrm{fb}}+\frac{q\left(N_{\mathrm{a}}+N_{\mathrm{d}}\right)}{2{\epsilon }_{\mathrm{si}}}{T}_{\mathrm{j}}^2+\frac{q\left(N_{\mathrm{a}}+N_{\mathrm{d}}\right)}{C_{\mathrm{ox}}}{T}_{\mathrm{j}}+\frac{q{\epsilon }_{\mathrm{si}}{N}_{\mathrm{a}}}{2C_{\mathrm{ox}}^2}-{\phi }_{\mathrm{dep}}}\end{array}$$

(9)

where C_ox is the gate oxide capacitance, φ_dep is the source depletion potential, and γ = (2ε_siqN_a)^1/2/C_ox. With the potential profile known, W_t can be calculated. Because (9) is derived from the depletion approximation, the smoothing function from [11,12,13] was used to model strong inversion of the electron.

There are two different 1D BTBT mechanisms present in LTFET [8]. One is the source-to-channel BTBT, which starts at low bias, and the other is the channel-to-channel BTBT, which takes place at high V_gs bias. The first source to channel the 1D BTBT model is discussed.

The potential profile within the channel is assumed to be linear, as seen in Figure 5d–f, which is given by

$${\phi }_{\mathrm{channel}}\left(x_{\mathrm{channel}}\right)=m{x}_{\mathrm{channel}}+{\phi }_{\mathrm{s}}$$

(10)

where m is the slope of the linear potential profile in the channel, m = (φ_s − φ_j)/T_j. φ_j can be found from (8) by using x_channel = T_j. Figure 5a–c shows φ_s as a function of V_gs of LTFET with T_j = 4, 5, and 6 nm at different V_ds biases, respectively. Figure 5d–f shows the potential profile along the cutline shown in Figure 4b for LTFET with T_j = 4, 5, and 6 nm at different V_gs and V_ds = 0.25 V, respectively. Symbols and lines denote the simulation results of TCAD and the proposed potential model, respectively. Reasonable agreement is observed within a maximum error of 10% between the model and TCAD simulations.

Figure 6a shows a band diagram at V_gs = 0.3 V and V_ds = 0.5 V, along the cutline of Figure 4b. Black and green symbols represent conduction band minimum energy (E_c) and valence band maximum energy (E_v), respectively. Red circles represent potential. Arrows denote W_ts. The longest W_t (W_{t_longest}) originates where φ_source = φ_dep, and the shortest W_t (W_{t_shortest}) originates from where the potential is the highest, that is, φ_s. The starting and ending points for W_{t_shortest} are x_{s_shortest} and x_{e_shortest}, respectively, and the starting and ending points for W_{t_longest} are x_{s_longest} and x_{e_longest}, respectively, which are all indicated by arrows in Figure 6a. x_{s_longest} naturally starts from L_dep, that is, x_{s_longest} = −abs(L_dep + T_j), and the ending point for the W_{t_shortest} is the surface, that is, x_{e_shortest} = 0. x_{e_longest} is the point where the BTBT condition for W_{t_longest}, that is, φ(x_{e_longest}) = φ_dep + E_g/q, is satisfied. By substituting this BTBT condition in (10) and inverting it, x_{e_longest} is given by x_{e_longest} = (φ_dep + E_g/q − φ_s)T_j/(φ_s − φ_j). x_{s_shortest} is the point where the BTBT condition for W_{t_shortest}, that is, φ(x_{s_shortest}) = φ_s − E_g/q, is satisfied. By substituting this BTBT condition in (7) and inverting it, x_{s_shortest} is given by

$$x_{\mathrm{s}\_\mathrm{shortest}}=\sqrt{{\phi }_{\mathrm{dep}}+{\phi }_{\mathrm{s}}-\frac{E_{\mathrm{g}}}{q}\left(\frac{2{\epsilon }_{\mathrm{si}}}{q{N}_{\mathrm{a}}}\right)}-abs\left(L_{\mathrm{dep}}+T_{\mathrm{j}}\right)$$

(11)

Finally, W_{t_shortest} and W_{t_longest} are given by

$$W_{\mathrm{t}\_\mathrm{shortest}}=x_{\mathrm{e}\_\mathrm{shortest}}-x_{\mathrm{s}\_\mathrm{shortest}}$$

(12a)

$$W_{\mathrm{t}\_\mathrm{longest}}=x_{\mathrm{e}\_\mathrm{longest}}-x_{\mathrm{s}\_\mathrm{longest}}$$

(12b)

G_tun is given by Kane’s model [14]

$$G_{\mathrm{tun}}=\frac{A_{\mathrm{k}}}{\sqrt{E_{\mathrm{g}}}}{\left(\frac{E_{\mathrm{g}}}{{qW}_{\mathrm{t}}}\right)}^{2.5}\exp \left(-{qB}_{\mathrm{k}}{W}_{\mathrm{t}}\sqrt{E_{\mathrm{g}}}\right).$$

(13)

I_ds for source-to-channel BTBT (I_{ds_s_c}) is given by

$$I_{\mathrm{ds}\_\mathrm{s}\_\mathrm{c}}=qW{{\displaystyle \int }}_0^{H_{\mathrm{s}}}{{\displaystyle \int }}_0^{x_{\mathrm{j}}}{G}_{\mathrm{tun}}\left(x\right)\mathit{dydx}={\mathit{qWH}}_{\mathrm{s}}{x}_{\mathrm{j}}\left(\frac{G_{\mathrm{tun}\_\mathrm{shortest}}+G_{\mathrm{tun}\_\mathrm{longest}}}{2}\right)$$

(14)

where x_j is the integration limit indicated in Figure 6a, and is equal to $x_{\mathrm{j}}=x_{\mathrm{e}\_\mathrm{shortest}}-x_{\mathrm{e}\_\mathrm{longest}}$. In (14), a constant average G_tun, that is, $\frac{G_{\mathrm{tun}\_\mathrm{shortest}}+G_{\mathrm{tun}\_\mathrm{longest}}}{2}$, is used. Here, G_{tun_shortest} and G_{tun_longest} are found by using W_t = W_{t_shortest} and W_{t_longest} in (13), respectively. G_tun is a function of W_t, as can be inferred from (13). The integral in (14), however, is with respect to x. Finding a closed-form expression for I_{ds_s_c} then necessitates expressing W_t as a function of x. However, because W_t cannot be expressed as a function of x, W_t can only be found for fixed BTBT boundary conditions, as done in (12a, b). In this scenario, dW_t/dx cannot be evaluated. As a result, there is no closed-form expression available for G_tun integrated as a function of x. Therefore, the simplification of using average G_tun was necessary and, as it will be shown in Section 3, the average G_tun approximates the integral of G_tun with respect to x reasonably well. When the bias is high enough, the potential increases so much that BTBT becomes possible from even inside the channel. This is illustrated by the band diagram shown in Figure 6b along the cutline of Figure 4b. Here, E_v/E_c becomes aligned within the channel, as illustrated by the arrows, in addition to the source/channel E_v/E_c alignment. Here, W_{t_longest} starts from x_{s_longest} = T_j and ends at x_{e_longest}, where the BTBT condition, φ(x_{e_longest}) = φ_j + E_g/q, is satisfied. Similarly, W_{t_shortest} starts at x_{s_shortest}, where the BTBT condition, φ(x_{s_shortest}) = φ_s − E_g/q, is satisfied and ends at x_{e_shortest} = 0. By substituting these boundary conditions in (10) and inverting it, x_{e_longest} and x_{s_shortest} can be calculated as x_{e_longest} = (φ_j + E_g/q − φ_s)T_j/(φ_s − φ_j) and x_{s_shortest} = −E_gT_j/(q(φ_s − φ_j)). As can be seen in Figure 6b, W_t is almost constant within the channel. Therefore, in the channel-to-channel regime, G_{tun_shortest} ≈ G_tun(W_{t_longest}) ≈ G_tun(W_{t_shortest}). This means that G_tun(x) can be taken out of the integral in the channel-to-channel drain current (I_{ds_c_c}) expression, which is given by

$$I_{\mathrm{ds}\_\mathrm{c}\_\mathrm{c}}=qW{H}_{\mathrm{s}}{x}_{\mathrm{j}}{G}_{\mathrm{tun}}\approx qW{H}_{\mathrm{s}}{x}_{\mathrm{e}\_\mathrm{longest}}{G}_{\mathrm{tun}\_\mathrm{shortest}}$$

(15)

The total I_ds is given by

$$I_{\mathrm{ds}}=I_{\mathrm{ds}\_\mathrm{Cnonoverlap}}+I_{\mathrm{ds}\_\mathrm{s}\_\mathrm{c}}+I_{\mathrm{ds}\_\mathrm{c}\_\mathrm{c}}$$

(16)

3. Results

Figure 7a–c shows I_ds–V_gs characteristics of LTFET with T_j = 4, 5, and 6 nm, respectively. Symbols and lines denote the simulation results of TCAD and the proposed model, respectively. Blue, red, and black colors denote V_ds = 0.25, 0.5, and 0.7 V, respectively. A kink is observed in Figure 7a–c, at the transition point where the 1D model takes over the 2D model. This is observed because the 1D and 2D models are independent of each other and don’t produce the same and continuous G_tun at the transition point.

There is no noticeable change observed in the subthreshold behavior as T_j is changed from 4 nm to 6 nm. However, the on-current (I_ON) is observed to decrease as T_j is increased. I_ON at V_gs = 0.8 V and V_ds = 0.7 V is 0.48, 0.22, and 0.09 µA for T_j = 4, 5, and 6 nm, respectively. This is because W_t and G_tun are inversely proportional, as can be observed from (13); the longer W_t in T_j = 5 and 6 nm results in lower G_tun, and consequently, lower I_ds. This effect is captured by the model reasonably well. This suggests that shorter T_j is more desirable for getting higher I_ON.

Figure 7d–f shows I_ds–V_ds characteristics of the LTFET for T_j = 4, 5, and 6 nm, respectively. Symbols denote TCAD simulation results, and lines denote model results. Black, red, blue, and magenta denote V_gs = 0.2, 0.4, 0.6, and 0.8 V, respectively. As shown in Figure 7d–f, the saturation characteristics of the LTFET are predicted reasonably well by the model.

Figure 8 shows I_ds–V_gs characteristics of LTFET with T_j = 4 nm and H_overlap = H_s varied at V_ds = 0.5 V. Symbols denote TCAD simulation results and lines denote model results. Blue, red, and black represent H_overlap = 40, 50, and 60 nm, respectively. It is shown in Figure 8 that, as H_overlap = H_s is increased, the I_ds increases. This is because, with an increase in H_overlap, the BTBT area increases. This results in an increase in I_ds. Once again, the model captures this effect reasonably well.

Compared to the planar TFET, the LTFET offers better SS and I_ON performance. This can be gauged from the fact that while in planar TFET, the dominant BTBT generation area comprises the surface source/channel depletion regions. In the LTFET, however, because of the gate–source overlap, this area is significantly amplified by the height of the source and C_overlap regions. Furthermore, because of this overlap, the electrostatic coupling between gate and source is stronger in LTFET. In other words, the electric field is stronger in the LTFET as compared to the planar TFET, which also results in higher I_ON and lower inverse subthreshold slope in LTFET, as was demonstrated even in the case of the experimental LTFET and planar TFET in [4].

For a compact model, the simulation results of the model agree reasonably well with those of TCAD within a maximum error of 10%. However, it is not entirely accurate. The inaccuracy results from the simplified integral expression in (14). Numerical integration of G_tun with respect to x will significantly improve the result. Another source of error is the use of the smoothing function to model electron inversion. The smoothing function only approximates surface potential saturation due to electron inversion, and is thus not very accurate at high bias. Considering the electron concentration term in the Poisson equation and doing a self-consistent solution for potential and electron concentration will also improve the model accuracy significantly. However, both numerical integration and self-consistent potential electron concentration solution will significantly add to the computational complexity of the model. This will make the model unsuitable for SPICE applications.

It should also be mentioned that the model was bench-marked only against TCAD data and not experimental data. This is because the experimental LTFET demonstrated significant trap-assisted tunneling (TAT), and Shockley–Read–Hall (SRH) generation–recombination current- and ambipolar current-induced degradation of the I_ds–V_gs characteristics [4]. In particular, TAT in line TFETs is a significant topic and requires its own modeling framework [9]. This work with the equations for surface and junction potentials lays the foundation for the TAT model. However, due to space constraints, TAT, SRH, ambipolar, quantum confinement [15], and breakdown models [16] could not be included in this manuscript.

4. Conclusions

A compact model for LTFET was presented. The model calculates both the 1D BTBT and 2D BTBT present in LTFET. The 1D model is based on the simultaneous solution of 1D Poisson equations in the channel and source region. The Poisson equation is integrated twice in both regions, and the expression for electric field and potential are equated at the source–channel junction point to yield expression for surface potential. To model electron inversion, a simple smoothing function was used. After obtaining the potential profile, starting and ending points of tunneling paths were determined using BTBT boundary conditions. The shortest tunneling path was considered in the drain current expression for source-to-channel BTBT. This was done to obtain a simplified expression for the source-to-channel drain current. Tunneling path lengths were similarly determined for the channel-to-channel BTBT regime. The model was compared against I_ds–V_gs/V_ds results obtained from the simulator for different V_ds/V_gs biases, and for different channel region thicknesses, and heights. The results of the compact model are in reasonable agreement with the simulator results.