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Open AccessFeature PaperArticle

Strained Silicon Single Nanowire Gate-All-Around TFETs with Optimized Tunneling Junctions

1
Peter-Grünberg-Institute (PGI 9), JARA-Fundamentals for Future Technology, Forschungszentrum Jülich, 52428 Jülich, Germany
2
HNF, Forschungszentrum Jülich, 52428 Jülich, Germany
*
Authors to whom correspondence should be addressed.
Appl. Sci. 2018, 8(5), 670; https://doi.org/10.3390/app8050670
Received: 15 March 2018 / Revised: 11 April 2018 / Accepted: 20 April 2018 / Published: 26 April 2018
(This article belongs to the Special Issue Silicon Nanowires and Their Applications)
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Abstract

In this work, we demonstrate a strained Si single nanowire tunnel field effect transistor (TFET) with gate-all-around (GAA) structure yielding Ion-current of 15 μA/μm at the supply voltage of Vdd = 0.5V with linear onset at low drain voltages. The subthreshold swing (SS) at room temperature shows an average of 76 mV/dec over 4 orders of drain current Id from 5 × 10−6 to 5 × 10−2 µA/µm. Optimized devices also show excellent current saturation, an important feature for analog performance. View Full-Text
Keywords: tunnel field effect transistor (TFET); band-to-band tunneling (BTBT); trap-assisted tunneling (TAT); gate-all-around (GAA) nanowires (NWs) tunnel field effect transistor (TFET); band-to-band tunneling (BTBT); trap-assisted tunneling (TAT); gate-all-around (GAA) nanowires (NWs)
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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).
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Narimani, K.; Trellenkamp, S.; Tiedemann, A.; Mantl, S.; Zhao, Q.-T. Strained Silicon Single Nanowire Gate-All-Around TFETs with Optimized Tunneling Junctions. Appl. Sci. 2018, 8, 670.

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