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Appl. Sci. 2018, 8(4), 504;

An FPGA Implementation of a Convolutional Auto-Encoder

Key Laboratory of Electronic Equipment Structure Design, Ministry of Education, Xidian University, Xi’an 710071, China
School of Aerospace Science and Technology, Xidian University, Xi’an 710071, China
Author to whom correspondence should be addressed.
Received: 24 February 2018 / Revised: 16 March 2018 / Accepted: 20 March 2018 / Published: 27 March 2018
(This article belongs to the Section Computer Science and Electrical Engineering)
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In order to simplify the hardware design and reduce the resource requirements, this paper proposes a novel implementation of a convolutional auto-encoder (CAE) in a field programmable gate array (FPGA). Instead of the traditional framework realized in a layer-by-layer way, we designed a new periodic layer-multiplexing framework for CAE. Only one layer is introduced and periodically reused to establish the network, which consumes fewer hardware resources. Moreover, by fixing the number of channels, this framework can be applicable to an image of arbitrary size. Furthermore, to effectively improve the speed of convolution calculation, the parallel convolution method is used based on shift registers. Experimental results show that the proposed CAE framework achieves good performance in image compression. It can be observed that our CAE framework has advantages in resources occupation, operation speed, and power consumption, indicating great potential for application in digital signal processing. View Full-Text
Keywords: convolutional auto-encoder; neural network; image compression; FPGA convolutional auto-encoder; neural network; image compression; FPGA

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Zhao, W.; Jia, Z.; Wei, X.; Wang, H. An FPGA Implementation of a Convolutional Auto-Encoder. Appl. Sci. 2018, 8, 504.

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