Transforming Group Codes in Mealy Finite State Machines with Composite State Codes

Abstract

A new state assignment method focusing on Mealy finite state machines (FSMs) is proposed. The proposed codes are an alternative to composite state codes (CSCs). CSCs are represented as concatenations of group codes and partial state codes. Both group and partial state codes are maximum binary codes. We propose encoding groups using one-hot codes. The main goal of this method is improving the value of the FSM cycle time without a significant degradation of the spatial characteristics. The method can be applied if FSM circuits are implemented using the look-up table (LUT) elements of field-programmable gate arrays (FPGAs). The resulting FSM circuit includes three logic blocks. The first block generates partial input memory functions and FSM outputs depending on maximum binary state codes and one-hot group codes. The partial codes are assigned in a way minimizing the number of arguments in the partial functions. This allows for the generation of most partial functions by single-LUT circuits. The second block generates the final values of the input memory functions and FSM outputs. This block does not require group codes to generate functions, as in CSC-based FSMs. The third block transforms maximum binary group codes into their one-hot equivalents. The proposed approach allows for a reduction in the number of series-connected LUTs in comparison with CSC-based FSMs. Due to this reduction, the temporal characteristics of an FSM circuit are improved. This paper includes an example of FSM synthesis applying the proposed method. The experiments were conducted using standard benchmark FSMs. The results of the experiments show that the proposed method allowed for an improvement in the cycle time of an average of 8.81%. Moreover, in relation to CSC-based FSMs, the LUT counts decreased by an average of 4.00%.

1. Introduction

Modern digital systems include a lot of different sequential devices [1,2]. Very often, to represent these devices, a model of a Mealy finite state machine (FSM) [3] is used. An FSM model is a starting point for creating the electrical circuit of a sequential device. In this paper, we discuss a case where the circuits of Mealy FSMs are created using the internal resources of field-programmable gate arrays (FPGAs) [4]. The choice of this basis is justified by the fact that FPGAs are a very popular tool used for creating the circuits of various digital devices [5]. Moreover, FPGAs will be used in logic design within the next thirty years [6].

As a rule, some optimization problems arise in the process of FSM design. These problems are interrelated. The following characteristics may require optimization [7,8,9]: the amount of internal resources used (occupied chip area), or performance, or power consumption. In this article, we propose a method which allows for an increase in the maximum operating frequency of an FPGA-based Mealy FSM circuit. The following internal resources are used to create the circuit: look-up table (LUT) elements, programmable flip-flops, dedicated multiplexers, a synchronization tree, programmable interconnections and programmable input–outputs [4,8,10]. We discuss a case where FSM states are encoded by composite state codes (CSCs) [11]. This approach is based on creating groups of compatible states. Both groups and states are encoded using the minimum possible number of variables. The proposed method improves performance without a significant increase in the amount of internal resources used. We use the LUT count [12] to estimate the chip area occupied by the FSM circuit.

Modern digital systems are processing larger and larger amounts of information [13]. When implementing digital systems based on FPGAs, very often increasing the system performance without a significant increase in the amount of internal resources consumed is a problem [14]. At the same time, the bottleneck may be the digital system control device, implemented in the form of an FSM. The control device generates control signals at each point in the system’s operation. Therefore, the performance of this control FSM significantly affects the performance of the digital system as a whole [15]. One of the ways to increase the performance of an FSM is a state assignment, which allows us to reduce the number of logical levels in the FPGA-based FSM circuit [16,17]. In this article, we propose a state assignment method allowing us to increase the FSM performance without a significant overhead regarding the internal resources used.

The main contribution of this paper is a novel approach improving the cycle time (the operating frequency) of LUT-based Mealy FSM circuits with composite state codes. The improvement is based on transforming the maximum binary codes of groups of compatible states into one-hot codes (OHCs). Within each group, states are encoded by maximum binary codes (MBCs). This approach leads to the development of a new architecture of an FSM circuit different from the architecture where OHCs are not used [11]. The performance improvement is related to the absence of the need to use group codes in the function assembler block. This approach allows the performance to improve for rather complex FSMs. A positive feature of this approach is the total absence of an increase in the amount of the internal resources of the FPGA chip used. Moreover, the proposed approach leads to the creation of circuits with slightly fewer LUTs than their equivalent CSC-based counterparts.

The main idea of this article is as follows: the transformation of maximum binary group codes into one-hot codes allows for a decrease in the number of partial Boolean functions generated by LUTs from the first logic level of an FSM circuit. Obviously, the code transformation requires additional LUTs and programmable interconnections (these are overheads of the proposed method), but our new method provides a decrease in the number of LUTs in the circuit assembling partial Boolean functions. This may result in a reduction in the values of LUT counts compared to the equivalent CSC-based FSMs. Our research shows that this phenomenon takes place for the proposed method.

The article includes seven sections, the first of which is this brief Introduction. Section 2 shows the peculiarities of implementing an FSM with LUTs. The analysis of FSMs with composite state codes is discussed in Section 3. An FSM architecture based on the transformation of group codes is proposed in Section 4. Section 5 is devoted to a synthesis example. Section 6 shows and analyzes the obtained experimental results. The paper also includes a Conclusion (Section 7).

2. LUT-Based FSM Design

There are a lot of approaches used for representing the behavior of a Mealy FSM [1]. The most common are state transition graphs (STGs) or state transition tables (STTs) [18]. We use both tools to represent transitions between the states from the set $A=\{a_1,\dots ,a_M\}$. The transitions depend on FSM inputs comprising the set $X=\{x_1,\dots ,x_L\}$. During the transitions, some FSM outputs are generated from the set $Y=\{y_1,\dots ,y_N\}$. As follows from these sets, an FSM has M internal states, L external inputs and N outputs. For each state, $a_m\in A$, an STG (or an STT) shows which outputs are generated under the influence of FSM inputs [1]. There are H interstate transitions represented by either an STG or STT.

The first step of FSM synthesis is a state assignment [19]. During the state assignment, the abstract states $a_m\in A$ are represented by some physical objects. These objects are binary codes, $BC\left(a_m\right)$, having R bits. The state codes consist of bits corresponding to state variables combined into a set, $T=\{T_1,\dots ,T_R\}$. Using an STT, it is possible to derive systems of Boolean functions (SBFs) representing a combinational part of an FSM circuit. The state codes $BC\left(a_m\right)$ are stored in a state code register, $RG$. The minimum width (the number of bits) is provided by so-called maximum binary codes. Their width (R) is determined as [1]

$$R=\lceil lo{g}_{2}M\rceil .$$

(1)

To change the content of the RG, three objects are used. These objects are input memory functions (IMFs), a pulse of initialization, $Start$, and a pulse of synchronization, $Clock$. As a rule, the RG consists of D flip-flops [1]. Due to this, the IMFs create a set, $D=\{D_1,\dots ,D_R\}$. If $Start=1$, then a code for the initial state $a_1\in A$ is loaded into the RG. If a certain edge of the pulse $Clock$ arises, then the bits of the IMFs are repeated in the contents of the RG.

Using an initial STT (or STG) and state codes, it is possible to derive the following SBFs [20]:

$$D=D(T,X);$$

(2)

$$Y=Y(T,X).$$

(3)

These SBFs determine the combinational part of an FSM circuit. Systems (2) and (3) determine a so-called P FSM [14]. The combinational part is implemented using some logic elements. The peculiarities of these elements significantly influence the architecture of an FSM circuit [7].

This paper is devoted to the design of FPGA-based FSMs. Modern FPGAs include a lot of LUTs, which are parts of configurable logic blocks (CLBs) [21]. In this article, we target chips produced by AMD Xilinx [4]. The CLBs from this company consist of LUTs, dedicated multiplexers and programmable flip-flops. Using multiplexers, it is possible to obtain a super-LUT having more inputs than a basic LUT. For example, there are $S_L=6$ inputs in the basic LUT from the Virtex-7 family of FPGAs [4,22]. To show the number of inputs, we denote an LUT as $S_L$-LUT. Inside a single CLB, either two seven-LUTs or one eight-LUT can be created with the help of multiplexers. These super-LUTs (SLUTs) have practically the same delay as their six-input counterparts [23]. If an SLUT must have an $S_L\ge 9$, then the internal resources of several configurable blocks are used. But such big SLUTs are significantly slower than SLUTs created inside a single CLB [23]. In this paper, we use the symbol $LUTer$ to show that a logic block is implemented using LUTs and other internal CLB resources.

Because there is a direct connection between the outputs of LUTs and the inputs of flip-flops, such blocks are implemented as registers inside CLBs. So, the state code register is a part of an LUTer. This preliminary information allows for the creation of a structural diagram of the FPGA-based FSM $U_1$ (Figure 1).

A block, $LUTerD$, implements IMFs represented by the system (2). We show the state register RG as a separate block, but in reality, this block is a part of $LUTerT$. The pulses $Start$ and $Clock$ enter $LUTerT$. The FSM outputs (3) are produced by the LUTs of the block $LUTerY$. These outputs are used by the other blocks of a digital system. So, it makes sense to reduce the delay between the arrival of FSM inputs, $x_l\in X$, and the production of FSM outputs, $y_n\in Y$.

A serious drawback is inherent in modern FPGAs: the number of basic LUT inputs ($S_L$) is really small [8]. This significantly affects the number of LUTs and their levels in the FSM circuit. If the sum of product (SOP) of a Boolean function, $f_i\in D\cup Y$, includes $N{L}_i$ literals, then the corresponding LUT-based circuit is multi-level if

$$N{L}_i>S_L.$$

(4)

To construct the SOPs of functions $f_i\in D\cup Y$, it is necessary to create a direct structure table (DST) [20]. Both STGs and STTs could be used for constructing a DST [18]. In our paper, we start synthesis using an STG.

An STG includes M vertices corresponding to FSM states. The vertices are connected by arcs determining interstate transitions. There are H arcs in an STG. The arc number $h\in \{1,\dots ,H\}$ is determined by the values of $X_h$ and $Y_h$. The conjunction of inputs $X_h$ is an input signal determining a particular transition. The symbol $Y_h$ stands for a collection of outputs (CO) generated during a particular transition.

To create a DST, it is necessary to transform an STG into the equivalent STT. An STT includes the following columns: $a_m$ (the current state), $a_S$ (a state of transition), $X_h$ (an input signal), $Y_h$ (a collection of outputs), and h (the number of interstate transitions). The first column includes the current state, the second column contains a state of transition, the third column contains an input signal determining the transition from the current state into the next state, and a CO generated during the transition, $Y_h$, is written in the fourth column.

A DST is an extension of the original STT with three additional columns. Two of the additional columns contain binary codes, $BC\left(a_m\right)$ and $BC\left(a_S\right)$. The third column includes a collection of IMFs, $D_h\subseteq D$, determining the code $BC\left(a_S\right)$ [20]. Of course, there are the same number of rows in the equivalent STT and DST.

Two types of codes are typical for FSMs: maximum binary codes and one-hot codes [24]. These approaches have both positive and negative aspects. Using MBCs leads to the minimum possible number of flip-flops into the RG, but this leads to really complex SOPs for functions (2) and (3). As a result, an FSM circuit may include a lot of LUT levels and a very sophisticated system of interconnections [7]. One-hot codes are characterized by having the maximum number of bits ($R_{OH}=M$). This leads to the use of many more flip-flops than in the case of MBC-based FSMs, but the SOPs of the IMFs and FSM outputs are rather simple.

A comparison of FSMs based on MBCs and OHCs was executed in article [25]. This comparison showed that using OHCs provides better results for FSMs with $M>16$. As was shown in [3], both LUT counts and power consumption depend significantly on the value of L. The following conclusion can be made from an analysis of the experiments conducted by the authors of paper [26]: MBC-based FSMs have better characteristics (as compared with OHC-based FSMs) if the following condition holds: $L>10$.

If condition (4) is true for a function, $f_i\in D\cup Y$, then this function should be decomposed. In this case, such a function is represented by a collection of partial Boolean functions (PBFs). To find such a representation, methods of functional decomposition (FD) [27] could be applied. To be represented by a single-LUT circuit, any partial function should depend on no more than $S_L$ arguments. Next, all LUTs generating partial Boolean functions representing the same function, $f_i\in D\cup Y$, should be combined into a multi-level circuit. It is known that applying FD-based methods results in multi-level FSM circuits having a very complicated system of interconnections [28,29].

To increase the value of the operating frequency, it is necessary to reduce the number of logic levels in an FPGA-based FSM circuit. This could be achieved, for example, by reducing the number of literals in the sum of products representing IMFs and FSM outputs. One of the ways used to solve this problem is an optimal state assignment [28]. The well-known algorithm JEDI [30] is the best example of such an approach’s efficiency. Optimization is achieved due to the placement of some state codes into the generalized cubes of an R-dimensional Boolean space. These cubes include the maximum binary codes of states for which transitions depend on the same input signals, $X_h$. To minimize the corresponding SOPs, it is necessary to use adjacent codes for these states. Moreover, this goal may be achieved by increasing the number of bits in the state codes. This leads to FSM circuits having fewer LUTs, LUT levels and interconnections than equivalent FSM circuits based on other state assignment methods. Basing on the results shown in [31], we should point out that applying JEDI leads to an improvement in LUT counts, performance and power consumption.

3. Peculiarities of FSMs Based on Composite State Assignment

Composite state assignment is proposed in paper [11]. As follows from [11], using CSCs may improve the main characteristics of FPGA-based FSM circuits: the resulting circuits occupy a smaller chip area and provide a higher operating frequency than their counterparts based on MBCs, OHCs and JEDI.

To execute the composite state assignment, it is necessary to split the set of states A by $KC$ groups of compatible states, $G^k\subseteq A$. This leads to a partition, ${\Pi }_{AC}=\{G^1,\dots ,G^{KC}\}$, with the minimum possible number of groups. The groups $G^k\in {\Pi }_{AC}$ are encoded by maximum binary codes, $CG\left(G^k\right)$, with $R_G$ bits:

$$R_G=\lceil lo{g}_{2}KC\rceil .$$

(5)

The groups are encoded using elements of the set ${\tau }_G=\{{\tau }_1,\dots ,{\tau }_{RG}\}$.

Maximum partial state codes encode states $a_m\in G^k$ inside each group, $G^k\in {\Pi }_{AC}$. If a group, $G^k\in {\Pi }_{AC}$, includes $N{S}_k$ elements, then the width of the partial codes is determined as

$$R_k=\lceil lo{g}_{2}N{S}_k\rceil .$$

(6)

To create partial state codes, $R_S$ variables are necessary. The value of $R_S$ is determined as

$$R_S=max(R_1,\dots ,R_{KC}).$$

(7)

The partial state variables determine the set ${\tau }_S=\{{\tau }_{RG+1},\dots ,{\tau }_{RG+RS}\}$. So, the total number of group and partial state variables, $R_{CC}$, is determined as

$$R_{CC}=R_G+R_S.$$

(8)

Expression (8) also determines the number of IMFs generated (and the number of flip-flops in the RG).

The concatenation of codes $CG\left(G^k\right)$ and $CS\left(a_m\right)$ determines a composite state code, $CC\left(a_m\right)$, of the state $a_m\in G^k$. So, the composite state codes are determined by the following expression:

$$CC\left(a_m\right)=CG\left(G^k\right)\ast CS\left(a_m\right).$$

(9)

In (9), we use the symbol ∗ to show the concatenation of two binary vectors.

To implement a CSC-based FSM circuit, it is necessary to find three sets representing each group, $G^k\in {\Pi }_{AC}$. The partial set of inputs $X^k\subseteq X$ includes inputs determining transitions from the states $a_m\in G^k$. This set includes $L_k$ elements. The partial set of outputs $Y^k\subseteq Y$ includes FSM outputs, $y_n\in Y$, generated during transitions from the states $a_m\in G^k$. The set of IMFs $D^k\subseteq D$ includes input memory functions generated during transitions from the states $a_m\in G^k$.

Each group, $G^k\in {\Pi }_{AC}$, should satisfy the following condition:

$$R_S+L_k\le S_L.$$

(10)

To create the partition ${\Pi }_{AC}$, it is possible to use the method proposed in [32]. This approach allows us to find a partition, ${\Pi }_{AC}$, with the minimum possible number of groups, $KC$.

So, each group determines the following PBFs:

$$D^k=D^k({\tau }_S,X^k);$$

(11)

$$Y^k=Y^k({\tau }_S,X^k).$$

(12)

To obtain the final values of functions $f_i\in D\cup Y$, it is necessary to assemble the corresponding partial functions. This is achieved using group codes. Each partial function should be multiplied by a conjunction, $G_k$, corresponding to the code $CG\left(G^k\right)$. So, the final values of SBFs (2) and (3) are determined by the following systems:

$$D=D(G_1,\dots ,G_{KC},D^1,\dots ,D^{KC});$$

(13)

$$Y=Y(G_1,\dots ,G_{KC},Y^1,\dots ,Y^{KC}).$$

(14)

As shown in [11], the functions (13) and (14) could be generated using the dedicated multiplexers of CLBs [23,33].

So, there should be two levels of logic blocks in the circuit of the CSC-based Mealy FSM $U_2$. The architecture of this circuit is determined by systems (11)–(14). The architecture of FSM $U_2$ (Figure 2) is proposed in article [11].

In FSM $U_2$, LUT-based blocks, $LUTer1$–$LUTerKC$, form the first logic level of the FSM circuit. The block $LUTerk$ generates partial functions (11) and (12), representing the group $G^k\in {\Pi }_{AC}$. The function assembler is represented by the block $LUTerY\tau$. The function assembler generates functions (13) and (14). The FSM outputs (14) enter the other blocks of the digital system. The IMFs (13) enter the flip-flops of the register RG. The outputs of the flip-flops determine both the group and partial state codes.

In [11], the results of various experiments are shown. The experiments allowed for a comparison of the characteristics of CSC-, MBC- and OHC-based FSMs. These results show that CSC-based FSMs have better LUT counts than are obtained using either MBCs or OHCs. It is very important that reducing the LUT count does not reduce the values of the maximum operating frequencies.

The best case for using CSC-based FSMs was determined in [11]. These conditions are the following:

$$R+L\ge 2S_L;$$

(15)

$$R_G+KC\le S_L.$$

(16)

If condition (15) is violated, then practically, there is no need to use FD-based approaches. The corresponding FSM circuits are mostly single-level [11]. If condition (16) is true, then there is a single level of LUTs in the function assembler circuit. If both conditions (15) and (16) hold, then there are two levels of LUTs in the circuits of $U_2$-based FSMs.

As follows from the analysis of systems (13) and (14), the violation of condition (16) is connected with the existence of a direct dependence between the functions $f_i\in D\cup Y$ and group variables ${\tau }_r\in {\tau }_G$. So, to reduce the number of levels in the function assembler circuit, it is necessary to eliminate this direct dependence. This will allow for the deletion of the conjunctions $G_1,\dots ,G_{KC}$ from functions generated by the function assembler. One of the possible approaches for solving this problem is proposed in our current article.

4. The Main Idea of the Proposed Method

In this paper, we propose a method aimed at the relocation of group variables from $LUTerY\tau$ to blocks from the first logic level. This diminishes the number of arguments in functions $f_i\in D\cup Y$. In turn, this increases the probability of obtaining a single-level circuit for the block $LUTerY\tau$. We propose encoding the groups $G^k\in {\Pi }_{AC}$ using one-hot codes. The states are still encoded by maximum binary partial codes. Now, the groups are encoded using the elements of the set ${\tau }_0=\{g_1,\dots ,g_{KC}\}$. These variables enter the blocks $LUTer1$–$LUTerKC$. This means that the variable $g_k\in {\tau }_0$ determines a literal used by all the PBFs generated by the LUTs of the block $LUTerk$. This method is focused on a situation where a single-level implementation of the function assembler circuit is impossible.

Now, the variables determining the one-hot group codes should enter the LUTs of the blocks $LUTer1$–$LUTerKC$. This leads to a change in equations for both PBFs and full functions. Now, the LUTs of the first logic level generate the following SBFs:

$$D^k=D^k(g_k,{\tau }_S,X^k);$$

(17)

$$Y^k=Y^k(g_k,{\tau }_S,X^k).$$

(18)

In this case, there are no connections between the group codes and LUTs of $LUTerY\tau$. This leads to the following SBFs representing the function assembler:

$$D=D(D^1,\dots ,D^{KC});$$

(19)

$$Y=Y(Y^1,\dots ,Y^{KC}).$$

(20)

Now, the IMFs in (19) are used to create the composite state codes. In these codes, groups are represented by maximum binary codes. To create the one-hot group codes, it is necessary to transform these maximum group codes into their one-hot equivalents. The transformation is executed by an additional code transformer block. The code transformer generates the following system of functions:

$${\tau }_0={\tau }_0\left({\tau }_G\right).$$

(21)

We name the resulting state codes mixed composite state codes (MCSCs). The term “mixed” means that the groups are represented by OHCs and the partial state codes are maximum codes. The proposed approach leads to the development of the MCSC-based Mealy FSM $U_3$. Its architecture is shown in Figure 3.

In an MCSC-based FSM, SBFs (17) and (18) are generated by the LUTs of the first logic level. These LUTs create the blocks $LUTerk(k\in \{1,\dots ,KC\left\}\right)$. The LUTs of block $LUTerY\tau$ generate the final values of the FSM outputs $y_n\in Y$ and input memory functions. The block $LUTerOH$ generates the SBF (21). As a result, one-hot group codes are created.

The block $LUTerY\tau$ includes the hidden state code register. This register is controlled by IMFs, together with signals $Start$ and $Clock$. Obviously, the equivalent FSMs $U_2$ and $U_3$ have the same amount of flip-flops in the RG. The outputs of the RG are variables from the set $\tau ={\tau }_G\cup {\tau }_S$.

The block $LUTerOH$ is a code transformer. It turns maximum binary group codes into the corresponding one-hot group codes. This block is based on an SBF (21).

To create the partition ${\Pi }_{AC}$, we use the greedy algorithm proposed in [34]. The compatible states are found using condition (10). As follows from Equations (17) and (18), it is necessary to reserve one of LUT inputs for a corresponding one-hot group variable. Obviously, this can lead to the necessity of using more than a single basic LUT for implementing a circuit for a partial Boolean function. So, it is possible that more LUTs would be necessary on the first logic level than there are for the equivalent FSM $U_2$.

Let, for each group, $G^k\in {\Pi }_{AC}$, the SOP of any partial function, $f_i^k\in D^k\cup Y^k$, depend on $M{L}_i^k$ literals. Let the following condition apply:

$$N{L}_i^k\le S_L-1.$$

(22)

In this case, including the variable $g_k\in {\tau }_0$ in any SOP does not lead to the development of a multi-level circuit. Obviously, if condition (22) is violated, then the function $f_i^k\in D^k\cup Y^k$ is represented by a multi-LUT circuit.

To diminish the number of CLBs required for implementing partial functions, $f_i^k\in D^k\cup Y^k$, it makes sense to encode some states, $a_m\in G^k$, using the adjacent partial codes $CS\left(a_m\right)$. This may be performed using, for example, a method similar to that of the algorithm JEDI [30].

For a better understanding of the novelty of the proposed method, it is necessary to show the main difference between the proposed method of state assignment and one-hot state assignment. One-hot codes include the maximum possible number of bits. This leads to a simplification of input memory functions due to a significant increase in the number of flip-flops used (compared to this number for FSMs using MBCs). An increase in the number of memory elements leads to an increase in the number of interconnections, which can significantly increase the FSM cycle time [16]. The method we propose allows for obtaining state codes where the number of bits is practically the same as for maximum binary codes. This allows for an increase in the FSM performance compared to the performance of equivalent OHC-based FSMs.

In this paper, we propose a synthesis method for the LUT-based Mealy FSM $U_3$. The synthesis process starts with an STG. The proposed method includes the following steps:

• Transforming the initial STG into a state transition table.
• Creating the partition ${\Pi }_{AC}$ of the set of states with the minimum number of groups.
• The encoding of groups $G^k\in {\Pi }_{AC}$ using maximum binary codes, $CG\left(G^k\right)$.
• The encoding of groups $G^k\in {\Pi }_{AC}$ using one-hot codes, $OCG\left(G^k\right)$.
• The encoding of states $a_m\in G^k$ using partial state codes, $SC\left(a_m\right)$.
• Creating composite state codes, $CC\left(a_m\right)$.
• Creating tables of blocks $LUTer1$–$LUTerKC$.
• Deriving SBFs (17)–(18), representing the circuits of $LUTer1$–$LUTerKC$.
• Creating a table for block $LUTerY\tau$.
• Deriving SBFs (19)–(20).
• Creating a table for block $LUTerOH$ and an SBF (21).
• Implementing the FSM circuit using the resources of a particular FPGA chip.

5. Example of Synthesis of Mealy FSM ${\mathit{U}}_{\mathbf{3}}$

Let us discuss an example of synthesis based on the proposed method. We applied this method to synthesize an LUT-based circuit for FSM A1. To obtain the circuit, we used LUTs with six inputs. The behavior of FSM A1 is represented by a state transition graph, shown in Figure 4.

Step 1. An analysis of Figure 4 shows that FSM $A1$ has the following characteristics: $M=12$, $L=7$, $N=8$ and $H=26$. This determines the sets $A=\{a_1,\dots ,a_{12}\}$, $X=\{x_1,\dots ,x_7\}$ and $Y=\{y_1,\dots ,y_8\}$. Using approach [18], we can transform the STG (Figure 4) into the equivalent STT with $H=26$ rows (

Table 1. State transition table for FSM $A1$.

${\mathit{a}}_{\mathit{m}}$	${\mathit{a}}_{\mathit{S}}$	${\mathit{X}}_{\mathit{h}}$	${\mathit{Y}}_{\mathit{h}}$	h
$a_1$	$a_4$	$x_1$	$y_1{y}_2$	1
	$a_3$	$\overline{x_1}{x}_6$	$y_3$	2
	$a_2$	$\overline{x_1}\overline{x_6}$	$y_2{y}_5$	3
$a_2$	$a_2$	$x_6$	$y_3{y}_4$	4
	$a_5$	$\overline{x_6}$	$y_6{y}_7$	5
$a_3$	$a_4$	$x_1$	$y_7$	6
	$a_2$	$\overline{x_1}{x}_7$	$y_3$	7
	$a_6$	$\overline{x_1}\overline{x_7}$	$y_1{y}_2$	8
$a_4$	$a_1$	$x_3$	$y_6$	9
	$a_3$	$\overline{x_3}$	$y_2{y}_3$	10
$a_5$	$a_6$	$x_6$	$y_3$	11
	$a_9$	$\overline{x_6}{x}_7$	$y_6{y}_7$	12
$a_6$	$a_4$	1	$y_3{y}_5$	13
$a_7$	$a_8$	$x_3$	$y_1{y}_7$	14
	$a_5$	$\overline{x_3}{x}_2$	$y_2$	15
	$a_{11}$	$\overline{x_3}\overline{x_2}$	$y_3$	16
$a_8$	$a_9$	1	$y_2{y}_4$	17
$a_9$	$a_8$	$x_7$	$y_3$	18
	$a_7$	$\overline{x_7}{x}_7$	$y_1{y}_2$	19
$a_{10}$	$a_{11}$	$x_3$	$y_2$	20
	$a_5$	$\overline{x_3}{x}_4$	$y_5{y}_7$	21
	$a_{12}$	$\overline{x_3}\overline{x_4}$	$y_1{y}_5$	22
$a_{11}$	$a_5$	$x_4$	$y_2{y}_6$	23
	$a_{10}$	$\overline{x_4}$	$y_3$	24
$a_{12}$	$a_5$	$x_4$	$y_3$	25
	$a_1$	$\overline{x_4}$	–	26

).

Each arc of the STG represents the pair of vertices $\langle a_m,a_S\rangle$. The hth row of the STT corresponds to the hth arc of the STG. The columns of the STT include the following variables: $a_m$ is the current state (the arc’s beginning); $a_S$ is a state of transition (the arc’s end); $X_h$ is an input signal written above the hth arc (it determines the transition from $a_m$ into $a_S$); $Y_h$ is a collection of outputs written above the hth arc $(Y_h\subseteq Y)$; h is the number of transitions $(h\in \{1,\dots ,H\left\}\right)$. The transition from an STG to the equivalent STT is transparent and straightforward [18].

Step 2. This step is executed using the greedy algorithm proposed in [34]. We have $S_L=6$. Applying the method from [34] gives us the partition ${\Pi }_{AC}=\{G^1,G^2,G^3\}$ with $KC=3$.

The states $a_m\in A$ are distributed among the groups in the following way: $G^1=\{a_1,a_2,a_3,a_5\}$, $G^2=\{a_4,a_6,a_7,a_{11}\}$ and $G^3=\{a_8,a_9,a_{10},a_{12}\}$. So, for each group, we have $N{S}_k=4$. The group $G^1$ determines the partial sets $X^1=\{x_1,x_6,x_7\}$ and $Y^1=\{y_1,\dots ,y_7\}$. The group $G^2$ determines the partial sets $X^2=\{x_2,x_3,x_4\}$ and $Y^2=\{y_1,y_2,y_3,y_5,y_6,y_7\}$. The group $G^3$ determines the partial sets $X^3=\{x_2,x_4,x_7\}$ and $Y^3=\{y_1,\dots ,y_5,y_7,y_8\}$. Using (6), we can obtain $R_k=2(k\in \{1,2,3\})$. Using (7), we can obtain the value $R_S=2$. We have $L_k=3$ for each group, $G^k\subset A$. Taking into account variables $g_k$, we can find that a single LUT with six inputs is enough to generate any partial function.

Step 3. We have $KC=3$. Using (5), we can obtain $R_G=2$. This determines the set ${\tau }_G=\{{\tau }_1,{\tau }_2\}$. Now, we can form the set ${\tau }_S=\{{\tau }_3,{\tau }_4\}$. There is no influence of the group codes on the number of LUTs in the blocks $LUTer1$–$LUTerKC$. Due to this, we can encode the groups in the following way: $CG\left(G^1\right)=00$, $CG\left(G^2\right)=01$ and $CG\left(g^2\right)=10$.

Step 4. Obviously, three bits is enough to create the one-hot group codes. This determines the set ${\tau }_0=\{g_1,g_2,g_3\}$. Let us encode the groups in the following way: $OCG\left(G^1\right)=100$, $OCG\left(G^2\right)=010$ and $OCG\left(G^2\right)=001$.

Step 5. In complex FSMs, it makes sense to encode states using the algorithm JEDI for optimal state encoding. This can lead to the optimization of the partial SOPs for output functions.

But in this very simple example, we encode states in the basic way. The method is the following: the smaller the subscript of a state, the more zeros its partial code includes. Using this approach, we can assign the following partial codes (Figure 5).

Step 6. In the Karnaugh map (Figure 5), we show these partial codes together with the maximum binary group codes. So, this map shows the composite state codes.

So, steps 1–6 are executed. Using the obtained codes, we can create tables representing the blocks LUTer1–LUTer3.

Step 7. In the discussed case, LUTer1 is represented by

Table 2. Table for $LUTer1$ of FSM $A1$.

${\mathit{a}}_{\mathit{m}}$	$\mathbf{CS}\left({\mathit{a}}_{\mathit{m}}\right)$	${\mathit{a}}_{\mathit{S}}$	$\mathbf{CC}\left({\mathit{a}}_{\mathit{S}}\right)$	${\mathit{X}}_{\mathit{h}}$	${\mathit{D}}_{\mathit{h}}$	${\mathit{Y}}_{\mathit{h}}$	h
$a_1$	00	$a_4$	0100	$x_1$	$D_2$	$y_1{y}_2$	1
		$a_3$	0010	$\overline{x_1}{x}_6$	$D_3$	$y_3$	2
		$a_2$	0001	$\overline{x_1}\overline{x_6}$	$D_4$	$y_2{y}_5$	3
$a_2$	01	$a_2$	0001	$x_6$	$D_4$	$y_3{y}_4$	4
		$a_5$	0011	$\overline{x_6}$	$D_3{D}_4$	$y_6{y}_7$	5
$a_3$	10	$a_4$	0100	$x_1$	$D_2$	$y_7$	6
		$a_2$	0001	$\overline{x_1}{x}_7$	$D_4$	$y_3$	7
		$a_6$	0101	$\overline{x_1}\overline{x_7}$	$D_2{D}_4$	$y_1{y}_2$	8
$a_4$	11	$a_6$	0101	$x_6$	$D_2{D}_4$	$y_3$	9
		$a_9$	1001	$\overline{x_6}$	$D_1{D}_4$	$y_6{y}_7$	10

, LUTer2 by

Table 3. Table for $LUTer2$ of FSM $A1$.

${\mathit{a}}_{\mathit{m}}$	$\mathbf{CS}\left({\mathit{a}}_{\mathit{m}}\right)$	${\mathit{a}}_{\mathit{S}}$	$\mathbf{CC}\left({\mathit{a}}_{\mathit{S}}\right)$	${\mathit{X}}_{\mathit{h}}$	${\mathit{D}}_{\mathit{h}}$	${\mathit{Y}}_{\mathit{h}}$	h
$a_4$	00	$a_1$	0000	$x_3$	–	$y_6$	1
		$a_3$	0010	$\overline{x_3}{x}_6$	$D_3$	$y_2{y}_3$	2
$a_6$	01	$a_4$	0100	1	$D_2$	$y_3{y}_5$	3
$a_7$	10	$a_8$	1000	$x_2$	$D_1$	$y_7$	4
		$a_5$	0011	$\overline{x_3}{x}_2$	$D_3{D}_4$	$y_3$	5
		$a_{11}$	0111	$\overline{x_3}\overline{x_2}$	$D_2{D}_3{D}_4$	$y_1{y}_2$	6
$a_{11}$	11	$a_5$	0011	$x_4$	$D_3{D}_4$	$y_2{y}_6$	7
		$a_{10}$	1000	$\overline{x_4}$	$D_1$	$y_3$	8

, and LUTer3 by

Table 4. Table for $LUTer3$ of FSM $A1$.

${\mathit{a}}_{\mathit{m}}$	$\mathbf{CS}\left({\mathit{a}}_{\mathit{m}}\right)$	${\mathit{a}}_{\mathit{S}}$	$\mathbf{CC}\left({\mathit{a}}_{\mathit{S}}\right)$	${\mathit{X}}_{\mathit{h}}$	${\mathit{D}}_{\mathit{h}}$	${\mathit{Y}}_{\mathit{h}}$	h
$a_8$	00	$a_9$	1001	1	$D_1{D}_4$	$y_2{y}_4$	1
$a_9$	01	$a_8$	1000	$x_7$	$D_1$	$y_3$	2
		$a_7$	0110	$\overline{x_7}$	$D_2{D}_3$	$y_1{y}_2$	3
$a_{10}$	10	$a_{11}$	0111	$x_3$	$D_2{D}_3{D}_4$	$y_2{y}_8$	4
		$a_5$	0011	$\overline{x_3}{x}_4$	$D_3{D}_4$	$y_5{y}_7$	5
		$a_{12}$	0011	$\overline{x_3}\overline{x_2}$	$D_1{D}_3{D}_4$	$y_1{y}_5$	6
$a_{12}$	11	$a_5$	0011	$x_4$	$D_3{D}_4$	$y_3$	7
		$a_1$	0000	$\overline{x_4}$	–	–	8

. These tables have the columns $a_m$, $CS\left(a_m\right)$, $a_S$, $CC\left(a_S\right)$, $X_h$, $Y_h$, $D_h$ and h. For each state, the columns $a_m$, $a_S$, $X_h$ and $Y_h$ are the same as they were in the initial STT (Table 1). The column $D_h$ is created using the composite state codes from Figure 5.

Step 8. The outcome of the previous step provides information which can be used for creating the SOPs of partial IMFs (13) and partial microoperations (14). This is performed using the partial state codes, inputs $x_l\in X$ and one-hot group variables. There are two stages in creating PBFs. The first stage is deriving the partial Boolean functions (11) and (12) from the tables of blocks LUTer1–LUTerKC. The second stage is multiplying each term of SOPs (11) and (12) by the corresponding one-hot group variables. So, the PBFs representing $LUTerk$ are multiplied by $g_k(k\in \{1,\dots ,KC\})$. The resulting expressions represent SBFs (13) and (14).

For our example, we show only the SOPs resulting from the partial functions $y_1^1$ and $D_1^1$, $y_1^2$ and $D_1^2$, and $y_1^3$ and $D_1^3$. These partial SOPs are represented by the following equations:

$$\begin{array}{c}{D}_1^1=F_{10}^1=g_1{\tau }_3{\tau }_4\overline{x_6};\hfill \\ D_1^2=F_4^2\vee F_8^2=g_2{\tau }_3\overline{{\tau }_4}{x}_3\vee g_2{\tau }_2{\tau }_4\overline{x_4};\hfill \\ D_1^3=F_1^3\vee F_2^3\vee F_6^3=g_3\overline{{\tau }_3}\overline{{\tau }_4}\vee g_3\overline{{\tau }_3}{\tau }_4{x}_7\vee g_3{\tau }_3\overline{{\tau }_4}\overline{x_3}\overline{x_4}.\hfill \end{array}$$

(23)

$$\begin{array}{c}{y}_1^1=F_1^1\vee F_8^1=g_1\overline{{\tau }_3}\overline{{\tau }_4}{x}_1\vee g_1{\tau }_3\overline{{\tau }_4}\overline{x_1}\overline{x_7};\hfill \\ y_1^2=F_4^2=g_2{\tau }_3\overline{{\tau }_4}{x}_3;\hfill \\ y_1^3=F_3^3\vee F_6^3=g_3\overline{{\tau }_3}{\tau }_4\overline{x_4}\vee g_3{\tau }_{3}v\overline{{\tau }_4}\overline{x_3}\overline{x_4}.\hfill \end{array}$$

(24)

In these systems, variables $F_h^k$ are product terms created from the lines, h, of tables representing blocks LUTer1–LUTerKC. We hope there is a transparent connection between SBFs (23) and (24) and Table 2, Table 3 and Table 4.

Step 9. To obtain the final values of both the IMFs and FSM outputs, it is necessary to create a table for the function assembler. This is a table for the block $LUTerY\tau$. The table contains $R_{CC}+N$ rows. This table provides information about the disjunctions of PBFs. Using this information, the final values of the FSM outputs and IMFs are obtained. There are the following columns in this table: $f_i$, 1, …, $KC$. The row number i includes the function $f_i\in D\cup Y$. The column number k corresponds to the partial function $f_i^k\in D^k\cup Y^k$. If the function $f_i\in D\cup Y$ is generated by the block $LUTerk$, then there is a value of 1 at the intersection of the column k and row i. Otherwise, the symbol 0 is written at this intersection. In the discussed case, the block $LUTerY\tau$ is represented by

Table 5. Table for $LUTerY\tau$ of Mealy FSM $A1$.

${\mathit{f}}_{\mathit{i}}$	1	2	3	${\mathit{f}}_{\mathit{i}}$	1	2	3	${\mathit{f}}_{\mathit{i}}$	1	2	3	${\mathit{f}}_{\mathit{i}}$	1	2	3
$D_1$	1	1	1	$D_4$	1	1	1	$y_3$	1	1	1	$y_6$	1	1	0
$D_2$	1	1	1	$y_1$	1	1	1	$y_4$	1	0	1	$y_7$	1	1	1
$D_3$	1	1	1	$y_2$	1	1	1	$y_5$	1	1	1	$y_8$	0	0	1

.

Step 10. Using Table 5 allows us to obtain a system of disjunctions representing functions $f_i\in D\cup Y$. In the discussed case, some IMFs are represented by SBF (25), and some outputs are represented by SBF (26):

$$D_1=D_1^1\vee D_1^2\vee D_1^3;\dots ;D_4=D_4^1\vee D_4^2\vee D_4^3;$$

(25)

$$y_1=y_1^1\vee y_1^2\vee y_1^3;\dots ;y_7=y_7^1\vee y_7^2\vee y_7^3;y_8=y_8^3$$

(26)

Obviously, using a similar approach, we can obtain the SOPs of all the functions from SBFs (19) and (20).

Step 11. To construct SBF (21), it is necessary to create a table for the block $LUTerOH$. This table includes the columns $G^k$, $CG\left(G^k\right)$, $OCG\left(G^k\right)$, ${\tau }_0$ and k. In the discussed case, the code transformer is represented by

Table 6. Table for $LUTerOH$ of Mealy FSM A1.

${\mathit{G}}^{\mathit{k}}$	$\mathbf{CG}\left({\mathit{G}}^{\mathit{k}}\right)$	$\mathbf{OCG}\left({\mathit{G}}^{\mathit{k}}\right)$	${\mathit{\tau }}_0$	k
$G^1$	00	100	$g_1$	1
$G^2$	01	010	$g_2$	2
$G^3$	10	001	$g_3$	3

.

The following SBF is derived from Table 6:

$$g_1=\overline{{\tau }_1}\overline{{\tau }_2};g_2={\tau }_2;g_3={\tau }_1.$$

(27)

As follows from SBF (27), there is only a single LUT in the circuit of $LUTerOH$. The variables $g_2$ and $g_3$ are exactly the same as group variables ${\tau }_2$ and ${\tau }_1$, respectively.

Step 12. To implement the FPGA-based circuit, it is necessary to apply some industrial CAD tools. These tools are necessary to execute the technology mapping [3,35]. The most popular tools are Vivado [36] and Quartus [37]. We do not discuss this step for our example.

To analyse the efficiency of the proposed approach compared to some other known methods, we conducted a lot of experiments. We compared the characteristics of $U_3$-based FSMs with the characteristics of their counterparts based on maximum binary state codes, one-hot state codes and composite state codes. In the next section, we show the results of our experiments and their analysis.

6. Experimental Results

We conducted experiments to compare four characteristics of $U_3$-based FSM circuits with the characteristics of FSM circuits based on other state assignment methods. These characteristics were the cycle times, maximum operating frequencies, LUT counts and area–time products. As an example of an MBC-based method, we use Vivado’s Auto method [36]. Let us point out that the number of code bits used by Auto may exceed the minimum value determined by (1). Vivado’s one-hot method [36] was used as an example of OHC-based state assignment. Also, we compared our approach with the algorithm JEDI [30], which is an MBC-based algorithm creating cubes covering the codes of some states [3]. Finally, we executed a comparison of $U_3$-based FSM circuits with their $U_2$-based counterparts [11].

In the experiments, we used benchmark FSMs from the well-known library LGSynth93 [38]. There are 48 Mealy FSMs (benchmarks) in the library. The benchmarks are represented in the KISS2 format. These benchmarks have a wide range of basic characteristics (numbers of states, inputs, outputs and transitions). A lot of scientists have been using these benchmarks as a basis for the comparison of various design methods [39,40,41]. The characteristics of the benchmarks are shown in

Table 7. Characteristics of benchmarks from LGSynth93 [38].

Benchmark	L	N	H	M	L + R
bbara	4	2	60	10	8
bbsse	7	7	56	16	11
bbtas	2	2	24	6	5
beecount	3	4	28	7	6
cse	7	7	91	16	11
dk14	3	5	56	7	6
dk15	3	5	32	4	5
dk16	2	3	108	27	7
dk17	2	3	32	8	5
dk27	1	2	14	7	4
dk512	1	3	15	15	5
donfile	2	1	96	24	7
ex1	9	19	138	20	14
ex2	2	2	72	19	7
ex3	2	2	36	10	6
ex4	6	9	21	14	10
ex5	2	2	32	9	6
ex6	5	8	34	8	8
ex7	2	2	36	10	6
keyb	7	7	170	19	12
kirkman	12	6	370	16	16
lion	2	1	11	4	4
lion9	2	1	25	9	6
mark1	5	16	22	15	9
mc	3	5	10	4	5
modulo12	1	1	24	12	5
opus	5	6	22	10	9
planet	7	19	115	48	13
planet1	7	19	115	48	13
Pma	8	8	73	24	13
s1	8	7	106	20	13
s1488	8	19	251	48	14
s1494	8	19	250	48	14
s1a	8	6	107	20	13
s27	4	1	34	6	7
s298	3	6	1096	218	11
s386	7	7	64	13	11
s510	19	7	77	47	25
s8	4	1	20	5	7
s820	18	19	232	25	23
s832	18	19	245	25	23
sand	11	9	184	32	16
shiftreg	1	1	16	8	4
sse	7	7	56	16	11
styr	9	10	166	30	14
tma	8	9	44	20	13

. The last column of this table includes the sum of the number of FSM inputs and the minimum number of bits in the maximum binary state codes. We used this additional column to select benchmarks where structural decomposition made sense.

To conduct the experiments, we used a platform including the FPGA chip from the Virtex-7 family. This was a VC709 Evaluation Platform (xc7vx690tffg1761-2) [22]. The CLBs used included basic LUTs with six inputs $(S_L=6)$. To implement a CLB-based circuit of $LUTerY\tau$, the dedicated multiplexers could be used. Each CLB included four basic LUTs and three dedicated multiplexers. We use thed industrial CAD package Vivado v2019.1 (64-bit) [36] to execute the step of technology mapping. Using the Vivado reports, we created four tables showing the results of the conducted experiments.

Each Boolean function, $f_i\in D\cup Y$, depended on $N{L}_i$ arguments. If condition (4) was violated for all IMFs and FSM outputs, then the circuit of FSM $U_1$ consisted of exactly $R+N$ LUTs. So, each function, $f_i\in D\cup Y$, was generated by a single-level circuit. In this case, the $U_1$-based FSM circuit possessed the best spatial and temporal characteristics. This model provided the minimum values of the LUT count and propagation time. So, if condition (4) is violated for all input memory functions and FSM outputs, there is no need to use either functional or structural decomposition. Obviously, the states may be encoded in a way minimizing the power consumption [24,27].

As follows from the results of the experiments shown in article [11], condition (4) only held for some benchmarks. These benchmarks had the following common property:

$$L+R>2S_L.$$

(28)

For FSMs satisfying (28), it made sense to replace $U_1$-based FSMs with FSMs with composite state assignment. We could use either the $U_2$ or $U_3$ models. For FPGAs from the Virtex 7 family, the basic LUT had $S_L=6$ inputs. Due to this, in our research, we only used benchmarks for which $L+R>12$. The experimental results are shown in

Table 8. Results of experiments (cycle time, nsec).

FSM	MB	OH	JEDI	${\mathit{U}}_2$	${\mathit{U}}_3$	L + R
ex1	6625	7155	5654	3620	3410	16
kirkman	7073	6494	6382	4359	3993	18
planet	7535	7535	5344	3491	3321	14
planet1	7535	7535	5344	3491	3321	14
pma	6841	6841	5888	4080	3708	14
s1	6830	7361	6363	4233	3902	14
s1488	7220	7579	6362	4384	4217	15
s1494	6694	6861	6085	4420	4178	15
s1a	6520	5669	5911	4521	4252	15
s510	5629	5629	5512	4581	3729	27
s820	6579	6529	5663	4419	3687	25
s832	6863	6526	5754	4553	3966	25
sand	8623	8623	7885	4424	4130	18
styr	7267	7697	6866	3719	3505	16
tma	6102	6766	6092	3557	3525	13
Total	103,937	104,800	91,106	61,851	56,843
Percentage, %	18,285	18,437	16,028	10,881	100

(cycle times, nanoseconds),

Table 9. Results of experiments (maximum operating frequency, MHz).

BM	MB	OH	JEDI	${\mathit{U}}_2$	${\mathit{U}}_3$	L + R
ex1	15,094	13,976	17,687	27,623	29,327	16
kirkman	14,138	15,400	15,668	22,941	25,042	18
planet	13,271	13,271	18,714	28,648	30,108	14
planet1	13,271	13,271	18,714	28,648	30,108	14
pma	14,618	14,618	16,983	24,512	26,972	14
s1	14,641	13,585	15,716	23,624	25,631	14
s1488	13,850	13,194	15,718	22,812	23,711	15
s1494	14,939	14,575	16,434	22,623	23,935	15
s1a	15,337	17,640	16,917	22,118	23,521	15
s510	17,765	17,765	18,142	21,831	26,817	27
s820	15,200	15,316	17,658	22,628	27,123	25
s832	14,571	15,323	17,378	21,965	25,213	25
sand	11,597	11,597	12,682	22,603	24,216	18
styr	13,761	12,992	14,564	26,892	28,532	16
tma	16,388	14,780	16,414	28,114	28,371	13
Total	218,441	217,303	249,389	367,582	398,627
Percentage, %	5480	5451	6256	9221	100%

(maximum operating frequency, MHz),

Table 10. Results of experiments (LUT count).

BM	MB	OH	JEDI	${\mathit{U}}_2$	${\mathit{U}}_3$	L + R
ex1	70	74	53	40	38	16
kirkman	42	58	39	31	30	18
planet	131	131	88	77	72	14
planet1	131	131	88	77	72	14
pma	94	94	86	72	69	14
s1	65	99	61	55	52	14
s1488	124	131	108	87	84	15
s1494	126	132	110	85	82	15
s1a	49	81	43	43	40	15
s510	48	48	32	26	28	27
s820	88	82	68	48	46	25
s832	80	79	62	50	52	25
sand	132	132	114	91	87	18
styr	93	120	81	71	69	16
tma	45	39	39	31	29	13
Total	1318	1431	1072	884	850
Percentage, %	15,506	16,835	12,612	10,400	10,000

(LUT counts) and

Table 11. Results of experiments (area–time products).

BM	MB	OH	JEDI	${\mathit{U}}_2$	${\mathit{U}}_3$	L + R
ex1	46,376	52,948	29,966	14,481	12,957	16
kirkman	29,707	37,662	24,891	13,513	11,980	18
planet	98,711	98,711	47,024	26,878	23,914	14
planet1	98,711	98,711	47,024	26,878	23,914	14
pma	64,304	64,304	50,639	29,373	25,582	14
s1	44,396	72,874	38,814	23,281	20,288	14
s1488	89,531	99,288	68,711	38,138	35,427	15
s1494	84,343	90,566	66,934	37,572	34,259	15
s1a	31,949	45,918	25,418	19,441	17,006	15
s510	27,019	27,019	17,639	11,910	10,441	27
s820	57,895	53,539	38,509	21,213	16,960	25
s832	54,904	51,556	35,677	22,763	20,624	25
sand	113,823	113,823	89,891	40,260	35,927	18
styr	67,582	92,365	55,617	26,402	24,183	16
tma	27,459	26,387	23,760	11,027	10,222	13
Total	9367	10,257	6605	3631	3237
Percentage, %	28,939	31,687	20,406	11,219	10,000

(area–time products).

Table 8, Table 9, Table 10 and Table 11 include the following columns: FSM (names of benchmark FSMs); MB (experimental results for MBC-based FSMs); OH (experimental results for OHC-based FSMs); JEDI (experimental results for FSMs with state codes generated by JEDI); $U_2$ (experimental results for FSMs with composite state codes); and $U_3$ (experimental results obtained for our new approach). The results of the summation of values from the corresponding columns are shown in the row “Total”. The row “Percentage” shows the percentage of the summarized characteristics of the investigated FSM circuits compared to those of $U_3$-based FSMs.

The main goal of the proposed method was increasing the performance of LUT-based FSM circuits in relation to the circuits of FSMs based on composite state codes. So, the most important characteristic was the cycle time (or operating frequency). The values for the cycle times were obtained directly from Vivado reports. These values are shown in Table 8.

As follows from Table 8, the proposed method made it possible to obtain LUT-based FSM circuits with shorter cycle times than those of the other studied FSMs. As can be seen from Table 8, $U_3$-based FSMs had the following improvements in cycle times: (1) 82.25% compared with MBC- based FSMs; (2) 84.37% compared with OHC-based FSMs; (3) 60.28% compared with JEDI-based FSMs; and (4) 8.81% compared with $U_2$-based FSMs.

An analysis of Table 8 shows that under some conditions, our method always produced circuits that were slightly faster than the circuits of the equivalent FSMs with composite state codes, but the level of improvement depended on the value of $L+R$. For example, we found $L+R=13$ for the benchmark $tma$. As follows from Table 8, our method provided an improvement of around 1%. Next, we found $L+R=27$ for the benchmark $s510$. As follows from Table 8, our method provided an improvement of around 19%. As we compare the results for each benchmark, we can make the following conclusion: the improvement achieved by replacing composite state codes with mixed CSCs increased with the growth of the value $L+R$.

We think that this phenomenon was related to the difference in the number of CLBs connected in series in the circuit creating the input memory functions and outputs of Mealy FSMs. As the value of $L+R$ increased, the number of consecutive CLBs grew faster for CSC-based FSMs than for the equivalent MCSC-based FSMs.

Using the values for the cycle time allowed us to create Table 9. This table shows the values of the maximum operating frequencies.

As follows from Table 9, the proposed method produced FPGA-based FSM circuits with higher frequencies than the other studied FSMs. As can be seen from Table 9, $U_3$-based FSMs achieved the following improvements in the frequency: (1) 45.2% compared with Auto-based FSMs; (2) 55.49% compared with OHC-based FSMs; (3) 37.44% compared with JEDI-based FSMs; and (4) 7.89% compared with $U_2$-based FSMs. The reasons for this state of affairs have already been considered in the analysis of the data from Table 8. We will not repeat them.

The main goal of the proposed approach is to improve the temporal characteristics of LUT-based FSM circuits in relation to the circuits of the equivalent CSC-based FSMs, but sometimes, it is very important that an increase in the frequency does not result in a significant deterioration of the spatial characteristics. These characteristics depend significantly on the number of LUTs used (LUT count) [12]. A comparison of the values of the LUT counts for FSM circuits based on various state assignment methods is shown in Table 10.

As follows from Table 10, the proposed approach led to the creation of FSM circuits that required fewer LUTs than the other investigated methods. Our method had an average improvement of (1) 55.06% compared with Auto-based FSMs, (2) 68.35% compared with OHC-based FSMs, (3) 26.12% compared with JEDI-based FSMs, and (4) 4% compared with FSMs based on composite state codes.

Sometimes, it is very important to reach a balance between the spatial and temporal characteristics of FSM circuits [19]. This balance can be estimated using some integral evaluations of the quality of a digital circuit. One of the main integral evaluations involves the product of the area occupied by a circuit and its performance (area–time product) [12]. In the case of LUT-based circuits, the area is estimated using a characteristic such as the LUT count [12]. Obviously, the performance is represented by the value of the cycle time. The smaller the value of this integral characteristic is, the higher the quality of the circuit (and the better the balance between the spatial and temporal characteristics). Using Vivado reports, we created Table 11, including values of the area–time products obtained for the circuits of the benchmark FSMs.

As follows from Table 11, the proposed method made it possible to obtain LUT-based FSM circuits with smaller values for the area–time products compared with their $U_2$-based counterparts. The $U_2$-based FSMs were inferior in relation to the equivalent $U_3$-based FSMs (the difference was 12.19%). Also, our method provided significantly better results than those for the other methods studied. The improvement was 189.39% in relation to MB-based FSMs, 216.87% in relation to OH-based FSMs and 104.06% in relation to JEDI-based FSMs.

An analysis of the results of the experiments carried out allowed us to draw the following conclusion regarding the equivalent $U_2$- and $U_3$-based FSMs. If condition (28) holds, then our method is always an improvement over the method based on composite state codes [11]. Under this condition, our method provides a shorter cycle time and requires fewer LUTs than the method based on CSCs. So, mixed composite state codes can be viewed as a good alternative to maximum binary CSCs.

7. Conclusions

One of the basic problems associated with LUT-based FSM design is the problem of improving the temporal characteristics of the produced circuits. Under certain conditions, the best spatial characteristics are provided if FSM states are encoded by composite state codes [11]. This method is based on finding a partition of the set of states according to the minimum number of groups of compatible states. In the composite state codes proposed in article [11], there was the minimum possible number of bits in the group codes. Within each group, states were encoded by partial maximum binary codes. To increase the maximum operating frequency of CSC-based FSM circuits, we propose encoding groups using one-hot codes.

As the conducted experiments show, the proposed method provides a reduction in the value of the cycle time compared with that of the equivalent CSC-based FSMs. This reduction is possible for rather complex FSMs for which the total number of inputs and state variables is at least twice the number of inputs of the base LUT. For example, for FSMs whose circuits are implemented using six-input LUTs, an improvement in the temporal characteristics is possible if $L+R>12$. The proposed method has the following positive feature: an increase in performance (an increase in the maximum operating frequency) is accompanied by a slight decrease in the LUT count.

As shown through the experiments, the results of which were given in the previous section, the proposed method can only be applied to an FSM for which condition (28) is met. If the sum of digits of codes with the appropriate number of logical conditions does not exceed twice the number of LUT inputs, then the use of this method does not make sense. In this case, it is advisable to use the other methods of state coding discussed in this article. An analysis of the tables containing the results of the studies shows that the improvements from the application of the proposed method increase as the value of the parameter $L+R$ increases.

So, the proposed state assignment method allows for an increase in the FSM performance without increasing the amount of internal chip resources used. The results of the investigations show that the proposed method can be used for designing rather complex FSMs.