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A new state assignment method focusing on Mealy finite state machines (FSMs) is proposed. The proposed codes are an alternative to composite state codes (CSCs). CSCs are represented as concatenations of group codes and partial state codes. Both group and partial state codes are maximum binary codes. We propose encoding groups using one-hot codes. The main goal of this method is improving the value of the FSM cycle time without a significant degradation of the spatial characteristics. The method can be applied if FSM circuits are implemented using the look-up table (LUT) elements of field-programmable gate arrays (FPGAs). The resulting FSM circuit includes three logic blocks. The first block generates partial input memory functions and FSM outputs depending on maximum binary state codes and one-hot group codes. The partial codes are assigned in a way minimizing the number of arguments in the partial functions. This allows for the generation of most partial functions by single-LUT circuits. The second block generates the final values of the input memory functions and FSM outputs. This block does not require group codes to generate functions, as in CSC-based FSMs. The third block transforms maximum binary group codes into their one-hot equivalents. The proposed approach allows for a reduction in the number of series-connected LUTs in comparison with CSC-based FSMs. Due to this reduction, the temporal characteristics of an FSM circuit are improved. This paper includes an example of FSM synthesis applying the proposed method. The experiments were conducted using standard benchmark FSMs. The results of the experiments show that the proposed method allowed for an improvement in the cycle time of an average of 8.81%. Moreover, in relation to CSC-based FSMs, the LUT counts decreased by an average of 4.00%. Full article