Design and Implementation of a High-Reliability Underwater Wireless Optical Communication System Based on FPGA

Abstract

In order to meet the reliability requirements of communication for underwater resource exploration, this study develops an underwater wireless optical communication (UWOC) system utilizing a blue semiconductor laser as the light source. At the receiver, a fully digital automatic gain control (AGC) module, implemented on a field-programmable gate array (FPGA), is designed to mitigate signal fluctuations induced by underwater turbulence. Digital filtering techniques, including median filtering (MF) and bilateral edge detection filtering (BEDF), are also employed to improve signal demodulation reliability. An improved Reed–Solomon (RS) coding scheme is further adopted to significantly reduce the bit error rate (BER). The design of a highly reliable UWOC system was realized based on the above techniques. The system’s performance was evaluated across a range of signal-to-noise ratios (SNRs) and bubble intensities. The results show that the digital AGC module can provide a gain range from −3.2 dB to 16 dB, adapting to varying signal strengths, which greatly bolsters the system’s resilience against underwater turbulence. Filtering techniques and RS coding further enhance the system’s immunity to interference and reduce the system BER. Communication experiments were conducted over various distances under three distinct water quality conditions. The results demonstrate that, within the detection range of the avalanche photodiode (APD), the system consistently maintained a BER below 3.8 × 10⁻³ across all water types, thereby confirming its high reliability. In clear seawater, the system demonstrated reliable information transmission over a 10 m distance at a data rate of 10 Mbps, achieving a BER of 2 × 10⁻⁸. Theoretical calculations indicate that the maximum transmission distance in clear seawater can reach 111.35 m.

1. Introduction

The exploration and utilization of the underwater environment have long been a significant focus in multiple fields, including marine biology, oceanography, national defense, and telecommunications [1,2]. However, effective communication in underwater environments is significantly hindered by the complex and dynamic nature of aquatic conditions [3,4,5]. Currently, underwater wireless communication is primarily achieved through three main approaches: radio frequency (RF) communication, acoustic communication, and optical communication [6]. RF communication’s effective communication range is limited due to the rapid attenuation of electromagnetic wave signals caused by the high conductivity of seawater. In addition, RF communication devices are usually large in size and not suitable for covert operation, which further limits their application in specific scenarios [7,8]. In contrast, acoustic waves experience less attenuation in aquatic environments and can support stable communication over long distances. As a result, acoustic communication has become the main mode of underwater communication today [9]. However, acoustic communication is constrained by several inherent limitations, including relatively low data transmission rates and significant propagation delays. These limitations make it less suitable for applications requiring high-bandwidth or real-time communication capabilities [10]. With the increasing demand for underwater communication systems, both RF and acoustic communications are facing challenges in meeting the requirements for high-bandwidth and real-time data transmission. In this context, UWOC has emerged as a promising alternative [11,12]. UWOC employs light waves for data transmission, offering significant advantages including high-bandwidth, low-latency, and high-speed communication capabilities [13,14,15]. The attenuation of light in underwater environments exhibits significant wavelength dependence. Experimental studies have demonstrated that the blue–green spectrum, particularly within the wavelength range of 470–525 nm, experiences substantially lower attenuation compared to other spectral regions. This characteristic makes the blue–green band the optimal wavelength range for UWOC [16]. In recent years, UWOC has garnered considerable attention owing to its distinctive advantages. Significant advancements in system performance have been achieved through comprehensive research efforts, encompassing channel modeling, modulation techniques, channel coding, and hardware design [17,18,19,20,21].

In terms of modulation, conventional techniques, including on–off keying (OOK) and pulse-position modulation (PPM), have been widely adopted by UWOC systems [22]. OOK is widely adopted in optical communication systems due to its simple hardware implementation, low resource consumption, high bandwidth efficiency, and low power consumption. However, its performance is significantly limited by poor interference resistance under low SNR conditions. In contrast, PPM demonstrates superior noise immunity by encoding information through temporal pulse positioning. Nevertheless, this modulation scheme imposes stringent requirements on timing synchronization accuracy. Even minor timing jitter or synchronization errors can substantially degrade the BER performance. Furthermore, the hardware implementation of PPM systems presents greater complexity compared to OOK-based systems [23,24,25]. Recently, advanced modulation techniques including quadrature amplitude modulation (QAM), orthogonal frequency division multiplexing (OFDM), and multiple-input multiple-output (MIMO) have been implemented in UWOC systems to enhance data transmission rates and spectral efficiency [26,27,28]. However, these techniques require substantial hardware resources, making their implementation challenging in resource-constrained underwater environments [29,30].

Regarding channel coding, forward error correction (FEC) codes, particularly RS codes and low-density parity-check (LDPC) codes, have been extensively employed in UWOC systems. RS codes have high error correction capability, but their high computational complexity may lead to large delays [31]. LDPC codes excel in performance close to the Shannon limit, but their FPGA implementation is difficult [32]. Additionally, Turbo codes and convolutional codes have been utilized in UWOC systems and their implementation complexity is also much higher than RS codes, so there is a need to explore better hardware implementations for scenarios with high BER requirements [33,34].

In hardware implementation, FPGAs have emerged as the preferred platform for UWOC systems due to their flexibility, high performance, and parallel computing. Unlike communication systems based on signal generators achieving Gbps rates, FPGA-based implementations offer enhanced real-time performance and miniaturization, significantly improving practical applicability [35,36]. Considering the power supply constraints in underwater environments, research efforts should focus on low-power design and resource optimization in hardware implementation. The development of novel power supply solutions that enable self-powered systems is crucial to meet the requirements for prolonged underwater operations [37]. Furthermore, the performance of optical components, including light source types, receiver sensitivity, and beam divergence angle, significantly influences the communication distances and data rates of UWOC systems [38,39,40,41].

The above analysis indicates that, despite significant advancements in the development of UWOC systems, the complex characteristics of underwater environments, particularly optical turbulence, suspended particulate matter, and multipath propagation effects continue to present substantial challenges to achieving reliable communication and extending operational range [42,43]. Even when the transmission wavelength is selected within the blue–green spectral window, the optical signal still undergoes considerable attenuation and multipath fading due to absorption and scattering effects. Previous studies, however, have been limited in their specificity regarding hardware implementation design and have not effectively addressed the noise and interference inherent in underwater environments. Furthermore, these studies have paid insufficient attention to optimizing resources, energy consumption, and delay in FPGA implementations, ultimately impacting the practicality of the systems.

In 2022, T. Ren et al. [35] reduced the burr interference generated by the threshold judgment during OOK demodulation by moving-average filtering, and achieved a transmission distance of 20 m and a BER of 10⁻⁶ at 5 Mbps in clear seawater. In 2024, A. Huang et al. [36] suppressed light intensity flicker caused by underwater turbulence by employing a board-level AGC circuit and combined it with the Altera Reed Solomon IP core for error correction, and achieved a 22 Mbps rate with a BER of 2.467 × 10⁻⁴ in a 12 m underwater channel. While these studies have addressed certain aspects of the existing challenges, limitations persist in hardware resource optimization, environmental adaptability, and optical signal attenuation mitigation, indicating substantial potential for further improvement.

To address these challenges, this paper proposes a series of innovative solutions: firstly, a fully digital AGC system is designed to effectively resist light intensity flicker; secondly, BEDF and MF are used to eliminate burrs and spike noise, respectively, which significantly improves the system’s ability to resist turbulence and noise interference; in addition, the RS coding IP is implemented in hardware, which is optimized to significantly reduce the resource loss and decoding delay; finally, a dedicated collimated beam expanding system is designed to significantly reduce the beam divergence angle and extend the communication distance. Based on these techniques, a practical UWOC system with high reliability and low power consumption is realized in this paper and comprehensively evaluated in the laboratory environment. The experimental results show that the system reliability is better than several recent implementations based on FPGA platforms, and the results are shown in

Table 1. Comparison of system performance.

Date	Light	Rate	Distance	BER
2022 [35]	LED	5 Mbps	20 m	~10−6
2023 [44]	LD	25 Mbps	10 m	1.0063 × 10−2
2023 [45]	LED	4 Mbps	12 m	~10−3
2024 [36]	LED	22 Mbps	12 m	2.467 × 10−4
This work	LD	10 Mbps	10 m	2 × 10−8

.

The rest of the paper is organized in the following manner: Section 2 provides a comprehensive description of the system architecture and optimized design methodologies. Section 3 details the experimental setup, presents the results, and analyzes the system performance. Section 4 concludes the paper by summarizing the findings, discussing potential application domains, highlighting system limitations, and outlining future research directions.

2. System Architecture and Design Principles

The overall system architecture is illustrated in Figure 1 and mainly consists of signal processing modules (data preprocessing, channel encoding, and modulation/demodulation) implemented on the FPGA, as well as peripheral devices including a digital-to-analog converter (DAC), analog-to-digital converter (ADC), optical antennas, and laser driver circuit. During the communication process, the information intended for transmission is initially written into the DDR by the processing system (PS). Subsequently, the programmable logic (PL) reads and packages the data via the advanced extensible interface (AXI) protocol, completing the data preprocessing. The packetized data are then encoded using RS coding to improve robustness in the complex underwater environment. To generate the baseband signal for modulation, the encoded data are first converted from parallel to serial format and then scrambled to enable the detection of hopping edges, ensuring accurate bit synchronization at the receiver. The scrambled data are modulated and converted to an analog signal using the DAC; this then drives the laser through the laser driver circuit. The laser beam is expanded and collimated before being transmitted through the underwater channel. At the receiver, the APD detector captures the optical signal. The output signal is sampled by the ADC. The sampled signal is demodulated and decoded, and then written back to the DDR via the AXI protocol. The processed data are read by the PS and displayed on a host computer, completing the entire underwater communication process. The specific design principles and analysis of the data preprocessing, channel coding, and modulation/demodulation schemes are as follows.

2.1. Data Preprocessing

In order to ensure the consistency of the data structure during data transmission, data preprocessing is employed in the system design with the following workflow: First, the overall data are extracted from the DDR using the AXI protocol and then packetized using a specific packet architecture, as illustrated in Figure 2. To clearly define the boundaries of the data packet, a start marker (header) is inserted at the start of the data, while an end marker (end of frame) is appended at the end. Then, the overall data are segmented based on the state machine design, with each set consisting of 239 bytes of data to be encoded. The frame header “A5” is added before each frame as a start flag, which is detected by the encoding module to start the encoding program. The “96” indicates the end of the encoding process for a data set. The “RS_code” in Figure 2 represents a data segment after RS encoding, which has a complete structure facilitating subsequent transmission and decoding processes.

2.2. RS Coding Design Based on FPGA

Afterwards, the packet data after data preprocessing is channel-coded to enhance the robustness of the system and to reduce the BER. In this study, an improved RS (255,239) coding module implemented on an FPGA platform is proposed. The module utilizes redundant information generated during the coding process for error correction. During the encoding process, a set of data to be encoded is considered as the coefficients of an information polynomial. The information polynomial is expressed as

$$u(x)=u_{238}{x}^{238}+u_{237}{x}^{237}+\cdots +u_{1}x+u_0,$$

(1)

where $u_0$ to $u_{238}$ are the information to be encoded. The RS (255,239) encoding in this design is defined over the Galois field $GF\left(2^8\right)$, with the generator polynomial selected as

$$g(x)={\displaystyle {\prod }_{i=1}^{i=16}(x+{\alpha }^i)},$$

(2)

The polynomial is expanded in the Galois field to obtain the generator polynomial coefficients $g_0$ to $g_{16}$; the systematic encoding is completed through the calculation as

$$r(x)=(u(x)x^{16}){\mathrm{mod}}_{g(x)},$$

(3)

The encoding circuit is illustrated in Figure 3 [46]. The information to be encoded is sequentially input into the circuit. At the start of encoding, “Switch1” is connected to the “ur” terminal, which is responsible for inputting $u(x)$ to participate in the subsequent Galois field operations. Meanwhile, “Switch2” is connected to the “u(x)” terminal, which is responsible for outputting the data to be encoded ($d_1$ to $d_{239}$) sequentially. After the information input is completed, the two switches are toggled, and the generated parity check symbols ($R_0$ to $R_{15}$) are appended to the last 16 bytes of the data. These parity symbols are then output sequentially along with the original information up to $d_{255}$, completing the encoding process.

To simplify the hardware implementation complexity, the present design employs a Python 3.8 script for data preprocessing, which implements various operations in the Galois field. Equation (2) is expanded as follows:

$$\begin{array}{cc}\hfill g(x)=& x^{16}+118x^{15}+52x^{14}+103x^{13}+31x^{12}\hfill \\ & +104x^{11}+126x^{10}+187x^9+232x^8\hfill \\ & +17x^7+56x^6+183x^5+49x^4\hfill \\ & +100x^3+81x^2+44x+79\hfill \end{array},$$

(4)

where $g_0$ to $g_{16}$ are the coefficients of the polynomials $x^0$ to $x^{16}$. During the encoding process, the coefficients of the generator polynomial remain unchanged. This characteristic is exploited to optimize the hardware implementation of Equation (3). Taking $u_0$ as an example, the Galois field multiplication of $u_0$ and the generator polynomial $g_0$ can be generated using script code. The precomputed results can be expressed as

$$y_{(8bit)}=g_0\otimes u_0\left\{\begin{array}{l}y[0]={x_0}^{\wedge }{x_2}^{\wedge }{x}_5\\ y[1]={x_0}^{\wedge }{x_1}^{\wedge }{x_3}^{\wedge }{x}_6\\ y[2]={x_0}^{\wedge }{x_1}^{\wedge }{x_4}^{\wedge }{x_5}^{\wedge }{x}_7\\ y[3]={x_0}^{\wedge }{x_1}^{\wedge }{x}_6\\ y[4]={x_1}^{\wedge }{x_5}^{\wedge }{x}_7\\ y[5]={x_2}^{\wedge }{x}_6\\ y[6]={x_0}^{\wedge }{x_3}^{\wedge }{x}_7\\ y[7]={x_1}^{\wedge }{x}_4\end{array}\right.,$$

(5)

where $u_0=\left[x_7{x}_6{x}_5{x}_4{x}_3{x}_2{x}_1{x}_0\right]$ and $g_0=79={\left(01001111\right)}_2$. When implementing the hardware circuit, the Galois field multiplication can be converted into XOR operations on the individual bits of $u_0$. This approach works well to reduce the encoding resources and complexity.

The RS decoding process is efficiently executed on an FPGA through a finite-state machine design, encompassing key computational steps such as syndrome computation, application of the Berlekamp-Massey (BM) algorithm, execution of the Chien search algorithm, and utilization of the Forney algorithm [47,48,49]. As depicted in Figure 4, the decoding journey begins with the incoming data $r(x)$ being stored in an FIFO buffer. Concurrently, the Syndrome module diligently computes the syndromes $S_0$ to $S_{15}$, which are essential for error detection. The syndromes serve as a pivotal trigger for state transitions within the finite-state machine. In the fortunate scenario where $S_j$ is equal to zero, it signifies the absence of transmission errors, allowing for the immediate and direct output of the error value “$Y_i=0$” without starting the error correction algorithm by turning on the “Switch”. However, when non-zero syndromes are encountered, it cues the initiation of the error correction algorithm. The BM algorithm is then engaged to derive the error locator polynomial ${\delta }_x$ from the syndromes. Armed with this polynomial, the Chien search algorithm systematically identifies the precise locations $X_i$ of errors within the data stream. Subsequently, the Forney algorithm is applied to pinpoint the error value $Y_i$. In the final stage of the process, the Error Corrector module meticulously applies the XOR operation between the error values and the data extracted from the FIFO. This operation rectifies the errors, yielding the decoded data $c(x)$. The use of syndromes to gauge the system’s state enables the system to bypass unnecessary decoding computations when no errors are present, thereby enhancing both the speed and efficiency of the decoding process.

2.3. Optimization of OOK Demodulation Design

The implementation of OOK modulation on FPGA platforms offers significant advantages, including simplicity, efficiency, and low resource utilization, making it ideal for resource-constrained environments. Its binary nature minimizes power consumption, while its inherent robustness enhances performance in challenging conditions. Furthermore, FPGA flexibility enables seamless integration of OOK with signal processing tasks like error correction and filtering, simplifying system design and improving overall performance. This combination provides a cost-effective solution, reducing hardware costs while leveraging FPGA versatility for scalable system development [12,35,36,44]. However, OOK performance can be degraded by turbulence, noise, and interference in complex environments [50]. To address these challenges, this study optimizes OOK demodulation and incorporates digital signal processing techniques, including AGC, MF, and BEDF, to enhance the system’s anti-interference capabilities.

First, a fully digital AGC system was designed to reduce the impact of optical intensity scintillation on demodulation sensitivity, which is caused by underwater turbulence, bubbles, and suspended particles. The technique employs a closed-loop feedback mechanism, whose core function is to dynamically adjust the system gain by calculating the average energy of the sampled signal through a sliding average filter and comparing it to a predefined threshold. This process ensures that the output signal amplitude remains within the desired range. The system’s principle is illustrated in Figure 5. First, the analog signal output from the APD is converted from analog to digital by a 12-bit ADC. The converted digital signal “Adc_data” is then processed by the absolute value module to obtain the amplitude information of the signal. Next, the absolute value “Abs_data” is fed into an average accumulator, which averages 32 samples under the control of a counter to achieve sliding-average filtering and obtain the average value of the signal amplitude. This average value “Ave_data” is subsequently compared with a preset threshold “Aim_avg”. The result of the comparison is used to calculate a dynamic gain coefficient. In order to smooth this gain coefficient, it is fed into a filter to obtain a smoothed feedback coefficient. This feedback coefficient “Gain factor” is used to make closed-loop dynamic adjustments to the “Adc_data” for automatic gain control. This FPGA-based solution offers greater flexibility and portability than analog AGC. By precisely realizing these operations on the FPGA, the algorithm parameters can be flexibly adjusted to suit different application requirements and environmental conditions. In addition, the programmability of FPGAs allows for rapid reconfiguration and upgrading of the system without the need to change the hardware, thus increasing the adaptability and maintainability of the system.

After that, the output signal “AGC_data” after gain control is demodulated; in order to prevent spike noise and burr interference in demodulation, we designed MF and BEDF for processing, respectively, and the optimized demodulation structure is shown in Figure 6. First, the input signal “Din” undergoes rectification and low-pass filtering. The spike noise within the envelope signal of the filtered output is removed through MF, with the filter window size selected as 9 based on simulation results. The process of implementing MF on an FPGA begins with the low-pass filtered output signal, which is first fed into a shift register that stores the most recent nine samples of data ($d_1$ to $d_9$). These samples are then divided into three groups, each containing three samples. Within each group, the samples are sorted to determine the maximum, median, and minimum values. Next, the median value from each group is selected to form the final output “Dout”. This process effectively filters out outliers, such as spiky noise, thereby smoothing the signal and improving its quality. To ensure accurate signal reconstruction, an adaptive joint decision threshold is employed for signal judgment. This threshold is initially configured according to the channel conditions and dynamically adjusted in real time using a 255-bit shift register to compute the mean value. The calculated average is then weighted and integrated with the initial threshold, ensuring reliable evaluation even when the initial sample size is limited. The judged signal is subsequently processed by BEDF. The implementation of the BEDF involves the detection of jumps in the input signal “Judge_data”, which is performed by a jump detection unit to identify the rising and falling edges of the signal. For each detected transition (rising edge $t_1$ and falling edge $t_2$), the time interval $\mathrm{\Delta }t$ between them is measured by count, and this time interval $\mathrm{\Delta }t$ is compared with a preset threshold value $T$ to determine the validity of the signal change. If $\mathrm{\Delta }t$ is less than $T$, the signal change may be caused by noise; if $\mathrm{\Delta }t$ is greater than or equal to $T$, the signal change is considered valid. Based on this judgment, an output signal is controlled by a switching circuit to ensure that the signal is allowed to pass only when $\mathrm{\Delta }t$ ≥ $T$. This filters out burrs that do not satisfy the bit duration requirement and ensures the accuracy and reliability of the signal. Finally, the demodulated signal is output under the control of the “Bit_sync” clock generated by the Bitsync module.

3. Underwater Communication Experiment and Discussion

To verify the performance of the constructed UWOC system, an underwater laser communication test platform was established in a laboratory environment, as shown in Figure 7a. The platform primarily consisted of a transmitter, a receiver, and an underwater channel. The underwater channel was simulated by a 2 m water tank, and the communication distance was extended to 10 m by employing reflective mirrors. A specific proportion of sea salt was added to pure water until the salinity reached 35 ppt to simulate clear seawater. The experimental water temperature was maintained at room temperature. The operating current and attenuation intensity were adjusted so that the output optical power was 23.3 mW, and the received optical power was measured to be 17.15 mW transmitted through a 2 m water tank. The attenuation coefficient of the water body, c = 0.153 m⁻¹, was calculated from the Beer–Lambert law, described in Equation (6) as

$${\tau }_c={\exp }^{-cZ},$$

(6)

where ${\tau }_c$ is the ratio of transmitted optical power to received optical power; $c$ represents the total loss coefficient; and $Z$ denotes the transmission distance. The water quality was tested and categorized as class I, with a total loss factor of 0.151 m⁻¹ [51]. The experiments were conducted in water of this quality.

The transmitter of the system consists of a host computer, a development board, a laser, and a collimated beam spreading optical antenna, as shown in Figure 7b. The host computer acts as a signal source and generates the data to be transmitted. The data are then transferred for processing to the development board, which consists of an FPGA core board, a driver circuit, and a DAC. The FPGA performs the critical signal processing tasks, while the DAC converts the processed digital signals into analog signals, which are then used by the driver circuit to light up the laser. The laser beam is then expanded and collimated by an optical antenna and transmitted through the underwater channel. The FPGA adopts ZYNQ7020 from Xilinx (San Jose, CA, USA), and the power supply comes from the 12 V voltage of the power adapter, which is transformed into 5 V voltage by the DC-DC chip (model JW5060) to supply power to the system, or the 5 V of the USB serial port at the PS end is directly connected to the PC to supply power to the system. To ensure that the analog signals generated by the DAC meet the laser’s driving requirements, a dedicated laser driver circuit was designed. This circuit maintains the input signal’s bandwidth while increasing the output current to a maximum of 3 A. The modulation rate can reach up to 150 MHz. This design provides the laser with the necessary band-width and current level for the drive signal, thereby guaranteeing the stability of laser operation. The 10-bit DAC is realized by using the 3PD5651E, which has a sampling rate of 125 Msps, and the OSRAM PLPT9 450LB_E laser (OSRAM, Munich, Germany) is selected as the light source, which has an optical power of 5 W and a typical wavelength of 447 nm to match the underwater low-absorption window. Considering the absorption and scattering properties of seawater, too large a beam divergence angle will lead to the problem of energy dispersion and a significant reduction of the communication distance; a set of optical antennas is designed in this study. These antennas consist of a fast-axis collimator, a slow-axis collimator, and a Galilean beam expander. This combination effectively collimates and expands the laser beam, reducing the divergence angles in the fast and slow axes from 0.855 rad and 0.157 rad to 0.315 mrad and 0.180 mrad, respectively. This improvement in beam collimation enhances the system’s performance by minimizing energy dispersion.

The receiver, as shown in Figure 7c, first uses optical devices for optical signal processing. The processed optical signal is converted into an electrical signal using the APD130A2 avalanche photodetector produced by Thorlabs (Newton, NJ, USA). This detector has a receiving threshold of −46 dBm and a response range of 200–1000 nm. The APD output signal is then detected by an oscilloscope to show a modulation frequency of 10 MHz and sampled by the ACM9238 at a sampling rate of 65 Msps, then converted to a digital signal and demodulated, decoded, and otherwise processed by the FPGA. Finally, the signal processed by the FPGA is displayed by the host computer through the AXI protocol. After the system construction was completed, picture transmission was tested at a communication rate of 10 Mbps. Figure 8a shows the diagram of the upper computer sending the picture. The picture information is processed by the transmitter and modulated onto the laser beam for transmission through a 10 m underwater channel. Figure 8b illustrates the received picture on the upper computer at the receiver end. The results demonstrate that the system successfully achieved reliable picture information transmission. After completing the information transmission test, the performance of each signal processing module in the system was further tested and analyzed in depth, and the results were as follows.

3.1. Verification of Demodulation Optimization

First, the fully digital AGC performance was tested; the output can be stabilized by adjusting the AGC gain coefficient by a certain amount, as shown in Figure 9. The blue curve depicts the original sampling signal, with fluctuations increasing in line with bubble strength. The red curve, on the other hand, represents the output signal after AGC module control. To avoid amplifying noise, the digital AGC gain is maintained within 0.2–2 V. Specifically, when the sampling signal Din is 0.2 V, the AGC gain adjusts to 1.26 V; when Din is 1.98 V, the AGC gain output stabilizes at 1.37 V. These results indicate that the AGC module can consistently maintain an output level of approximately 1.37 V, with a gain adjustment range spanning from −3.2 dB to 16 dB, thereby meeting the system’s gain control requirements.

Subsequently, the MF performance in the demodulation structure was analyzed, and the results are presented in Figure 10. The X-axis represents the sampling time, while the Y-axis indicates the relative magnitude of the digital signal in arbitrary units (a.u.). The figure demonstrates the effect of median filtering on the envelope signal. The blue dashed line corresponds to the original envelope signal, which exhibits significant spike noise. In contrast, the red solid line represents the median-filtered signal, where the spike noise has been effectively suppressed, resulting in a smoother waveform. This filtering process enhances the reliability of subsequent threshold calculations, thereby improving the overall demodulation performance.

The effect of BEDF is illustrated in Figure 11. The smooth envelope signal after median filtering is shown in black, while the red dashed line represents the threshold value calculated by the joint judgment threshold module. The judgment signal, output under a 50 MHz system clock, is represented by the blue curve. This signal exhibits obvious burrs, which can lead to incorrect demodulation outputs under the bit synchronization signal. After the BEDF process, these burrs are effectively removed, as indicated by the red dashed line.

3.2. BER Testing of the System

In order to meet the system’s demand for real-time BER detection, this study designed a BER test module at the digital end and verified the effects of AGC, filtering, and RS coding on the system’s BER based on this design. At the transmitter, a pseudo-random sequence (PRS) of 10,000,000 bits was generated using a linear feedback shift register (LFSR), and used as the original data for transmission testing. At the receiver end, the corresponding random sequence was generated in the same manner and compared with the received data to calculate the system’s BER.

Firstly, the BER of the system was evaluated under various SNRs. Sampled signals at various SNRs are illustrated in Figure 12. As the SNR decreases, the received signal waveforms become increasingly distorted. Specifically, when the SNR is reduced from 25 dB to 3 dB, the waveform of the sampled signal progressively deteriorates, but the data stream remains consistent. When the SNR is further decreased to 2 dB, the sampled signal begins to distort, making it difficult to recover the original signal using signal processing techniques.

The BER test results are illustrated in Figure 13. At high SNRs, the BER of the three systems remains nearly identical and is well below the forward error correction (FEC) threshold of 3.8 × 10⁻³. When the SNR is below 15 dB, filtering can reduce the BER by one order of magnitude. Additionally, the incorporation of RS coding further reduces the BER by another order of magnitude. When the SNR is reduced to 3 dB, the BER of the original system becomes higher than the FEC, which fails to satisfy the communication requirements. Then, after the filtering process, the BER is reduced to 2.98 × 10⁻⁴, which is reduced by two orders of magnitude. With RS coding applied, the BER is further reduced to 5.38 × 10⁻⁵, and the reliability of the system is improved. These results demonstrate that the designed MF, BEDF, and RS coding effectively reduce the system BER. When the SNR is reduced to 2 dB, the sampled signal begins to exhibit errors. At this point, the filtering no longer effectively reduces the BER, which rises above the FEC threshold. The BER reaches 0.0472, exceeding the RS code’s error correction capability of 0.0314. Consequently, the system BER increases to 0.0326, and the effectiveness of RS coding diminishes.

To further verify the effectiveness of improving system reliability through filtering and coding, the system’s ability to resist underwater turbulence was tested under an SNR of 25 dB. As shown in Figure 7a, a gas pump was used to generate bubbles of varying intensities to simulate underwater turbulence. The gas pump features three flow rate settings and four bubble channels, with a maximum flow rate of 8 L/min, allowing for precise control of bubble intensity. The bubble intensity is calculated from the current flow and number of channels. The experiments were carried out by simulating different turbulence conditions. The results are shown in Figure 14. The system’s BER is 2 × 10⁻⁸ at a bubble intensity of 0 L/min, which represents the actual performance of image transmission under pure seawater. As the bubble intensity increases, the BER of all systems rises approximately linearly. However, the use of filtering and RS coding significantly reduces the system’s BER under different bubble intensities. At a bubble intensity of 3 L/min, the original system’s BER approaches the FEC. As the bubble intensity increases to 6 L/min, communication becomes unreliable without filtering. Filtering enhances reliability by nearly a factor of two, bringing the system closer to the FEC threshold. With RS coding applied, the system maintains reliable transmission even at a bubble intensity of 7 L/min. When the bubble intensity further increases and the BER exceeds the error correction capability of RS coding, the system’s BER dramatically increases. These experiments demonstrate that MF and BEDF effectively enhance system reliability, particularly in complex environments.

The performance of the fully digital AGC system was then evaluated in simulated clear seawater, and the results are shown in Figure 15. Under different bubble strengths, the design of the AGC module leads to a significant reduction of the BER, and the effect is more obvious as the bubble strength increases. Without AGC adjustment, the system’s BER increases faster between 4 and 5 L/min bubble strength, indicating that it exceeds the error correction limit of RS coding. The BER is even higher than the FEC at 5 L/min, with a BER of 1.85 × 10⁻², which makes it difficult to realize reliable communication. The BER of the system decreases to 6.8 × 10⁻⁵ after gain control, demonstrating a significant improvement in its anti-turbulence capability.

Finally, the corresponding experiments were analyzed under three different water quality conditions: clear seawater (I), coastal seawater (II), and turbid harbor water (III). Clear seawater, characterized by a high amount of dissolved particles, contrasts with coastal seawater, which has higher turbidity due to increased dissolved and suspended particles, and turbid harbor water, which exhibits the highest turbidity and severely limits light propagation due to strong absorption and scattering effects. The total link loss coefficients, attributed to underwater absorption and scattering, are 0.151 m⁻¹, 0.339 m⁻¹, and 2.195 m⁻¹ for clear seawater, coastal seawater, and turbid harbor water, respectively [51]. To simulate coastal seawater, natural seawater was collected from the coastal area of Dushu Lake in Suzhou. The seawater was filtered to remove large particles while retaining its natural constituents. Fine sediment particles (such as clay and silt) and organic matter (such as algae and detritus) were then added to the filtered seawater to adjust the concentration and achieve the desired water quality level. The proportions of these additions were carefully controlled to ensure that the total attenuation coefficients, calculated using Equation (6), were 0.147 m⁻¹, 0.333 m⁻¹, and 2.114 m⁻¹, respectively, which approximately simulate the three water qualities. The communication was tested at distances ranging from 2 m to 10 m under three simulated water qualities, and the results are illustrated in Figure 16. With the increase in transmission distance, the system’s BER increases approximately linearly. When the transmission distance reaches 8 m in class III water quality, it is difficult for the receiver to detect the laser signal and the communication link is broken. The results show that when the received light intensity is within the detectable range of the APD, the BER of the system is lower than the FEC in the three types of water quality, which satisfies the demand for reliable communication in a wide range of underwater environments.

3.3. Calculation of System Transmission Distance

Due to limitations in the experimental conditions, the present study employed theoretical calculations to assess the transmission distance, incorporating factors such as system link loss, system loss, and the geometric loss of the optical antenna. Taking clear seawater as an example, with a loss coefficient of 0.151 m⁻¹ and assuming a transmission distance of 100 m, the underwater channel loss is calculated to be −65.58 dBm by Equation (6). Due to the size limitation of the receiving aperture that prevents the entire laser beam from entering the detector, there is an additional loss of optical energy known as the geometric loss of the optical antenna. This loss can be calculated as follows [51]:

$${\tau }_{geo}=10\lg {\left({\displaystyle \frac{D}{2\times Z\times \tan (\frac{\theta }{2})+D}}\right)}^2,$$

(7)

where ${\tau }_{geo}$ represents the geometric loss; $D$ is the spot exit diameter; $Z$ is the transmission distance; and $\theta$ is the divergence angle. The geometric loss is calculated to be −3.98 dB for a laser spot diameter of 54 mm and a beam divergence angle of 0.315 mrad under 100 m underwater transmission conditions. The additional loss of the system due to spectral attenuation is −6 dBm. The total loss is calculated to be −75.56 dBm. The semiconductor laser provides a power of 5 W, equivalent to 37 dBm. Therefore, after 100 m of underwater transmission, the total power of the detector is −38.56 dBm. The experimental results demonstrate that system in this study maintains reliable communication when the received light intensity approaches the APD sensitivity threshold of −46 dBm. As a result, the received power still meets the test criteria for reliable transmission after a distance of 100 m underwater. Subsequently, utilizing the reception threshold of the APD detector as a reference, the maximum transmission distances for the system under various water quality conditions were calculated. The results indicated distances of 111.35 m for clear seawater, 49.60 m for coastal seawater, and 7.66 m for turbid harbor water, respectively.

3.4. Analysis of FPGA Resource Utilization

The system is designed to support bidirectional communication, with all functional modules implemented on the FPGA’s logic resources. The resource utilization after synthesis is illustrated in Figure 17a. As shown in the figure, the look-up table (LUT) utilization is 17.99%, which is relatively high compared to other resources. This is primarily attributable to the complex computational tasks involved in the system, including AXI protocol data interactions, filtering operations, RS code encoding/decoding, and other intricate logic functions. To reduce LUT resource consumption, algorithm optimization can be applied to refine computation-intensive modules, eliminating redundant logic and minimizing unnecessary LUT usage. Additionally, a pipelined architecture can be implemented to distribute LUT resource requirements more evenly, alleviating bottlenecks caused by centralized logic operations. The DSP utilization is relatively low at 4.09%, achieved by converting a significant portion of multiplication and division operations into shift-and-addition operations, thereby reducing the demand for DSP resources. The BRAM utilization is only 2.5%, contributing to the overall stability of the system. This low utilization is achieved by storing data in DDR mode, which greatly reduces the reliance on the PL-side BRAM. However, this approach shifts part of the resource burden to the PS side, leveraging the unique advantages of the ZYNQ7020 development board. Twenty percent of the system’s IO resources are allocated for data interaction between the FPGA and peripherals, such as the ADC and DAC. The flexible configuration of IO resources in the FPGA ensures efficient and accurate data transfer between the digital and analog domains. Furthermore, the abundant IO resources provide scalability for future system expansion, enabling the integration of additional peripherals for underwater environmental monitoring, such as temperature sensors and other sensing modules.

The system power consumption is illustrated in Figure 17b, which comprises two primary components: dynamic and static energy consumption. The dynamic energy consumption dominates, accounting for 92% of the total, while the static energy consumption constitutes the remaining 8%. Within the dynamic energy consumption, the PS module is the largest contributor, consuming 85% of the total power. This is primarily due to data interactions between the host computer and the PS side, as well as extensive storage tasks on the DDR. The overall power consumption of the system is maintained at a low level of 1.921 W. To further reduce system power consumption, dynamic voltage and frequency scaling (DVFS) technology can be used on the PS side to dynamically adjust the operating voltage and frequency according to the load conditions, thus significantly reducing power consumption during low-activity periods, while gated clocks can be used on the PL side to apply gated clocks on the programmable logic (PL) side to deactivate unused logic modules during idle states, thus further reducing power consumption.

Further comparative analysis between the optimized RS coding module and the official IP reveals significant improvements in resource efficiency (LUTs and registers) and low power consumption, while maintaining competitive throughput, as illustrated by the metrics listed in Figure 18. By converting Galois field multiplication into bitwise XOR operations, particularly during the encoding process, the hardware complexity is effectively reduced. Specifically, the proposed design achieves a 16.4% reduction in LUT usage, a 31.2% reduction in register usage, and a 35.7% reduction in power consumption, with only a 15.2% decrease in throughput, from 151 MHz to 128 MHz. However, considering the actual communication rate of the system, this design not only meets the requirements but also provides considerable redundancy margin.

The receiver state machine effectively reduces decoding delay, particularly for error-free data, thereby significantly minimizing decoding time and enhancing decoding efficiency. As shown in Figure 19, at 100 MHz clock frequency, the design outputs the decoding result “decode_y” at 2655 ns, which is 2090 ns earlier than the 4745 ns timing required by the official IP for its “decode_y1” output. This improvement is equivalent to a reduction of 209 clock cycles and results in a substantial decrease in overall decoding time.

4. Conclusions

This study designs and implements a 10 Mbps UWOC system based on an FPGA. By optimizing the demodulation architecture, introducing MF, BEDF, RS (255,239) encoding, and fully digital AGC technology, the system’s anti-interference capability and reliability are significantly enhanced. The system achieves an image transmission with a bit error rate as low as 2 × 10⁻⁸ over a 10 m simulated clear seawater and demonstrates stability under three different water quality conditions. The application of beam expansion and collimation techniques enables the system to reach a maximum transmission distance of 111.35 m in clear seawater.

This research provides important theoretical and technical references for the design of high-reliability, low-power, and low-latency underwater laser communication systems, with broad application prospects. For instance, it can be deployed in submarine underwater links, underwater node information collection and transmission, information interaction between ships and underwater divers, underwater Internet of Things, and autonomous underwater vehicles (AUVs), among other fields. Additionally, it can be combined with network protocols and relay schemes to establish underwater communication local area networks, enabling multi-point cooperative communication [43,52]. The optical antenna design adopted by the system provides strong support for long-distance optical communication. The fully digital AGC system, MF, BEDF, and RS code signal processing modules developed in this study are encapsulated as IP cores, enabling seamless future technological upgrades and system migration.

However, this experiment also has certain limitations. Firstly, there is a significant difference between the laboratory test environment and actual marine conditions. Complex currents, suspended particles, and biological interferences may all affect the system performance. Secondly, due to the limitations of laboratory conditions, the theoretical transmission distance of 113.5 m remains to be verified. Additionally, the system was powered by a PC during testing, the limited energy capacity of underwater devices and the difficulty of battery replacement make power supply a critical challenge for future applications. It is necessary to further consider the power supply issues in practical applications. To overcome these limitations, future research will involve encapsulating the system for communication testing in real-world environments and further optimizing the design based on the results. Concurrently, effective power supply solutions will be explored, including advanced energy harvesting technologies to achieve self-powered systems [37,53]. Furthermore, integrating machine learning and artificial intelligence could lead to more advanced system reliability designs [54]. Through interdisciplinary collaboration and continuous technological innovation, UWOC systems are poised to achieve significant advancements in reliability, transmission rate, and range of applications, ultimately emerging as a cornerstone of underwater communication and unlocking new possibilities for marine exploration and resource utilization.